JPH04247388A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To offer a dynamic semiconductor memory device in which the reduction of readout potential difference by a capacitive coupling noise between neighboring bit lines is reduced. CONSTITUTION:This semiconductor memory device includes plural word lines WL3, WL4 and plural bit lines BL11-BL22. Each sense amplifier SA15 detects potential difference between the bit lines BL 15 and BL17 comprising each pair of bit lines(BL15, BL17). Each pair of bit lines(BL15, BL17) is comprised of every second bit lines BL15, BL17. The bit line 15 on one side of each pair of bit lines (BL15, BL17) is provided so as to intersect to the bit line BL16 of adjacent another pair of bit lines (BL16, BL18) at a prescribed intersection part, and the bit line BL17 on the other side so as to intersect to another bit line BL18 of the pair of bit lines (BL16, BL 18) at the prescribed intersection part.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to preventing malfunctions during reading in dynamic semiconductor memory devices.

0002

2. Description of the Related Art FIG. 10 is a diagram showing the configuration of the main parts of a conventional dynamic semiconductor memory device.

In FIG. 10, a plurality of bit lines BL1 to
A plurality of word lines WL1 and WL2 intersect with BL8.
is located. Bit lines BL1 to BL8 are bit line pairs (BL1, BL2), (BL3, BL4), (BL
5, BL6) and (BL7, BL8). Memory cells MC1, MC3, MC5,
MC7 is provided. Word line WL2 and bit line BL2
, BL4, BL6, BL8.
, MC4, MC6, and MC8 are provided. Each memory cell includes a capacitor C for storing information and a transfer gate TR made of an N-channel MOS transistor. Transfer gate TR is connected between capacitor C and a corresponding bit line. The gate of transfer gate TR is connected to a corresponding word line.

Furthermore, dummy word lines DWL1 and DWL2 are arranged to intersect with bit lines BL1 to BL8. Dummy word line DWL1 and bit lines BL1, BL
3. A dummy memory cell DM is installed at the intersection with BL5 and BL7.
C1, DMC3, DMC5, and DMC7 are provided. Dummy word line DWL2 and bit lines BL2, BL4,
A dummy memory cell DMC2 is located at the intersection with BL6 and BL8.
, DMC4, DMC6, and DMC8 are provided. Like the memory cell, each dummy memory cell includes a capacitor DC for storing information and a transfer gate DTR made of an N-channel MOS transistor. Writing is performed on the capacitor DC of each dummy memory cell at the bit line precharge potential Vp when the bit line is precharged.

[0005] Bit line pair (BL1, BL2), (BL3
, BL4), (BL5, BL6), (BL7, BL8)
Sense amplifiers SA1, SA3, SA5, and SA7 are respectively connected to sense amplifiers SA1, SA3, SA5, and SA7 for detecting and amplifying the potential difference appearing in the bit line pair.

When reading information (signals), a row decoder (not shown) selects, for example, word line WL1 in accordance with an externally applied row address signal, and raises its potential to an "H" level. Thereby,
Memory cells MC1 and M connected to the word line WL1
The information in C3, MC5, and MC7 is sent to the bit line BL, respectively.
1, BL3, BL5, and BL8. At the same time, the potential of dummy word line DWL2 is raised to "H" level. As a result, dummy memory cells DMC2, DM
The potentials in C4, DMC6, and DMC8 are read out to bit lines BL2, BL4, BL6, and BL8, respectively, as reference potential VR. On the other hand, bit lines BL1, BL3, BL5,
The potential of BL7 becomes slightly higher or lower than its reference potential VR.

After that, the potential difference appearing in each bit line pair is
Detected and amplified by each sense amplifier. moreover,
One bit line pair is selected by a column decoder (not shown) in accordance with a column address signal applied from the outside, and information on the bit line pair is read out to a data input/output line pair (not shown). Ru.

Note that when the word line WL1 is selected, a dummy word line DWL is selected to cancel noise caused by the potential of the word line WL1 rising.
The potential of 1 falls. When word line WL2 is selected, the potential of dummy word line DWL1 rises and the potential of dummy word line DWL2 falls.

[0009] Here, the potential appearing on each bit line pair when reading information will be considered. As shown in FIG. 11, a ground capacitance C0 exists between each bit line and the ground potential via a cell plate or substrate, and an inter-bit line capacitance CBB exists between two adjacent bit lines. shall be taken as a thing. Further, the length of each bit line is L, and the capacitance of the memory cell and dummy cell is Cs.

The charge stored in the memory cell becomes Cs·Vcc (Vcc write) when "H" information is stored, and becomes 0 when "L" information is stored.
(0V writing). In addition, dummy memory cell DMC1
, DMC2, the charge stored in each of them is Cs·Vp. Each bit line is precharged to a precharge potential Vp before a read operation. Therefore, the charge on each bit line becomes C0·Vp.

In FIG. 10, for example, word line WL1
Consider the case where dummy word line DWL2 and dummy word line DWL2 are selected. Here, it is assumed that "H" information is stored in the memory cell MC3. Also, the bit line BL after the read operation
The potential of bit line BL4 is set to VH, and the potential of bit line BL4 is set to VR. Furthermore, bit lines BL1, BL2, BL5, BL6
Let the potentials of V1, V2, V5, and V6 be respectively. First, regarding bit line BL3, the following equation holds true according to the law of conservation of charge before and after reading.

C0・Vp+Cs・(Vcc−Vcp)=C0
・VH+Cs・(VH−Vcp) +CBB・(
VH-V2)+CBB・(VH-VR)
(1) Furthermore, the following equation holds true regarding the bit line BL4.

[0013] C0・Vp+Cs・(Vp−Vcp)=C0・
VR+Cs・(VR−Vcp) +CBB・(V
R-VH)+CBB・(VR-V5)
...(2) From equations (1) and (2), the following equation holds true.

Cs・(Vcc−Vp)=C0・(VH−VR)+3・CBB・(VH−V
R) +CBB・(V5-V2)+Cs・(VH
-VR)...(3) The read potential difference (VH-VR) is the smallest on the word line WL1
All memory cells MC1, MC3, M selected by
This is a case where "H" information is stored in C5 and MC7. Therefore, when V5=VH and V2=VR, the read potential difference (VH-VR) is expressed by the following equation.

VH-VR=Cs・(Vcc-Vp)/(C0+4・C
BB+Cs)...(4) As is clear from the above equation (4), the bit line capacitance C
The read potential difference is reduced by BB.

[0016]

As memory elements become more highly integrated and the bit line pitch decreases, the inter-bit line capacitance CBB increases and the denominator of equation (4) increases. Therefore, the read potential difference decreases due to capacitive coupling noise between adjacent bit lines. As a result, there is a problem that the soft error rate worsens, the read margin decreases, etc., and eventually malfunction occurs.

[0017] Twisted bit line technology for reducing capacitive coupling noise between bit lines is disclosed in, for example, Japanese Patent Laid-Open No. 60-254489 and IEEE JOUR
NALOF SOLID-STATE CIRCU
ITS, VOL24, No. 5, OCTOBER 1
989, pp. 1184-1190.

An object of the present invention is to provide a semiconductor memory device in which a drop in read potential difference due to capacitive coupling noise between adjacent bit lines is reduced.

[0019]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a plurality of bit lines constituting a plurality of bit line pairs, a plurality of word lines arranged to intersect with the plurality of bit lines, and a plurality of word lines arranged to intersect the plurality of bit lines. It includes a plurality of memory cells provided at the intersections of a bit line and a plurality of word lines, and a plurality of sense amplifier means for detecting the potential difference between the bit lines forming each bit line pair.

In the semiconductor memory device according to the first invention,
Each bit line pair is comprised of every other bit line, and each bit line of each bit line pair intersects one bit line of another bit line pair at a predetermined intersection.

In the semiconductor memory device according to the second invention,
Furthermore, two bit lines that intersect with each other are connected to the first
and a second type of bit line, where the first type of bit line includes an intersection formed by the first layer, and the second type of bit line includes an intersection formed by the first layer. includes an intersection formed by a different second layer. The two bit lines of each bit line pair are both of the same type.

[0022] In the semiconductor memory device according to the third invention,
Each bit line pair is composed of every other bit line, and one bit line of the two bit lines of each bit line pair has a predetermined relationship with one bit line of another bit line pair adjacent to one side. The bit line intersects at the intersection and the other bit line intersects with one bit line of yet another bit line pair adjacent to the other side at a predetermined intersection.

[0023] In the semiconductor memory device according to the fourth invention,
Furthermore, two bit lines that intersect with each other are connected to the first
and a second type of bit line, where the first type of bit line includes an intersection formed by the first layer, and the second type of bit line includes an intersection formed by the first layer. includes an intersection formed by a different second layer. The two bit lines of each bit line pair are both of the same type.

[0024]

[Operation] According to the semiconductor memory device according to the first to fourth inventions, each bit line intersects with an adjacent bit line at a predetermined intersection, and each bit line pair is connected to every other bit line. With this configuration, a drop in read potential difference due to capacitive coupling noise between adjacent bit lines is reduced.

In particular, according to the semiconductor memory device according to the third aspect of the invention, the influence of inter-bit line noise is reduced even when the sense amplifier means amplifies the potential difference on the bit line pair.

According to the semiconductor memory devices according to the second and fourth aspects of the invention, two semiconductor memory devices connected to the same sense amplifier means
The stray capacitances of the two bit lines are equalized. Therefore, the read potential difference becomes uniform. Furthermore, no malfunction occurs during amplification by the sense amplifier means.

[0027]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the structure of the main parts of a dynamic semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the overall structure of the semiconductor memory device.

First, referring to FIG. 2, as will be described later, the memory cell array 1 includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, and a plurality of memory cells provided at the intersections of the word lines. including. The plurality of bit lines of the memory cell array 1 constitute a plurality of bit line pairs,
A sense amplifier SA is connected to each bit line pair. Each sense amplifier SA is connected to a data input/output line pair I/O via N channel MOS transistors Q1 and Q2.

On the other hand, row address buffer 2 provides externally applied address signal RA to row decoder 3 as row address signals RA0 to RAn in response to row active row address slave signal RAS. Row decoder 3 selects one of the plurality of word lines included in memory cell array 1 in response to row address signals RA0 to RAn, and raises its potential to the "H" level. Column address buffer 4 converts externally applied address signal CA into column address signals CA0 to CA0 in response to low active column address slave signal CAS.
It is applied to column decoders 5a and 5b as CAn. Column decoders 5a and 5b receive column address signals CA0 to
In response to CAn, a pair of transistors Q1 and Q2 is selected and an "H" level selection signal is applied to their gates. A clock generation circuit 6 generates clock signals such as a precharge signal and a sense amplifier activation signal and supplies them to the memory cell array 1.

When reading information, the information read from memory cell array 1 is transferred to data input/output line pairs I/O and I/O.
The data is outputted to the outside via the O buffer 7 as output data Dout. When writing information, the input data Din is
The signal is input to memory cell array 1 via /O buffer 7 and data input/output line pair I/O. Note that each of these portions 1 to 7 is formed on the semiconductor chip CH.

Next, refer to FIG. 1. In FIG. 1, a plurality of bit lines BL11 to BL22, a plurality of word lines WL3, WL4 crossing them, and a dummy word line DWL3 are shown.
, DWL4 are shown. Word line WL3 and bit lines BL11, BL14, BL15, BL18, BL19,
Memory cells MC11 and M are located at the intersection with BL22, respectively.
C14, MC15, MC18, MC19, and MC22 are connected. Word line WL4 and bit line BL12,B
Memory cells MC12, MC13, MC are located at the intersections with L13, BL16, BL17, BL20, and BL21, respectively.
16, MC17, MC20, and MC21 are connected.

In addition, dummy word line DWL3 and bit lines BL11, BL14, BL15, BL18, BL19,
A dummy memory cell DMC is provided at each intersection with BL22.
11, DMC14, DMC15, DMC18, DMC1
9, DMC22 is connected. Dummy word line DW
L4 and bit lines BL12, BL13, BL16, BL1
7, BL20, and BL21 have dummy memory cells DMC12, DMC13, DMC16, and DMC, respectively.
17, DMC20, and DMC21 are connected.

Here, let k be a positive integer and let the k-th bit line be BL(k). In this embodiment, bit line BL(2k+1) and bit line BL(2k+2) intersect with each other at their respective centers.

The plurality of bit lines BL11 to BL22 are connected to a plurality of bit line pairs (BL11, BL13), (BL12,
BL14), (BL15, BL17), (BL16, B
L18), (BL19, BL21), (BL20, BL
22), and sense amplifiers SA11, SA12, SA15, SA16, and S
A19 and SA20 are connected.

The configurations of each memory cell, each dummy memory cell, and each sense amplifier are similar to those in the conventional semiconductor memory device shown in FIG. 10, but the configuration of the bit line pair is different from that of the conventional bit line pair. Their arrangement is different due to the different configuration of the .

Next, the potential appearing on each bit line pair when reading information will be considered. A ground capacitance C0 exists between each bit line and the ground potential via a cell plate or substrate, and an inter-bit line capacitance CBB exists between adjacent bit lines.
Assume that there exists. In this embodiment, each bit line of length L crosses an adjacent bit line at its center. Therefore, consider dividing each bit line into two parts having length L/2. As shown in FIG. 3, each part of each bit line has a ground capacitance C0/2 and an inter-bit line capacitance C
BB/2 exists. Further, the cell capacitance of the memory cell and the dummy memory cell is assumed to be Cs.

The charge stored in the memory cell becomes Cs·Vcc (Vcc write) when "H" information is stored, and becomes 0 (0) when "L" information is stored.
V writing). Furthermore, the charge stored in the dummy memory cell is Cs·Vp. Assuming that each bit line pair is precharged to a precharge potential Vp before a read operation, the charge on each bit line becomes C0·Vp.

In FIG. 1, consider the case where word line WL3 and dummy word line DWL4 are selected, for example. Here, it is assumed that "H" information is stored in the memory cell MC15. After the read operation, the potential of the bit line BL15 is set to VH, and the potential of the bit line BL17 is set to VR. Further, the potentials of the bit lines BL11 and BL13 are set to V11 and V13, respectively, and the bit lines BL12 and BL14 are set to V11 and V13, respectively.
The potentials of bit line B are set to V12 and V14, respectively, and the potential of bit line B
The potentials of L16 and BL18 are set to V16 and V18, respectively.
shall be. The potentials of bit lines BL19 and BL21 are set to V19 and V21, respectively, and the potentials of bit lines BL20 and BL22 are set to V20 and V22, respectively.

First, regarding the bit line BL15, the following equation holds true according to the law of conservation of charge before and after reading.

C0・Vp+Cs・(Vcc−Vcp)=C0
・VH+Cs・(VH−Vcp) +CBB・(
4・VH-2・V16-V18-V14)/2
(5) Regarding the bit line BL17, the following equation holds true.

C0・Vp+Cs・(Vp−Vcp)=C0・
VR+Cs・(VR−Vcp) +CBB・(4
・VR-V16-2・V18-V20)/2
...(6) From equations (5) and (6), the following equation holds true.

Cs・(Vcc−Vp)=C0(VH−VR)+2・CBB・(VH−VR
)+Cs・(VH-VR) +CBB・(-V1
6+V18-V14+V20)/2
...(7) In the above equation (7), the read potential difference (VH-VR
) becomes minimum when "H" information is stored in memory cells MC18 and MC22 selected by word line WL3. That is, V16=VR, V1
When 8=VH, V14=VR, and V20=VH, the read potential difference (VH-VR) is expressed by the following equation.

VH−VR=Cs・(Vcc−Vp)/(C0+3
・CBB+Cs)...(8) Comparing equation (8) with equation (4) in the conventional example, it can be seen that the coefficient of CBB in the denominator has decreased from 4 to 3, and the read potential difference (VH - VR) has increased. Recognize. Note that the same consideration can be given to the case where "L" information is stored in the memory cell.

FIG. 4 is a diagram showing the configuration of bit lines located at the ends of memory cell array 1 (FIG. 2).

In FIG. 4, bit lines BL3 to BL10
are arranged similarly to the bit lines shown in FIG. 1, and are connected to sense amplifiers SA3, SA4, SA7, and SA8. The bit line BL2 located at the end is connected to the potential fixing circuit 1.
0, it is always fixed at the same potential. The same potential is, for example, 1/2 of the power supply potential.

As a result, the bit line pair located at the end of memory cell array 1 also has the same effect as the bit line pair in FIG.

Next, the noise between bit lines when the read potential difference is amplified by the sense amplifier will be explained. here,
Consider inter-bit line noise received by bit lines BL15 and BL17 connected to sense amplifier SA15 in FIG. 1 or 3.

After reading information from memory cells, bit line B
It is assumed that the potential of L15 is higher than the potential of BL17. When the sense amplifier SA15 operates, the potential difference is amplified so that the potential of the bit line BL15 approaches the "H" level and the potential of the bit line BL17 approaches the "L" level.

However, as shown in FIG. 3, between bit line BL15 and bit line BL14, bit line BL15
and the bit line BL18, and between the bit line BL15 and the bit line BL16, respectively.
There are BB/2, CBB/2 and CBB. Therefore, bit line BL15 is connected to bit lines BL14 and BL16.
, BL18. For example, the potentials of bit lines BL14 and BL16 are both “L”.
”, the bit line BL15 will be affected in the opposite direction to the potential change of the bit line BL15. In this case, the potential of the bit line BL18 will be “H”.
"The bit line BL1 changes as it approaches the level
The noise from the half part of bit line BL16 and the noise from the half part of bit line BL16 cancel each other out. However, the noise from half of the bit line BL14 and the bit line BL
The noise from the other half of the 16 will remain.

As described above, the bit line BL15 may be subject to inter-bit line noise depending on potential changes of adjacent bit lines.

FIG. 5 is a diagram showing the configuration of the main parts of a dynamic semiconductor memory device according to still another embodiment of the present invention. The semiconductor memory device of this embodiment has been improved so that it is not affected by inter-bit line noise even during amplification by the sense amplifier.

The difference between the embodiment of FIG. 5 and the embodiment of FIG. 1 is that one of the two bit lines constituting each bit line pair
At the point where one bit line intersects one bit line of another bit line pair located on one side, and the other bit line intersects one bit line of yet another bit line pair located on the other side. be. For example, bit line pair (BL15, BL1
The bit line BL15 constituting 7) intersects the bit line BL16 of the adjacent bit line pair (BL14, BL16), and the bit line BL17 crosses the bit line BL16 of the adjacent bit line pair (BL14, BL16).
18, BL20) intersects with the bit line BL18.

In the embodiment of FIG. 5, the bit line pair (BL15, B
The read potential difference appearing at L17) is determined. First, regarding the bit line BL15, the following equation holds true.

C0・Vp+Cs・(Vcc−Vcp)=C0
・VH+Cs・(VH−Vcp) +CBB・(
4・VH-2・V16-V18-V14)/2
(9) Regarding the bit line BL17, the following equation holds true.

C0・Vp+Cs・(Vp−Vcp)=C0・
VR+Cs・(VR−Vcp) +CBB・(4
・VR-V16-2・V18-V20)/2...
(10) From equations (9) and (10), the following equation holds true.

Cs・(Vcc−Vp)=C0(VH−VR)+2・CBB・(VH−VR
)+Cs・(VH-VR) +CBB・(-V1
6+V18-V14+V20)/2...
(11) Thus, equations (9), (10) and (11
) is the same as equations (5), (6), and (7).

In equation (11), the read potential difference (VH-V
Consider the case where R) is minimized. V16=VR, V14
=VH, V18=VH, and V20=VR, the read potential difference (VH-VR) is expressed by the following equation.

VH−VR=Cs・(Vcc−Vp)/(C0+3
-CBB+Cs)...(12) Equation (12) is also the same as Equation (8). Comparing equation (12) with equation (4) in the conventional example, similar to equation (8), the read potential difference (VH-VR)
It can be seen that the is getting larger.

Next, consider the bit line noise when the read potential difference (VH-VR) is amplified by the sense amplifier.

FIG. 6 is a diagram for explaining the influence of inter-bit line noise on the bit lines BL15 and BL17 during amplification of the read potential difference.

In FIG. 6, bit line pair (BL15, B
L17) is connected to the bit line pair (BL14, BL16) during amplification.
) or the bit line pair (BL18, BL20). The noise from the bit line pair (BL14, BL16) is indicated by N1, N2, N3, N4, and the noise from the bit line pair (BL14, BL16) is
18, BL20) noise from N5, N6, N7, N8
It is indicated by.

Bit line BL15 is connected to bit line pair (BL14
, BL16), and the bit line BL17 receives noises N1 and N2 of opposite phase to each other from the bit line pair (BL18, BL2).
0), noises N7 and N8 of mutually opposite phases are received. Furthermore, bit line BL15 and bit line BL17 receive in-phase noises N3 and N4, respectively, from the same bit line BL16. Furthermore, bit line BL15 and bit line BL17 receive in-phase noise N5 and N6, respectively, from the same bit line BL18.

Therefore, the noise that the bit line BL15 receives from the adjacent bit line during amplification and the bit line BL1
It is considered that the noise received by bit lines 7 from adjacent bit lines during amplification is approximately the same.

In this way, the bit line pair (BL15, BL
17) is hardly affected by inter-bit line noise from surrounding bit lines even during amplification after a read operation.

FIG. 7 is a diagram showing the configuration of the bit lines located at the ends of the memory cell array in the embodiment of FIG.

Bit lines BL2 to BL9 shown in FIG. 7 are arranged similarly to the bit lines shown in FIG. 5, and are connected to sense amplifiers SA2, SA3, SA6, and SA7. Bit line BL located at the end of the memory cell array
0, BL1 are always kept at the same potential (
For example, it is fixed at 1/2 of the power supply potential. As a result, the bit line pair located at the end of the memory cell array is
It has the same effect as the bit line pair shown in FIG.

FIGS. 8 and 9 are diagrams for explaining the configuration of bit line intersections in the embodiments of FIGS. 1 and 5, respectively.

In FIG. 8, a bit line pair (BL15, BL17) connected to sense amplifier SA15 and a bit line pair (BL16, BL17) connected to sense amplifier SA16 are shown.
The intersection where BL18) intersects will be explained.

Bit line BL15 is connected to wiring layers MM1 and MM2.
, PP1, and the bit line BL16 is formed by the wiring layer M
Formed by M3. Further, the bit line BL17 is formed by wiring layers MM4, MM5, and PP2, and the bit line B
L18 is formed by the wiring layer MM6. Wiring layer MM1
~MM7 are formed by coplanar layers. Wiring layer PP1 at the intersection of bit line BL15 and bit line BL16 and bit line BL17 and bit line BL
The wiring layer PP2 at the intersection with the wiring layer MM1
- It is formed by a layer different from MM6.

Regarding bit line BL15, wiring layer MM
1 is connected to another wiring layer PP1 through the contact hole CH1.
The wiring layer PP1 is connected to the contact hole CH
3 to the wiring layer MM2. Bit line BL1
7, the wiring layer MM4 is connected to another wiring layer PP2 through the contact hole CH2, and the wiring layer PP2 is connected to the wiring layer MM through the contact hole CH4.
Connected to 5.

Bit lines formed of one type of wiring layer, such as bit lines BL16 and BL18, are called first type bit lines. In addition, bit lines formed by two types of wiring layers, such as bit lines BL15 and BL17, are
This type of bit line is called. In the second type of bit line, one wiring layer is connected to the other wiring layer via another wiring layer at the intersection, so that the stray capacitance and resistance of the bit line increase. Therefore, in the second type of bit line, compared to the first type of bit line,
The time required for charging and discharging becomes longer.

In this embodiment, the bit lines BL15 and BL17 connected to the sense amplifier SA15 are both of the second type, and the bit lines BL16 and BL18 connected to the sense amplifier SA16 are both of the first type. This is the bit line. That is, two bit lines connected to one sense amplifier are both of the same type.

Thereby, the capacitances of the two bit lines connected to the same sense amplifier become equal. As a result, the charging and discharging times are equal for the two bit lines connected to the same sense amplifier, so the read potential difference becomes uniform and malfunctions are prevented.

FIG. 9 is a diagram for explaining the configuration of the bit line intersection in the embodiment of FIG.

In the embodiment shown in FIG. 9, as in the embodiment shown in FIG. 8, the two bit lines connected to the same sense amplifier are both of the same type.

Bit line BL11 is connected to wiring layers MM1 and MM.
2 and another wiring layer PP1, and the bit line BL13 is a second type bit line formed by wiring layer MM2 and another wiring layer PP1.
4, MM5 and another wiring layer PP2. The bit line BL12 is a first type bit line formed by the wiring layer MM3, and the bit line BL14 is a first type bit line formed by the wiring layer MM6.

In the embodiment of FIG. 9 as well, since the capacitances of the two bit lines connected to the same sense amplifier are equal, the read potential difference becomes uniform and malfunctions are prevented.

In the embodiments shown in FIGS. 1 and 5, a plurality of sense amplifiers are arranged alternately at both ends of a plurality of bit lines, but all sense amplifiers are arranged at one end of a plurality of bit lines. It may be placed in

[0080]

As described above, according to the first to fourth aspects of the invention, it is possible to reduce noise from adjacent bit lines via the bit line capacitance, and to reduce the drop in read potential difference between bit line pairs. can be done. Therefore, a highly reliable semiconductor memory device can be obtained.

In particular, according to the third invention, even when the sense amplifier means amplifies the read potential difference, the influence of inter-bit line noise can be canceled out.

Furthermore, according to the second and fourth inventions,
The read potential difference is made uniform, and malfunctions are prevented during amplification by the sense amplifier means.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of main parts of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the semiconductor memory device of the same embodiment.

FIG. 3 is a diagram for explaining the capacitance associated with each bit line in the semiconductor memory device of the same embodiment.

FIG. 4 is a diagram showing the configuration of bit lines at the end of the memory cell array in the same embodiment.

FIG. 5 is a diagram showing the configuration of a main part of a semiconductor memory device according to another embodiment of the present invention.

FIG. 6 is a diagram for explaining the influence of noise on bit lines in the semiconductor memory device according to the same embodiment.

FIG. 7 is a diagram showing the configuration of bit lines at the end of the memory cell array in the same embodiment.

FIG. 8 is a diagram for explaining the configuration of a bit line intersection in the embodiment of FIG. 1;

FIG. 9 is a diagram for explaining the configuration of a bit line intersection in the embodiment of FIG. 5;

FIG. 10 is a diagram showing the configuration of main parts of a conventional semiconductor memory device.

FIG. 11 is a diagram for explaining the capacitance associated with each bit line in a conventional semiconductor memory device.

[Explanation of symbols]

WL3, WL4...Word lines DWL3, DWL4...Dummy word lines BL0-BL22...Bit lines MC11-MC22...Memory cells DMC11-DMC22...Dummy memory cells SA3, S
A4, SA7, SA8, SA11, SA12, SA15
, SA16, SA19, SA20... sense amplifiers 10, 11... potential fixing circuits. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (4)

[Claims] 1. A plurality of bit lines constituting a plurality of bit line pairs, a plurality of word lines arranged to intersect the plurality of bit lines, and an intersection between the plurality of bit lines and the plurality of word lines. A plurality of memory cells provided in the memory cell and a plurality of sense amplifier means for detecting the potential difference between the bit lines constituting each bit line pair are provided, each bit line pair is composed of every other bit line, and each bit line pair is composed of every other bit line. A semiconductor memory device in which each bit line of a line pair is provided to intersect with one bit line of another bit line pair at a predetermined intersection. 2. A plurality of bit lines constituting a plurality of bit line pairs, a plurality of word lines arranged to intersect the plurality of bit lines, and an intersection between the plurality of bit lines and the plurality of word lines. A plurality of memory cells provided in the memory cell and a plurality of sense amplifier means for detecting the potential difference between the bit lines constituting each bit line pair are provided, each bit line pair is composed of every other bit line, and each bit line pair is composed of every other bit line. Each bit line of a line pair is provided to intersect one bit line of another bit line pair at a predetermined intersection, and the two bit lines that intersect with each other are a first type of bit line and a second type of bit line, respectively. type of bit line, wherein the first type of bit line includes an intersection formed by a first layer, and the second type of bit line includes a second type of bit line formed by a second layer different from the first layer. 1. A semiconductor memory device in which two bit lines of each bit line pair are both of the same type. 3. A plurality of bit lines constituting a plurality of bit line pairs, a plurality of word lines arranged to intersect the plurality of bit lines, and an intersection between the plurality of bit lines and the plurality of word lines. A plurality of memory cells provided in the memory cell and a plurality of sense amplifier means for detecting the potential difference between the bit lines constituting each bit line pair are provided, each bit line pair is composed of every other bit line, and each bit line pair is composed of every other bit line. Of the two bit lines of the line pair, one bit line intersects one bit line of another bit line pair adjacent to one side at a predetermined intersection, and the other bit line intersects one bit line of another bit line pair adjacent to the other side, and A semiconductor memory device that intersects one bit line of another bit line pair at a predetermined intersection. 4. A plurality of bit lines constituting a plurality of bit line pairs, a plurality of word lines arranged to intersect the plurality of bit lines, and an intersection between the plurality of bit lines and the plurality of word lines. A plurality of memory cells provided in the memory cell and a plurality of sense amplifier means for detecting the potential difference between the bit lines constituting each bit line pair are provided, each bit line pair is composed of every other bit line, and each bit line pair is composed of every other bit line. Of the two bit lines of the line pair, one bit line intersects one bit line of another bit line pair adjacent to one side at a predetermined intersection, and the other bit line intersects one bit line of another bit line pair adjacent to the other side, and The two bit lines intersect with one bit line of another bit line pair at a predetermined intersection, and each of the two bit lines that intersect with each other consists of a first type bit line and a second type bit line, and
The type of bit line includes an intersection formed by a first layer, the second type bit line includes an intersection formed by a second layer different from the first layer, and each bit line includes an intersection formed by a second layer different from the first layer. A semiconductor memory device in which two bit lines of a bit line pair are both of the same type.