JPH04246950A - Defective node decision system on computer network - Google Patents

Abstract

PURPOSE: To provide a system for monitoring each transmission signal strength of a node on an LAN cable, and judging the position of a transmission signal. CONSTITUTION: A system is provided with a monitor arranged in a node normally connected with a cable. When an information frame is transmitted, the signal strength of a frame preamble and the address of the origin of transmission are recorded. Then, a distance from the end part of the cable to a node is calculated from this signal strength. An LAN collision trap circuit periodically transmits a pseudo frame signal with the maximum length, and monitors the generated collision or disturbing signal. When each signal is detected, collision/ disturbance information bits, signal strength, and time are recorded in an FIFO. Software 1204 reads this, and judges the presence of invalid early collision, invalid delayed collision 1208, or disturbance 1206 based on this recording. The software compares 1210 the signal strength with strength measured by a monitor for judging a defective node, and displays 1216 the address and position of the defective node.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to computer systems and, more particularly, to computer networks. More particularly, the present invention relates to a method and apparatus for monitoring the location and operation of nodes on a computer network.

0002

[Prior art] Local area network (LAN)
Computer networks, also known as computers, continue to be popular in environments where one or more computers are used. L for IEEE802.3 protocol (Ethernet)
The length of each segment of the AN ranges from 185 to 500 meters depending on the type of cable used. Up to 3 cables per segment, depending on the type of cable used
You can attach 0 or up to 100 nodes. Because of this length and number of nodes, a single segment often includes an entire office or even an entire building with cables running between the walls and floors.

The IEEE 802.3 protocol is a carrier sense multiple access/collision detection (CSMA/CD) type protocol that allows all nodes to time share the same cable. When the first node wants to send information to another node, the first node listens for the carrier (meaning the other node is transmitting) and if no carrier is detected, the first node sends Start. If two nodes start transmitting at the same time, a collision will occur and both nodes will detect the collision and stop transmitting. Each node transmits again later. This way all nodes use the same cable without interfering with each other.

[0004] If a node is bad, it may start transmitting without first listening to the carrier, which often causes collisions. Bad nodes may detect carriers incorrectly or may detect carriers late, resulting in late collisions. If a node is not properly tuned, it may not be able to detect carriers pumped near the lower or upper limits of its allowed current.

[0005] The length of each information frame transmitted over the cable is limited, and a bad node may send out a frame that is too long. If a frame is too long, other nodes on the network may interfere with the node sending the long frame. If a node is not properly tuned, it may send out jamming signals too early, resulting in jamming of valid frames.

Many other problems can and do occur with segments. When a problem occurs, the system administrator needs to know which node is the source of the problem. Because all nodes use the same cable, and this cable can extend up to 500 meters through walls, raceways, or building floors, finding bad nodes is a difficult task for administrators. It is.

There is a need in the art for a system for discovering nodes on network segments. It is further desired that such a system detect late conflicting nodes. It is further desired that such a system detect early interfering nodes. Furthermore, there is a need for a system that detects nodes that cannot detect carrier levels close to acceptable limits. This invention meets these needs.

[0008]

[Problem to be solved by the invention] The purpose of this invention is to
EE802.3 is to monitor signals on a segment of a computer local area network.

Another object of the invention is to measure the signal strength of the signals transmitted from each node connected to this network segment.

Another object is to calculate the position of each node located in a segment of the network based on the signal strength of the signals sent from each node.

Another objective is to calculate the position of a node by measuring the signal strength from the node at two points on the network segment, and to calculate the ratio of the signal strength at the second point to the total signal strength at both points. calculate,
The purpose is to obtain the distance from the node to the first measurement point.

Another purpose is to display the location of nodes to users of such networks or to network administrators.

Another object of the invention is to detect late conflicting nodes on a network.

Yet another object of the present invention is to detect nodes that are unable to recognize carrier signals that are close to the limits of allowed carrier transmission levels.

Yet another objective is to detect nodes that emit jamming signals before the end of a valid frame.

[0016]

SUMMARY OF THE INVENTION These and other objects of the present invention are achieved in a system for monitoring signal strength on each transmission on a LAN cable.

[0017] This system has a monitor at each end of the LAN cable, one of the monitors typically located at a computer node attached to the cable. As each information frame is transmitted over the cable, the monitor records the relative signal strength of this frame and the source address contained in this frame. The ratio of each signal strength to the total signal strength is then calculated, and this ratio is used to determine the location of the node that sent this frame on the network.

Each LAN level monitor has a filter that filters the incoming signal and sends the filtered signal to a sample/hold circuit that sends the signal to an analog-to-digital converter. In parallel with these elements, a phase-locked loop extracts the data and clock from this signal, and a source address stripper circuit removes the source address from the information frame. Once the source address is removed and the signal strength level is converted to a digital value, the source address and signal level are stored in a first-in-first-out (FIFO) buffer.

Data from each FIFO in each LAN level monitor is collected by software that uses the source address recorded in the FIFO to relate the two values of signal strength level. Once the signal strength levels at the two ends of the cable are determined, the location of this node can be determined.

The LAN collision trap circuit periodically sends out a pseudo frame signal and monitors collision or interference signals that occur during the pseudo frame. When a collision or disturbance is detected, the signal strength and time of this collision or disturbance are recorded in the FIFO. The system's software reads this FIFO and determines whether the collision is a valid early collision or an invalid late collision or disturbance based on this time and the information bits. If a late collision or jamming is detected, the software determines the faulty node by comparing the signal strength of this collision or jamming signal with the strength measured by the LAN level monitor and identifies the faulty node that caused the collision or invalid jamming. Display the address and location of a node.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description describes the best presently contemplated embodiments of this invention. This description is not to be construed in a limiting sense, but is provided merely to explain the general principles of the invention. The scope of this invention must be determined with reference to the claims.

Generally, the invention comprises a system for monitoring the signal strength of each transmission on a LAN cable. This system has level monitors at each end of the LAN cable, one of the monitors typically located at a computer node attached to the cable. As frames of information are transmitted over the cable, each monitor records the frame's relative signal strength and the source address contained in the frame.

The system also includes a LAN collision trap circuit that periodically sends out a pseudo frame signal and monitors for collision or interference signals that occur during the pseudo frame. When a collision or disturbance is detected, bits representing the collision or disturbance and the signal strength and time of the collision or disturbance relative to the start of the pseudo frame are recorded in the FIFO. Software in the system reads this FIFO and
Based on this time it is determined whether a delayed collision or disturbance has been detected. If a late collision or jamming is detected, the software determines the bad node by comparing the signal strength of the collision or jamming signal with the strength measured by the LAN level monitor and determines the address of the bad node that caused the collision or jamming. and display the position.

FIG. 1 shows a block diagram of a computer system employing the present invention. In FIG. 1, computer system 100 includes processing element 102. In FIG. Processing element 102 communicates with other components of computer system 100 over system bus 104 . keyboard 106
is used to receive text information from the user of the system (usually the network administrator). Display 108 is used to output information to a network administrator and may have the ability to output graphical information. Main memory 110 includes data correlation software 120 that interfaces with the rest of the system via an operating system 122. Data correlation software 120, operating system 12
2 and a table of information regarding networks are stored on disk 114. Printer 116 is used to create a hard copy of the results of the data correlation software.

Network level monitor 112 collects and analyzes each information frame sent over network 118 and is therefore connected to one end of network 118 . A similar network monitor is Network 118
It is connected to the other end and sends its data back to computer system 100 via serial interface 124 and serial cable 126. LAN collision trap 130 generates a maximum length pseudo frame signal that is sent out on network 118 and then LAN collision trap 1
30 monitors network 118 to determine if other nodes on the network are bad or misaligned.

FIG. 2 shows a diagram of a computer network employing the present invention. In FIG. 2, computer system 100 is shown as incorporating a LAN level monitor 112 and a LAN conflict monitor 130. In FIG. A local area network 118 extends from computer 100 and is connected to several LAN nodes 202. LAN 118 has a second LAN level monitor 204 at the other end. LAN level monitor 204 collects information and sends the information back to computer system 100 over serial interface 126.

It is important to place two LAN level monitors at each end of LAN cable 118. LAN
If the monitor is located elsewhere, two LAN
Only nodes located between the monitors can be accurately discovered, and 2
Inaccurate locations are shown for nodes outside the two LAN monitors.

[0028] LAN118 has 50 ohms ±1% at each end.
consists of a coaxial cable terminated by a resistor 206 with a value of . The media access unit (MA) of each node 202
U) is a resistor 20 with a value of at least 7.5K ohms
Terminated at 8. Because the values of resistors 208 are large, they are not important in calculating the minimum and maximum resistance values found on local area network 118. The minimum resistance detected by the MAU between the center conductor of the LAN segment 118 and the shield is 24.775 ohms. This value is 1 meter LAN cable (minimum 2 nodes)
has a resistance of 50 milliohms and the minimum termination resistance of resistor 206 is 49.5 ohms. The maximum resistance detected by the MAU is 27.75 ohms, the length of this segment is 185 meters and thus has a resistance of 10 ohms, and the termination resistor 206 has a maximum value of 50.5 ohms. be.

FIG. 3 shows a diagram of a conventional information frame of IEEE802.3. In FIG. 3, information frame 302
starts from preamble 304. Preamble 304
has 7 bytes with a bit pattern of 10101010. The preamble 304 has a binary pattern 1010
Starting delimiter 30, which is one byte containing 1011
6 follows. Following the start delimiter 306 is a destination address 308 that is 6 bytes long. The destination address is followed by the source address 310, which is also 6 bytes long. Next follows the data portion 312 of this frame, which varies in length from 48 bytes to 1502 bytes. The last information in the frame is the frame check sequence 314, which is 4 bytes of error correction code redundancy data.

FIG. 4 shows a block diagram of the LAN monitor circuit 112 of FIG. 1. In FIG. 4, LAN monitor circuit 1
12 is a collision detector 402 receiving network 118
including. Collision detector 402 monitors network 118 and sends a collision detection (CD) signal 422 to controller 410 whenever a collision occurs. The maximum transmission rate of network 118 is 10 megabits/second, but the preamble frequency is 5 megahertz due to the data pattern contained in preamble 304 (FIG. 3). A 5 MHz filter and amplifier circuit 404 receives the signal from network 118, removes all harmonics and DC bias within the 5 MHz preamble, and transmits it to level detector 4.
05, and this level detector 405 sends a certain level to a sample/hold circuit 408. Sample/hold circuit 408 receives the signal from filter 404 and holds its signal level until analog to digital converter 414 can process the analog signal. Filter 404
It also detects when information is being sent out on network 118 and outputs a carrier sense signal (CSN) which goes to controller 410 and source address stripper circuit 412.

A clock extraction phase-locked loop circuit 406 is also connected to the network 118. circuit 40
6 is serial data 4 from information on the network 118
28 and also used to synchronize the serial data 428 (BIT_CLOCK)
Extract 426. Serial data 428 is data 42
8 and goes to a source address stripper circuit 412 which monitors 8 and extracts the source address from this data. Source address stripper circuit 412 outputs a source address clock (SA), which is an inductive signal that clocks each byte of the source address.
_CLOCK) signal 430. Source address stripper 412 also sends an end signal after all bytes of the source address have been clocked by source address clock (SA_CLOCK) 430.

Controller circuit 410 controls other circuits and also provides all signals necessary to collect data to FIFO 416. Controller 410 opens to sample/hold circuit 408 after carrier is detected.
Send signal 436. This OPEN signal 436 causes sample/hold circuit 408 to begin a sampling period. After 32 clock bits, controller 410 sends a HOLD signal 438 to cause sample/hold circuit 408 to hold the analog level. Controller 410 sends a D_OE signal 434 to source address stripper 412 to cause source address stripper 412 to gate parallel data 444 into FIFO 416 . The controller 410 receives an A/D conversion (A/D_CONV) signal 44
2 to an analog/digital converter circuit 414 to convert the analog signal into a digital signal. When the controller 410 is ready to store the converted level value in the FIFO, it sends an A/D_OE signal 440 to the analog-to-digital converter circuit 414. After gating the appropriate data into FIFO 416, controller 410 writes (WRITE)
Send signal 450 to FIFO 416.

[0033] After data is stored in FIFO 416,
Computer system 100 can receive the data via parallel bus 448 and interface circuit 418.

FIG. 5 shows the source address stripper 4 of FIG.
A block diagram of 12 is shown. In FIG. 5, serial-to-parallel converter circuit 502 extracts data 428 and bit clock 426 from clock extraction phase-locked loop circuit 406 (FIG. 4).
receive. After converting this data into parallel, the serial-to-parallel converter 502 sends the data on an 8-bit bus 512 to a D-flop latch 504, which sends the data on another 8-bit bus 444 to an 8-bit FIFO 416 (
latched before being sent to Figure 4). Controller 410 (Figure 4
D_OE signal 434 from ) gates this data from D-flop latch 504 onto bus 444 .

Data 428 and clock bits 426 are also connected to start delimiter detector 506. When start delimiter detector 506 receives carrier sense signal 424,
Data 428 is examined until starting delimiter byte pattern 306 (FIG. 3) is recognized. When the start delimiter byte pattern is detected, the start delimiter detector 506 selects S
D REC signal 514 is sent to byte division circuit 508 . After receiving the SD REC signal 514, the byte divider circuit 508 divides the bit clock 426 by eight to create a byte clock signal 516, which is sent to the source address counter circuit 510. Byte clock signal 516
is gated by SD REC 514 and carrier sense 424 to synchronize the bytes within the information frame. Source address counter circuit 510 ignores the first six byte clock signals 516. This is because they clock the destination address byte. The next six byte clock signals 516 are then passed to obtain the source address clock 430. Source address clock 430 is connected to D-flop latch 504 to latch eight parallel bits of signal 512. Also, the SA clock signal 43
0 is also sent to controller 410, which uses this signal to activate D_OE 434 and transfer the parallel bits to FIFO 41.
6 (FIG. 4). After the SA clock signal is asserted six times, once for each source address bit, a termination signal 432 is asserted and sent to controller 410. In the manner described above, the circuit of FIG. 5 selects six source addresses from the incoming information frame, converts them to parallel data, and sends each of the six bytes onto the 8-bit parallel bus 444.

FIG. 6 shows a state diagram of controller circuit 410 of FIG. This state diagram will be described in conjunction with block diagram 4. 6 and 4, the controller is in state 0 (6
Start from 02). Carrier detection (CSN) signal 42
4, the controller goes to state 1 (604) and sends an open signal 436 to sample/hold circuit 408. This causes the sample/hold circuit 408 to begin sampling the output of the 5 MHz filter and amplifier 404. After 32 bit clocks, the controller enters state 2 (
606), dropping the open signal 436 and asserting the hold signal 438 to the sample/hold circuit 408, causing the stored value to be held for the analog level of the network signal. After sending the hold signal, the controller goes to state 3 (608), drops the hold signal, and
/D conversion (A/D_CONV) signal is asserted to convert the output of sample/hold circuit 408 to a digital value.

[0037] If a collision is detected or the carrier falls, the controller returns to state 0. This is because the frame is incomplete and no information is stored from it. Alternatively, the controller enters state 4 (610) and begins storing the source address in FIFO 416. Condition 4
(610) waits for the SA clock signal and enters state 5 (612).
), and in this state asserts the D_OE signal 434 and the write signal 450 to write the source address to the FIFO 416. After all six bits have been written to FIFO 416, the controller is in state 6 (614). In state 6 (614), the A/D_OE signal 440 is
The parallelized output signal is sent to a digital converter 414 and gated to a FIFO 416. Then the controller is in state 7
(616), and in this state, the A/D_OE signal 44
0 and asserts the write signal to transfer the digital value to FI.
Write to FO416. The controller then enters state 0 (602)
and wait for the next information frame.

FIG. 7 shows a top level flowchart of the software of the present invention. This software is part of data correlation software 120 (FIG. 1). The purpose of the software shown in FIGS. 7 and 8 is to correlate the data collected in the FIFOs of the system's two LAN monitors. This software collects digital values of the transmission levels measured at each LAN monitor for each information frame and uses these levels to calculate the location of the node that sent the information frame.

In FIG. 7, after entering block 702
It is determined whether FIFO data is available in the FIFO of any LAN monitor. If data is available, block 702 transitions to block 704, which calls FIG. 8 to store this data in a table. After storing the FIFO data in the table, or if there is no FIFO data, control passes to block 706 which determines if a user request has been entered. If a user request has been entered, block 706 transfers to block 708 where a LAN address is obtained from the user. Next, block 7
The node's location is obtained from the table at 10 and the location is displayed to the user at block 712 before returning to block 702.

FIG. 8 shows a flowchart of the storage table function of this software. In FIG. 8, after entry, block 802 determines whether data is available in the first LAN monitor's FIFO. If data is available in the FIFO of the first LAN monitor, block 8
02 moves to block 804 where the first FIFO
reads the source address and signal level from the source address and determines whether the signal level reading is equal to the value already stored in the table for that source address. If the value is equal to a value already stored in the table, no new table entry is made and block 806
Transition to 0. Table entries include node addresses and signal levels from both FIFOs. If the level obtained from the FIFO is different from the level stored in the table, block 806 transitions to block 808 where the new level is stored in the table before transitioning to block 810. Block 810 determines whether there is data in the second LAN monitor's FIFO. This F
If the IFO has data, block 810 moves to block 812 where it obtains the source address and level value from the FIFO. Block 814 determines whether the level already stored in the table is the same as the level read from the FIFO. If the levels are the same, block 814 transitions to block 818. This is because there is no need to update the table. If the levels are different, block 814 moves to block 816 where the new level value from the second LAN monitor's FIFO is stored in the table. Then block 818
It is determined whether this table has been updated by any of the above processes. If the table is being updated, a new position must be calculated, so block 818 transitions to block 820. Block 820 calculates the distance from the center of the cable to the node using the following equation:

[0041]

[Math 1]

If the distance value is positive, this node is in the direction from the center towards the first LAN monitor; if the distance value is negative, this node is in the direction from the center to the second LAN monitor.
It's facing towards the monitor. Thin LAN cable has a loss of 0.0098 dB per foot, while thick LA cable has a loss of 0.0098 dB per foot.
N cable has a loss of 0.0033 dB per foot. After calculating this distance, block 822 stores this value in a table before returning to FIG.

The following is an example of calculating this distance for a thin LAN cable.

Example 1: Level 1 = 0.7980, Level 2 = 0.6368 Distance = ((10*LOG(0.7980/0.6368))
)/0.0098=100 Therefore, this node is LA
N located 100 feet from the center of the cable on the side of the cable closest to Monitor 1.

Example 2: Level 1 = 0.35, Level 2 = 0.99 Distance = ((1
0*LOG(0.35/0.99))/0.0098)
=-461 Therefore, this node is located 461 feet from the center of the cable on the side of the cable opposite LAN Monitor 1. Also, the value of level 2 is approximately 1, which is the required sending voltage level, so this node is connected to the LAN
It would be located approximately in line with monitor 2, so the cable length would be approximately 922 feet.

Steps for comparing this level with a threshold can be inserted between blocks 804 and 806 and between blocks 812 and 814. This threshold is the minimum level that a node must send, and if the signal level is below this threshold, an error message will be displayed.

FIG. 9 shows a diagram of signal levels defined in the IEEE802.3 standard. Looking at Figure 9 and again at Figure 2, the carrier sense threshold setting for each MAU (maximum) must be -0.9158 volts, which translates to -37 milliamps (minimum average current for one MAU). Multiplied by a minimum resistance value of 24.775 ohms (based on a LAN with a minimum length of 2 meters and terminations of 49.5 ohms). The LAN Collision Monitor uses a current mode digital-to-analog converter to test the MAU of each node on the network, with different values for the minimum and maximum values (-37ma and -45ma), respectively, as described below. It outputs a level of direct current, and also outputs a value between the minimum and maximum values.

FIGS. 10 and 11 show block diagrams of LAN collision trap 130 of FIG. 10 and 11, a 5 MHz bandpass filter 1002 receives the signal from the local area network 118 and sends an output to a precision rectifier 1004. The output of precision rectifier 1004 is a preamble voltage level signal 1038, which is connected to level detector 1006 and sample/hold circuit with source multiplexer 1018. The output of the level detector 1006 is transferred to a voltage level shifter 1008.
and becomes the preamble logic signal 1044 input to the controller 1020.

Also connected to the LAN 118 is a 10 MHz bandpass filter 1010 which is connected to a second precision rectifier 1012 . The output of the precision rectifier 1012 is a disturbance voltage level signal 1040 that is connected to a level detector 1014 and a second input of a sample/hold circuit with source multiplexer 1018. The output of level detector 1014 is connected to a voltage level shifter 1016 whose output is a JAM logic signal 1042 that is connected to controller 1020.

The controller 1020 outputs the DA output (DA_OUT
) signal 1052 and value signal 1054 to digital-to-analog converter 1022. The output of digital/analog converter 1022 is connected to LAN 118.

Further, the LAN 118 includes a carrier detection circuit 1.
030 is connected, and the output of this circuit is a frame detect signal 1 which is connected to an interframe spacing timer 1032 and a programmable frame counter 1034.
It is 084. Interframe spacing timer 10
32 sends the I_END signal 1056 to the controller 10.
Send to 20. Controller 1020 controls I_START
) signal 1058 and I_RESET signal 1
060 to interframe spacing timer 1032. Programmable frame counter 1034 sends an F_END signal 1062 to controller 1020, which sends an F_START signal 10.
64 and an F_RESET signal 1068 to the programmable frame counter 1034.

Maximum frame length timer circuit 1036 sends a MAXEND signal to controller 1020. Controller 1020 generates a maximum start (MAXSTART) signal 10
72, a maximum control (MAXCLR) signal 1074, and a maximum output (MAXOUT) signal 1076 to maximum frame length timer 1036. The maximum frame length counter 1036 also outputs an 11-bit parallel output collision time signal 108.
2 to FIFO 1026. The controller selects P or J (P_O
R_J) signal 1077 is output as bit 11 on bus 1082 for storage in FIFO 1026.

Controller 1020 sends a hold signal 1048 and an S_SELECT signal 1046 to the source multiplexed sample/select signal 1046 to select one of its inputs and send its output 1050 to A/D converter circuit 1024. It is sent to the hold circuit 1018. A/D converter output 1080 is connected to FIFO 1026. FI
The output of FO 1026 is gated to system bus 104 (FIG. 1) via interface 1028. A reset signal 1078 is received from system bus 104.

The operation of circuit diagrams 10 and 11 can be better explained in conjunction with the state diagram of FIG. In FIG. 12, the controller begins in the RESET state 1102 and remains there until the RESET signal 1078 goes high on the system bus 104. In the RESET state, controller 1020
A reset (F_RESET) signal 1068 is sent to programmable frame counter 1034. Reset again (
RESET) state, the controller 1020 is in the I-RESET (I-RESET) state.
_RESET) signal 1060 to the interface spacing timer 1032 and the maximum control (MAXCLR)
A signal 1074 is sent to maximum frame length timer 1036.

After receiving the RESET signal 1078, the controller starts the frame count (FRAME_COU).
NT) enters state 1104. Frame count (FRA)
In the ME_COUNT) state, the controller
ART) signal 1064 to programmable frame counter 1034. A programmable frame counter is a counter setup to prevent the LAN collision trap circuit from taking up too much of the available resources on the local area network. This counter usually has 1
It is given a value of 000 and counts down to zero, one per frame on the local area network. As shown in Figure 11, frame detection (F
RAME_DETECT) signal 1084 is an input to a programmable frame counter that sets the counter to 1 for each frame on local area network 118.
count down times. Therefore, if the programmable frame counter is set to 1000, the LA
N collision traps are 10 from other nodes on the network.
It simply sends a pseudo frame every time a 00 frame is sent.

Programmable frame counter 1034
When counts zero, the F end (F_END) signal 1
062 to the controller 1020. When F end (F_END signal) 1062 is received, the state of the controller becomes FRAME.
IFS timer (IFS_TIME) from COUNT state
R) State 1106 is reached. IFS timer (IFS_TI
In the MER) state 1106, the controller starts I_
START) signal 1058 to interface spacing timer 1032. The interface spacing timer is designed to cause the LAN collision trap circuit to wait an appropriate amount of time between the last frame and the beginning of its pseudo-frame. That is, the IEEE 802.3 interface standard requires a minimum time interval between frames, and the LAN collision trap circuit must comply with this standard. When the interframe spacing timer counts down to zero, the I_END signal 1
056 to the controller 1020. I end (I_END)
Upon receiving the signal, the controller starts the IFS timer (IFS_T
IMER) state 1106 to PF0 state 1108.

In the PF0 state 1108, the LAN collision trap circuit outputs a pseudo frame onto the network 118. In the PF0 state 1108, the controller
An OUT signal 1052 is sent to the digital-to-analog converter circuit 1022, and a VALUE signal 1058 is sent on the network 118 to provide the digital-to-analog converter with the appropriate value for the DC current level of the pseudo frame. After receiving these two signals, digital-to-analog converter circuit 1022 converts this value to an analog value and sends it onto network 118. In the PF0 state 1108, the controller 1020 also sets the maximum start (MAXS
TART) signal 1072 to maximum frame length timer 103
Send to 6. This signal causes maximum frame length timer 1036 to begin timing the maximum length for a given frame. Using this timer, the LAN collision trap circuit 130
can send a maximum allowed length frame over network 118.

The controller remains in the PF0 state 1108 until one of three events occurs. One of these events is the receipt of a MAXEND signal 1076 indicating that the pseudo frame has reached its maximum length, at which point the controller transitions from the PF0 state 1108 to the FRAME_COUNT state 1104. , indicating that there are no nodes on the network that have caused an error during this pseudo frame. Controller 102
When 0 receives either the PREAMBLE signal 1044 or the JAM signal 1042,
Controller is selected from PF0 state 1108 (SELECT)
The state becomes 1110. This change indicates that either a collision signal preamble or a jamming (JAM) signal has been received. In either case, the LAN collision trap circuit must identify the node.

In the SELECT state 1110, the controller 1020 sends an S_SELECT signal 1046 to the source multiplexed sample/hold circuit 1018. This signal is sent to the source multiplexed sample/hold circuit 1018 as a preamble (P
REMBLE) signal 1038 and jamming (JAM) signal 1
040 to hold.

The controller then goes to the SAMPLE state 1112 and outputs the CONVERT signal 108.
6 to the A/D converter circuit 1024, hold (HOLD)
) signal 1048 to the sample/hold circuit while maintaining the S_SELECT signal 1046. Next, the controller is set to the store level (STORE_LEVEL)
The state becomes 1114, and in that state F reset (F_RE
SET) signal 1068 to reset the programmable frame counter. Also, AD output (AD_OUT
PUT) signal 1084 to A/D converter circuit 1024 to cause its converted output to be sent on bus 1080 to FIFO circuit 1026. Controller 1020 then sends a WRITE signal 1088 to FIFO 1026 to cause the value of A/D converter output 1080 to be written to the FIFO. The controller then enters a WAIT state 1116 to give FIFO 1026 time to write data. The controller then enters the STORE_TIME state 1118 and the MAXOUT signal 107
6 to the maximum frame length timer 1036 to determine the collision time (relative to the beginning of the pseudo frame).
TIME) value is output on bus 1082. The controller also sends a P or J (P_OR_J) signal 1077 to bus 10.
Send on 82. The controller also sends a WRITE signal 1088 to write the count value and P
Or write the J (P_OR_J) signal to the FIFO. The controller then sets the frame count (FRAME_CO
UNT) Return to state 1104 and wait until the next time the pseudo frame can be sent on the local area network.

FIG. 13 shows that the signal level of the collision transmission is set to the LAN in order to determine the address of the node causing the collision.
1 shows a flowchart of a portion of correlation software 120 (FIG. 1) that correlates levels detected by a level monitor. In FIG. 13, after entering, at block 1202, the FIF
Determine if O1026 has any collision or disturbance data. If no collision data or additional collision data is stored in the FIFO, block 1
202 returns to the caller. If data is stored in the FIFO, block 1202 moves to block 1204 where the next set of data is read from the FIFO 1206. Block 1206 then determines whether this data represents a jamming signal, and if so, transitions to block 1210. If the data is not of a jamming signal, block 1206 transfers to block 1208, which determines whether the collision was a late collision based on the time of the collision. If the collision is not delayed,
Block 1208 returns to the caller or transitions to block 1210 to determine the address and location of the late conflicting node. Next, at block 1210, the LAN
Compare the crash trap data with the data in the table collected in FIG. The level detected by the LAN collision trap circuit of FIGS. 10 and 11 is the LA of FIGS. 5 and 6.
It is compared to the levels collected by the N level monitor. The matching is done within the tolerance level. This is because even slight variations in signal levels do not represent different nodes. If a match is obtained within the tolerance,
Block 1212 transitions to block 1216, which displays the node addresses of the two colliding nodes. If no match is found, block 1212
moves to block 1214, which displays a message indicating that the node is unknown.

Whether a collision is a valid early collision or an invalid late collision is determined by comparing the time of the collision to the start of the pseudo frame. In its largest configuration, an 802.3 LAN consists of five 185 meter maximum segments (using thin LAN cables) connected by four repeaters. ANSI/IEEE802.3
According to the A-1988 standard, a 185 meter LAN segment (using thin LAN cable) has a propagation delay of less than 9.5 bit times (one bit time is 100 nanoseconds), and a repeater has a propagation delay of 7.5 bits. time, so the maximum delay from one end of a LAN cable in its maximum configuration to the other end is 77.5 bit times. Therefore, a proper collision can only occur during the first 7.75 microseconds of the frame. The maximum length frame is 1518 bytes or 12,144 bit times, which is 1.214 milliseconds. Collisions that occur during the last 1.206 milliseconds of the pseudo frame are late collisions.

Since the interference signal detected in FIGS. 10 and 11 is a 10 MHz signal, the level value is LAN
Slightly different from the level collected by the level monitor. This difference is due to the difference between the attenuation in the cable of the 10 MHz signal and the attenuation that occurs on the 5 MHz preamble signal. Therefore, to compensate for this different loss before making the comparison, block 1210 first adjusts the level value from FIFO 1026 for the jamming signal.

Information from the LAN collision traps about valid early collisions can be used to analyze the backoff timing of each node in the LAN to find anomalies, such as backoff timings that are the same or too short. .

[0065]

[Effects of the Invention] As described above, according to the present invention, the IEE
It is possible to monitor signals on a segment of an E802.3 computer local area network. Furthermore, according to the invention it is possible to measure the signal strength of the signals sent out from each node connected to this network segment. Furthermore, according to the present invention,
It is possible to calculate the position of each node located on a segment of the network based on the signal strength of the signal sent from each node. Furthermore, according to the invention, the position of a node is calculated by measuring the signal strength from the node at two points on the network segment, and the ratio of the signal strength at the second point to the total signal strength at both points is calculated. It is possible to calculate and obtain the distance from the node to the first measurement point. Furthermore, according to the present invention, it is possible to display the location of a node to a user of such a network or an administrator of the network. Furthermore, according to the invention it is possible to detect late conflicting nodes on the network. Furthermore, according to the invention, it is possible to detect nodes that are unable to recognize a carrier signal close to the limit of the permissible carrier transmission level. Furthermore, according to the invention it is possible to detect nodes that emit jamming signals before the end of a valid frame.

Having thus described the presently preferred embodiments of the invention, it will be appreciated that each of the objects of the invention has been satisfactorily accomplished. Additionally, various modifications to the structure and circuitry of the present invention, as well as various embodiments and applications, will become apparent to those skilled in the art without departing from the spirit and scope of the invention. This disclosure and description are illustrative and do not limit the invention in any way, the scope of the invention being better defined by the claims.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer system incorporating the present invention.

FIG. 2 is an illustration of a computer network incorporating the present invention.

FIG. 3 is an illustration of a conventional information frame for an IEEE 802.3 computer network.

FIG. 4 is a block diagram of a LAN level monitor circuit of the present invention.

FIG. 5 is a block diagram of the source address stripper circuit of FIG. 4;

FIG. 6 is a state diagram of the controller circuit of FIG. 4;

FIG. 7 is a top level flow diagram of the LAN level monitor software of the present invention.

FIG. 8 is a flowchart of the storage table function of the LAN level monitor software of the present invention.

FIG. 9 is an explanatory diagram of signal levels regarding carriers of pseudo frames transmitted by the LAN collision trap circuit of the present invention.

FIG. 10 is a block diagram of the LAN collision trap circuit of the present invention.

FIG. 11 is a block diagram of the LAN collision trap circuit of the present invention.

FIG. 12 is a state diagram of a controller for a LAN collision trap.

FIG. 13 is a flow diagram of software for determining late collisions.

[Explanation of symbols]

100 Computer system 102 Processing element 104 System bus 106 Keyboard 108 Display 110 Main memory 112 LAN level monitor 114 Disc 116 Printer 118 Network 120 Data correlation software 122 Operating system 124 Serial interface 126 Serial cable 130 LAN collision trap

Claims (1)

[Claims] 1. A system for determining a bad node on a computer network cable, the system comprising: a signal level determination device connected to the cable to generate a first signal level when a signal is detected in the cable; means and;
signal level detecting means for detecting an invalid signal on the cable and generating a second signal level when the invalid signal is detected; connected to the signal level determining means and the signal level detecting means; and a calculation means for comparing the first signal level and the second signal level to determine the defective node.