JPH04246910A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an overshoot phenomenon or an undershoot phenomenon from generating at an output signal due to an impedance inconsistency with an outside circuit at the time of the high speed operation of a semiconductor integrated circuit. CONSTITUTION:A depression type NMOS transistor 5 is provided between the output terminal of an output buffer circuit whose output stage is constituted of transistors 3 and 4, and an output terminal 7. The gate voltage of the depression type NMOS transistor 5 is controlled by a control voltage inputted to a control voltage input terminal 6. Therefore, the output impedance of the semiconductor integrated circuit can be matched with the input impedance of the outside circuit.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, the present invention relates to a semiconductor integrated circuit having an output buffer circuit whose output stage is constituted by a CMOS circuit.

0002

[Prior Art] Conventionally, semiconductor integrated circuits (hereinafter referred to as LSIs) have various other LSIs at their input terminals and output terminals.
, circuits, elements, etc. are connected via signal lines, thereby configuring a desired system. An LSI is provided with an output buffer circuit composed of a CMOS circuit in its output section, and its electrical characteristics are similar to that of a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) and an N-channel MOS transistor (hereinafter referred to as a PMOS transistor) that constitute a CMOS circuit.
(referred to as an NMOS transistor). These electrical characteristics include the power supply current flowing through the transistor, the switching speed of the transistor, the Vt value and the capacitance value determined at the time of circuit formation. Further, the signals transmitted from the LSI to the external circuit are influenced by the characteristics of the wiring inside the LSI up to the output terminal and the characteristics of the wiring from the output terminal to the external circuit, especially when the LSI operates at high speed.

FIG. 6 is a circuit diagram showing a conventional semiconductor integrated circuit. The output buffer circuit is configured as shown below. There is a PMOS between the power supply VDD and the ground GND.
A transistor 3 and an NMOS transistor 4 are connected in series, and the transistors 3 and 4 are driven by the output of the drive circuit 2. Drive circuit 2 connects input terminal 1 and PMO
Inverters 2a and 2b are cascade-connected between the gate of the S transistor 3 and an inverter 2c is cascade-connected between the input terminal 1 and the gate of the NMOS transistor 4.
2d, which generates a signal according to the internal output signal S1 of the LSI input from input terminal 1,
This signal is supplied to each gate of transistors 3 and 4. An output terminal 12 of the LSI is provided at the output end of the above-mentioned output buffer circuit, that is, at the interconnection point of the transistors 3 and 4, and an external circuit 13 is connected to this output terminal 12.

In the semiconductor integrated circuit configured as described above, either the PMOS transistor 3 or the NMOS transistor 4 is turned on in response to the internal output signal S1, and an external output is provided via the output terminal 12 and the signal line. Signal S2 is transmitted to external circuit 13.

[0005]

[Problems to be Solved by the Invention] However, in the conventional semiconductor integrated circuit described above, the external output signal S2
If the rising or falling speed of S2 is slow, approximately 10 ns or less, the characteristics of the transmission path are not suitable for external output signal S2.
However, when the signal speed increases beyond about 10 ns, the influence of the characteristics of the transmission path on the external output signal S2 cannot be ignored. That is, if the output impedance Z0 of the LSI and the input impedance Zi of the external circuit 13 do not match (mismatch), the LSI
The external output signal S2 is transmitted on the transmission path between the external circuit 13 and
There is a problem in that a reflection phenomenon occurs, and as a result, the output waveform of the external output signal S2 is disturbed, resulting in a so-called overshoot phenomenon or undershoot phenomenon.

FIGS. 7 and 8 are waveform charts showing overshoot and undershoot phenomena in the semiconductor integrated circuit shown in FIG. 6, respectively. Note that FIG. 7 shows the waveform of the external output signal S2 at the output terminal 12 when the low-level internal output signal S1 is input to the input terminal 1, and FIG. 8 shows the waveform of the external output signal S2 at the output terminal 12 when the high-level internal output signal S1 is input to the input terminal 1. External output signal S2 at output terminal 12 when
The waveform of is shown.

As shown in FIGS. 7 and 8, as the signal speed increases, the waveform of the external output signal S2 changes significantly compared to the waveform of the internal output signal S1. Therefore, the internal output signal S1 of the LSI cannot be accurately transmitted to the external circuit 13.

The present invention has been made in view of such problems, and provides a semiconductor integrated circuit that can prevent overshoot and undershoot phenomena from occurring in output signals due to impedance mismatch during high-speed operation. The purpose is to

[0009]

Means for Solving the Problems A semiconductor integrated circuit according to the present invention has at least one semiconductor integrated circuit whose source is connected to the output terminal of an output buffer circuit and whose drain is connected to an output terminal.
A depletion type MOS transistor, and a voltage control means for controlling the gate voltage of the depletion type MOS transistor.

0010

[Operation] In the present invention, at least one depletion type MOS transistor is connected between the output terminal and the output terminal of the output buffer circuit, and the gate voltage of this depletion type MOS transistor is controlled by a predetermined voltage control means. controlled. Therefore, by controlling the gate voltage of the depletion type MOS transistor, the resistance value between the output terminal and the output terminal of the output buffer circuit can be changed. Thereby, the output impedance of the semiconductor integrated circuit at the output terminal can be changed, so that the output impedance of the semiconductor integrated circuit and the input impedance of an external circuit connected to the output terminal can be matched. Therefore, impedance mismatch does not occur during high-speed operation of the semiconductor integrated circuit, and overshoot and undershoot phenomena can be prevented from occurring in the output signal.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

The output buffer circuit is constructed as shown below. There is no PM between the power supply VDD and the ground GND.
An OS transistor 3 and an NMOS transistor 4 are connected in series, and these transistors 3 and 4 are driven by the output of the drive circuit 2. Drive circuit 2 has input terminal 1 and P
Inverters 2a and 2b are cascade-connected between the gate of the MOS transistor 3, and inverter 2 is cascade-connected between the input terminal 1 and the gate of the NMOS transistor 4.
2d, which generates a signal in response to an internal output signal of the LSI input from input terminal 1, and supplies this signal to each gate of transistors 3 and 4. Note that the transistors 3 and 4 have the same ability to drive a load.

Depletion type NMOS transistor 5
is connected to the transistor 3, whose source is connected to the transistor 3 via the output signal line 9.
4 and its drain is connected to the interconnection point of output terminal 6.
It is connected to the. A control voltage input terminal 6 is connected to the gate of the depletion type NMOS transistor 5, and the depletion type NMOS transistor 5 is driven in accordance with a control signal input from the control signal input terminal 6. A voltage dividing circuit 8 is connected to the control signal input terminal 6, and this voltage dividing circuit 8 is composed of a variable resistor 8a connected between the power supply VDD and the ground GND.
It is possible to apply any voltage between VDD (V) and VDD (V). Note that an external circuit or the like is connected to the output terminal 7.

Next, the operation of the semiconductor integrated circuit according to this embodiment will be explained. For example, when an LSI testing device (hereinafter referred to as a tester) is connected as an external circuit, the input impedance of the tester is usually 50Ω, but the output impedance of the LSI has no fixed value and varies depending on the product. For example, when the output impedance of the LSI is 20Ω, impedance matching between the tester and the LSI is not achieved, which adversely affects the output waveform of the LSI as described above.

However, in this embodiment, the LS
The output terminal of the output buffer circuit of I, that is, the transistor 3,
A depletion type NMOS transistor 5 is provided between the interconnection point of 4 and the output terminal 6, and a voltage dividing circuit 8
The gate voltage of the depletion type NMOS transistor 5 can be controlled by the output voltage of the depletion type NMOS transistor 5. By controlling the gate voltage of this depletion type NMOS transistor 5, the resistance value between the output terminal of the output buffer circuit of the LSI and the output terminal 7 can be changed. As a result, the input impedance of the external circuit and L
It is possible to match the output impedance of the SI. Therefore, impedance mismatch does not occur during high-speed operation of the semiconductor integrated circuit, and overshoot and undershoot phenomena can be prevented from occurring in the output signal.

FIG. 2 is a waveform diagram showing the electrical characteristics of a depletion type NMOS transistor, in which the vertical axis shows the drain-source current ID, and the horizontal axis shows the drain-source voltage VDS.

As shown in FIG. 2, in the depletion type NMOS transistor 5, the drain-source current ID increases in proportion to the drain-source voltage VDS in the non-saturation region (to the left of the broken line A in FIG. 2). That is,
The resistance value of the depletion type NMOS transistor 5 is constant in the non-saturation region. However, even if the drain-source voltage VDS is constant, by changing the voltage VGS applied to the gate voltage, the drain-source current ID changes, resulting in a depletion type NMOS.
The resistance value of transistor 5 changes. Therefore, by controlling the gate voltage of the depletion type NMOS transistor 5, the resistance value between the source and drain of the depletion type NMOS transistor 5 can be changed. Note that the depletion type NMOS transistor 5
In the saturation region (to the right of the broken line A in FIG. 2), the drain-source current ID is constant regardless of the drain-source voltage VDS. For this reason, depression type NM
In the saturation region, the resistance value of the OS transistor 5 is
It changes depending on the source-to-source voltage VDS.

FIG. 3 is a waveform diagram showing the input voltage VIN at the input terminal 1 of the output buffer circuit of the semiconductor integrated circuit shown in FIG. FIG. 3 is a waveform diagram showing characteristics. Note that FIG. 4 is a diagram when the power supply voltage and ground voltage of the output buffer circuit are set to VDD (V) and 0 (V), respectively.

As is clear from FIGS. 3 and 4, the input voltage VIN of input terminal 1 varies from 0 (V) to VDD (V).
When the input voltage VIN changes, the output response voltage VOUT of the output line 9 changes continuously in accordance with the change in the input voltage VIN. In order to accurately transmit such an output response voltage VOUT to the external circuit connected to the output terminal 7, the output response voltage VOUT
Even if (=the input voltage to the source of the depletion type NMOS transistor 5) changes from VDD (V) to 0 (V), the resistance value of the depletion type NMOS transistor 5 must remain constant. Therefore, the depletion type NMOS transistor 5 must be used in a non-saturation region (see FIG. 2).

In this embodiment, for example, when the input impedance of the external circuit connected to the output terminal 7 of the LSI is about 50Ω, the output impedance ( The resistance value is set to approximately 50 to 100Ω. In this case, the output voltage of the voltage divider circuit 8 is adjusted to supply an appropriate control voltage to the control voltage input terminal 6, and the gate voltage of the depletion type NMOS transistor 5 is set to approximately 4.
By controlling the output impedance to approximately 50 V
It can be made into Ω. Thereby, the input impedance of the external circuit and the output impedance of the LSI can be matched. At this time, a measuring device is connected to a predetermined location (for example, the output terminal 7), and while the system is operating, the input voltage to the control voltage input terminal 6 is measured while observing the waveform of the output signal with the measuring device. If you adjust
Even more reliable impedance matching is possible.

FIG. 5 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. In this embodiment, a plurality of depletion type MOS transistors are provided between the output terminal and the output terminal of the output buffer circuit, so in FIG. 5, the same components as those in FIG. 1 are given the same reference numerals. A detailed explanation of that part will be omitted.

Depletion type NMOS transistor 5
The sources a to 5e are commonly connected to the interconnection point of the transistors 3 and 4, and the drains are commonly connected to the output terminal 7. A control voltage input terminal 6 is connected to each gate of the depletion type NMOS transistors 5a to 5e via a decoder 10. This decoder 10
are connected to selection signal input terminals 11a to 11c, and the decoder 10 is connected to selection signal input terminals 11a to 11c.
A control voltage is supplied to any one of the depletion type NMOS transistors 5a to 5e depending on the combination of selection signals input to the . The depletion type NMOS transistors 5a to 5e are designed and formed on the LSI so that their resistance values do not overlap when the same control voltage is supplied to each gate electrode.

In this embodiment, even if the input impedances of the external circuits connected to the output terminal 7 are different, an appropriate resistance value can be obtained by combining the selection signals input to the selection signal input terminals 11a to 11c. A depletion type NMOS transistor can be selected. Furthermore, by controlling the gate voltage of the selected depletion type NMOS transistor, more accurate impedance matching can be achieved than in the first embodiment, so this embodiment has high versatility.

[0025]

As explained above, according to the present invention, at least one depletion type MOS transistor is connected between an output buffer circuit and an output terminal, and the depletion type MOS transistor is controlled by a predetermined voltage control means. Since the gate voltage is controlled, the output impedance of the semiconductor integrated circuit and the input impedance of the external circuit connected to the output terminal can be matched. Therefore, impedance mismatch does not occur during high-speed operation of the semiconductor integrated circuit, and overshoot and undershoot phenomena can be prevented from occurring in the output signal.

Therefore, according to the present invention, the output signal of the semiconductor integrated circuit can be accurately transmitted to the external circuit, and stable high-speed operation can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing electrical characteristics of a depletion type NMOS transistor.

FIG. 3 is a waveform diagram showing the input voltage of the output buffer circuit of the semiconductor integrated circuit shown in FIG. 1;

FIG. 4 is a waveform diagram showing input/output characteristics between the input voltage and the output response voltage of the output buffer circuit of the semiconductor integrated circuit shown in FIG. 1;

FIG. 5 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a conventional semiconductor integrated circuit.

7 is a waveform diagram showing an overshoot phenomenon in the semiconductor integrated circuit of FIG. 6. FIG.

8 is a waveform diagram showing an undershoot phenomenon in the semiconductor integrated circuit of FIG. 6; FIG.

[Explanation of symbols]

1; Input terminal 2; Drive circuit 2a, 2b, 2c, 2d; Inverter 3; PMOS transistor 4; NMOS transistor 5, 5a to 5e; Depletion type MOS transistor 6; Control voltage input terminal 7, 12; Output terminal 8; Voltage circuit 8a; variable resistor 9; output signal line 10; decoder 11a, 11b, 11c; selection signal input terminal 13; external circuit

Claims (1)

[Claims] 1. At least one depletion type MOS transistor whose source is connected to an output terminal of an output buffer circuit and whose drain is connected to an output terminal;
A semiconductor integrated circuit comprising voltage control means for controlling the gate voltage of the depletion type MOS transistor.