JPH04246846A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a high integrated semiconductor IC provided with a multilayer interconnection to be enhanced in yield and reliability by a method wherein a semiconductor device forming method and especially a forming method where a layer insulating film provided to a semiconductor device of multilayer interconnection structure is formed are offered, where an SiO2 glass insulating film which is fully turned into glass and free from cracks can be filled flat into a narrow groove whose width is of the order of submicrons through the layer insulating film forming method concerned. CONSTITUTION:A first process where tetraethoxysilane gas is introduced onto a board in a nitrogen or inert gas atmosphere of reduced pressure to form a tetraethoxysilane condensed film on the board concerned, a second process where water vapor is introduced onto the board provided with the condensed film in the atmosphere of reduced pressure the same as above to enable water vapor to react on the tetraethoxysilane condensed film on the board to turn it into a silanol film, and a third process where the board is heated to turn the silanol film into an insulating film of silicon oxide glass through dehydrating reaction.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
In particular, the present invention relates to a method for forming an interlayer insulating film in a semiconductor device having a multilayer wiring structure.

[0002] In recent years, as semiconductor ICs have become more highly integrated, multilayer wiring has come to be used more and more as wiring constituting circuits. Furthermore, the width of wiring patterns, the spacing between wiring patterns, etc. tend to become narrower and narrower.

[0003] When interconnections are multilayered and the spacing between interconnections becomes narrower, the narrow and deep steps formed on the lower interconnection surface are filled with an interlayer insulating film to form upper interconnections. It is extremely important to flatten the top surface of the interlayer insulating film to make the cross-sectional area of the upper layer wiring uniform, to prevent increases in electrical resistance and disconnections due to migration, and to improve the reliability of the semiconductor IC. It's coming.

0004

[Prior Art] Conventionally, the insulating film forming methods mainly used to form the above-mentioned interlayer insulating film include the well-known chemical vapor deposition (CVD) method and organic (rarely inorganic) methods.
There is a spin-on glass (SOG) coating method.

However, chemical vapor grown silicon oxide (CV), which is formed by a gas phase chemical reaction between a silicon source such as ordinary monosilane (SiH4) and an oxidation source such as oxygen (O2),
D-SiO2) film has poor step coverage during growth, so when the interconnect spacing becomes narrower due to higher integration as mentioned above, the schematic diagram of the CVD-SiO2 interlayer insulating film formation surface shown in Fig. 4 As shown in the cross-sectional view, CVD-Si
A groove 56 having a reversely tapered side surface 55 is formed on the space between the lower wirings 53A, 53B, etc. of the O2 interlayer insulating film 54, and is similarly deposited on the interlayer insulating film 54 by sputtering or the like with poor step coverage. Aluminum (A
Groove 56 in the interlayer insulating film 54 of the upper wiring layer 57 such as
An extremely thin portion 58, a fault 59, etc. are formed on the top of the layer, resulting in a problem that the reliability of the upper layer wiring is reduced. (51 is a semiconductor substrate, 52 is a lower insulating film) On the other hand, for example, ethanol [C2H of silanol [Si(OH)4]
After spin-coating SOG consisting of a 5OH] solution, etc.
In the SOG coating method in which the coating film is vitrified by heating, as shown in the schematic cross-sectional view of the surface on which the SOG interlayer insulating film is formed in FIG.
Although the upper surface of the interlayer insulating film 60 can be flattened by sufficiently filling the gaps such as B, when the SOG film 60 is heated and vitrified, cracks 61 are formed in the thick portions of the SOG film 60. It enters the lower layer wiring 53A and becomes hygroscopic.
, 53B, etc., and the lower layer wiring 53A, etc.
53B etc., which caused deterioration due to corrosion. Also, when forming a contact window in this SOG interlayer insulating film and forming an upper wiring layer on it, a thick layer of SOG was applied.
Since the OG interlayer insulating film is not completely vitrified by the heat treatment, gases such as water vapor are released into the contact window, and a nonconductor film such as a natural oxide film is formed on the lower wiring surface exposed in the contact window. There is also the problem that the contact resistance between the lower layer wiring and the upper layer wiring increases due to the formation.

Furthermore, in the above-mentioned SOG coating method, in order to prevent the occurrence of cracks and generation of gas, a process of applying a thin SOG film and vitrifying it by heat treatment is repeated to form an SOG film of a predetermined thickness. A method was also tried to do this, but even with this method, when the width of the groove formed between the lower wiring lines narrowed to the submicron order, a thick layer of SOG liquid would accumulate in the recesses between the wiring lines after one application. It is extremely difficult to vitrify this SOG film by heating with a lamp or the like without causing cracks in the SOG film in that area.

[0007]

[Problems to be Solved by the Invention] Therefore, the present invention aims to provide an interlayer structure that allows a SiO2 glass-based insulating film that is completely vitrified and does not cause cracks to be flatly buried in a narrow trench on the order of submicrons. It is an object of the present invention to provide a method for forming an insulating film, and to improve the yield and reliability of highly integrated semiconductor ICs having multilayer wiring.

[0008]

[Means for Solving the Problems] The above-mentioned problems include a step of introducing tetraethoxysilane vapor onto a substrate in a reduced pressure atmosphere of nitrogen or inert gas to form a tetraethoxysilane condensed film on the substrate; A step of introducing water vapor onto the substrate having a tetraethoxysilane condensed film in a reduced pressure atmosphere of nitrogen or inert gas and converting the tetraethoxysilane condensed film into a silanol film by reaction with the water vapor, and heating the substrate. The method for manufacturing a semiconductor device according to the present invention includes a step of changing the silanol film into an insulating film made of silicon oxide glass by a dehydration reaction, or forming a lower conductor pattern on an insulating film formed on a semiconductor substrate. , a method for manufacturing a semiconductor device comprising the steps of forming an interlayer insulating film on the formation surface of the lower conductor pattern and forming an upper conductor pattern on the interlayer insulating film, when forming the interlayer insulating film; , a first step of spraying tetraethoxysilane vapor onto the formation surface of the lower conductor pattern to deposit a condensed film of tetraethoxysilane on the formation surface of the lower conductor pattern; A second step in which water vapor is sprayed onto the lower conductor pattern forming surface having a condensed film, and the tetraethoxysilane condensed film is changed into a silanol film by a chemical reaction.
and a third step of changing the silanol film into a silicon oxide glass film through a dehydration reaction through heat treatment, and forming the lower conductor pattern by repeating the first, second, and third steps in sequence. The problem is solved by a method of manufacturing a semiconductor device, which includes the step of forming an interlayer insulating film of a predetermined thickness made of silicon oxide glass and having a planarized upper surface on the surface.

[0009]

[Function] Fig. 1 is a process sectional view for explaining the principle of the present invention, in which 1 is a reaction vessel, 2 is a shower for gas introduction, 3 is a vacuum exhaust port, 4 is a tetraethoxysilane (TEOS) introduction valve, 5 is water vapor (H2O) introduction valve, 6 is nitrogen (N
2) An introduction valve, 7 a substrate stage, 8 an infrared lamp, and 9 a substrate.

That is, in the method of the present invention, FIG.
As shown in the figure, after placing the substrate 9 on which an insulating film is to be formed on the substrate stage 7 and reducing the pressure inside the reaction container 1 with N2, [Si(OC2H5)4] is placed in the reaction container 1.
A vapor 110 of tetraethoxysilane (TEOS) having a certain composition is introduced so as to be blown onto the substrate 9 via a shower 2, for example, to form a condensed film 10 of TEOS on the substrate.

Next, after purging the inside of the reaction vessel 1 with N2 and further reducing the pressure, water vapor (H2O) 111 is applied to the substrate 9, that is, the condensed film 10 of TEOS, through the shower 2, as shown in FIG. 1(b). was introduced by spraying Si(O
C2H5)4+H2O → Si(OH)4+4C2H
The TEOS condensation film 10 is converted into S by the reaction of 5OH ↑.
Silanol [Si(OH)4], which is the same component as OG
The film is changed into a film 12.

Next, after purging the inside of the reaction vessel 1 with N2,
For example, the substrate 9 is heated to 500 to 800
The silanol [Si(OH)4] film 12 is dehydrated and hardened (vitrified) by heating to about .degree.

[0013] The thickness of the SiO2 glass insulating film 13 formed in the above one cycle process is 500 to 1000.
Since the SiO2 glass insulating film has a predetermined thickness of about 5,000 to 10,000 Å, the above steps are repeated about 10 cycles to form a SiO2 glass insulating film having a predetermined thickness of about 5,000 to 10,000 Å.

According to this method, the TEOS condensed film 10 is deposited on the inner surface (side surface and bottom surface) of a groove having a narrow width on the order of submicrons, as a thin film that is slightly thicker at the corner portions. Therefore, the SiO2 glass insulating film 13, which is formed by converting the TEOS condensed film 10 into silanol and vitrifying the silanol film by heat treatment, is sufficiently vitrified without cracking, and the corners of the grooves are slightly thicker. It is formed as a thin film.

[0015] Therefore, by repeating the above steps, the above SiO
Since cracks do not occur in the SiO2 glass insulating film that is flatly embedded in the groove by laminating the two glass insulating films 13, sufficient moisture resistance is ensured. In addition, since the glass has been sufficiently vitrified, when forming a contact window and forming an upper wiring metal layer on it, gas is not released from the SiO2 glass insulating film into the contact window and the wiring interface is Since oxidation, contamination, etc. are avoided, an increase in contact resistance between wiring layers is also prevented.

[0016]

EXAMPLE The present invention will be specifically described below with reference to an example of the manufacturing apparatus shown in FIG. 2 and a process cross-sectional view of an example shown in FIG. 3.

In FIG. 2 showing an example of the manufacturing apparatus used in the method of the present invention, 1 is a reaction vessel, 2 is a gas introduction shower, 3 is a vacuum exhaust port, 4 is a TEOS introduction valve, and 5 is a gas introduction shower.
is a steam introduction valve, 6 is a N2 introduction valve, 7 is a substrate stage, 8 is an infrared lamp, 9 is a substrate, 14 is a TEOS
Container, 15 is a hot air circulating constant temperature layer that heats the TEOS to about 60-70°C, 16 is a pure water container, 17 is a constant temperature water tank that heats pure water to about 50°C, 18 is a replacement N2 supply pipe, 19
is the N2 supply pipe for purging, 20 is the TEOS supply pipe, 21 is the steam supply pipe, 22A, 22B, 22C, 22D
are temperature controllers 23A and 23B using thermocouples.
, 23C, 23D, etc., 24A,
24B, 24C, and 24D are gas flow meters (for low differential pressure), 25 is a N2 purge valve, and 26 is a TEOS steam source valve.

When forming an interlayer insulating film of a semiconductor IC by the method of the present invention, for example, as shown in FIG. 3(a), a lower insulating film 32 is formed on a semiconductor substrate 31;
A substrate to be processed 34 (corresponding to 9 in FIG. 2) on which a plurality of polysilicon wirings 33A, 33B, etc. of submicron width are formed at submicron intervals on this lower layer insulating film 32,
After placing the substrate on the substrate stage 7 in the reaction container 1 in FIG. 2 and replacing the inside of the reaction container 1 with N2, exhaust is performed from the vacuum exhaust port 3 to reduce the pressure inside the reaction container 1 to about 1 to 10 Torr. While maintaining the temperature, open the valve 4 and use the gas introduction shower 2 to remove the TEOS, which has been maintained at room temperature to approximately 50°C.
The vapor 110 is transferred to the substrate 3 to be processed as shown in FIG. 3(a).
4 for several seconds as if spraying onto the substrate 3 to be processed.
A TEOS condensed film 10A having a thickness of approximately 500 to 1000 Å is formed on the surface of the TEOS film 10A along the surface thereof.

Next, the TEOS introduction valve 4 in FIG. 2 is closed, the inside of the reaction vessel 1 is replaced with N2, the pressure is reduced to about 1 to 10 Torr, and the valve 5 is opened, as shown in FIG. 3(b), from room temperature to 50°C. The water vapor 111 maintained at a certain level is blown onto the substrate 34 to be processed on which the TEOS condensed film 10A is formed, reacts with H2O, and evaporates the reaction product C2H5OH by vacuum evacuation to form silanol [Si(OH)]. )4] film 12A.

Next, the valve 5 in FIG. 2 is closed, the valve 6 is opened, and the inside of the reaction vessel 1 is replaced with N2. Then, the inside of the reaction vessel 1 is evacuated to a specified level to create an N2 atmosphere of about several Torr, and the infrared lamp 8 is turned on. The surface of the substrate 1 is heated to, for example, about 700° C. for about 15 seconds using infrared rays (I.R.) emitted from the silanol film 12A to a thickness of about 500 to 1000 Å by dehydration reaction, as shown in FIG. 3(c). The first SiO2 glass insulating film 13A is completely vitrified and cured, and has no defects such as cracks.

Next, the formation of the TEOS condensed film, TEOS
Reaction of OS condensation film with water vapor, and I. The R heating process is repeated, for example, about 5 times, and as shown in FIG. 3(d), the first and second layers are completely vitrified and hardened to a thickness of about 500 to 1000 Å, and have no defects such as cracks.
, third, fourth, fifth and sixth SiO2 glass insulating films,
13A, 13B, 13C, 13D, 13E,
13F is laminated, thickness 3000-6000 Å
A SiO2 glass interlayer insulating film 13 is formed.

Note that in the above method, the TEOS condensed film 1
0A, etc., adheres thickly to the corners of the groove, so the
), as the first, second, and third SiO2 glass insulating films are stacked, the corners of the SiO2 glass interlayer insulating film 13 become gently rounded, and finally, as shown in the figure, the SiO2 glass interlayer insulating film 13 becomes polygonal. The upper surface of the SiO2 glass interlayer insulating film 13 above the submicron width trench between the silicon interconnections 33A and 33B is substantially flattened.

Next, as shown in FIG. 3(e), for example, an aluminum wiring 35 is formed on the SiO2 interlayer insulating film 13 by ordinary sputtering and patterning methods to form a multilayer structure using the interlayer insulating film according to the present invention. The wiring structure is completed.

[0024]

As described above, according to the present invention, it is possible to form an interlayer insulating film that is completely vitrified and hardened and that does not cause cracks even in the grooves between wirings having a narrow width on the order of submicrons. Since an interlayer insulating film with a flattened top surface can be formed by embedding, the reliability of the upper layer wiring formed on the interlayer insulating film is ensured, and at the same time, the moisture resistance of the interlayer insulating film is improved, increasing the reliability of the lower layer wiring. Sexuality also improves. Furthermore, since the interlayer insulating film according to the present invention is completely vitrified, gas is not released into the contact window when wiring connections are formed, and the lower wiring surface is prevented from becoming nonconductive. Low contact resistance at the connection portion is ensured.

As described above, the present invention is extremely effective in improving the yield and reliability of semiconductor devices having a multilayer wiring structure.

[Brief explanation of the drawing]

[Figure 1] Process cross-sectional diagram for explaining the principle of the present invention

[Figure 2]
A schematic configuration diagram of an example of a manufacturing device used in the present invention

[Figure 3]
Process sectional view of an embodiment of the method of the present invention

[Figure 4]
Schematic cross-sectional view of CVD-SiO2 interlayer insulation film formation surface

[Figure 5
] Schematic cross-sectional view of the SOG interlayer insulation film formation surface

[Explanation of symbols]

1 Reaction container 2 Gas introduction shower 3 Vacuum exhaust port 4 Tetraethoxysilane (TEOS) steam introduction valve 5 Water vapor (H2O) introduction valve 6 Nitrogen (N2) introduction valve 7 Substrate stage 8 Infrared lamp 9 Substrate 10 TEOS condensed film 12 Silanol Film 13 SiO2 glass insulation film 110 TEOS vapor 111 Water vapor IR Infrared

Claims (2)

[Claims] 1. A step of introducing tetraethoxysilane vapor onto a substrate in a reduced pressure atmosphere of nitrogen or inert gas to form a tetraethoxysilane condensed film on the substrate;
a step of introducing water vapor onto the substrate having the tetraethoxysilane condensed film in a reduced pressure atmosphere of nitrogen or inert gas and converting the tetraethoxysilane condensed film into a silanol film by reaction with the water vapor; 1. A method for manufacturing a semiconductor device, comprising the step of heating and converting the silanol film into an insulating film made of silicon oxide glass through a dehydration reaction. 2. A lower conductor pattern is formed on an insulating film formed on a semiconductor substrate, an interlayer insulating film is formed on the surface of the lower conductor pattern, and an upper conductor pattern is formed on the interlayer insulating film. In a method for manufacturing a semiconductor device that includes a step of forming a conductor pattern, when forming the interlayer insulating film, tetraethoxysilane vapor is sprayed onto the formation surface of the lower conductor pattern to form the lower conductor pattern. A first step of depositing a condensed film of tetraethoxysilane on the forming surface, and spraying water vapor onto the lower conductor pattern forming surface having the condensed film of tetraethoxysilane to form the tetraethoxysilane through a chemical reaction. The method includes a second step of changing the condensed film into a silanol film, and a third step of changing the silanol film into a silicon oxide glass film through a dehydration reaction by heat treatment, and the first, second, and third steps are performed. A method for manufacturing a semiconductor device, comprising the steps of sequentially and repeatedly forming an interlayer insulating film of a predetermined thickness made of silicon oxide glass and having a flattened upper surface on the surface on which the lower conductor pattern is formed.