JPH04246708A - Dc constant-voltage circuit - Google Patents

Abstract

PURPOSE:To prevent the oscillation and to suppress a sudden increase of an input current. CONSTITUTION:When an input voltage Vin drops, an output voltage Vout of an output transistor Q2 drops. When a non-inversion input terminal voltage of a differential amplifier obtained by dividing Vout becomes lower than a reference voltage Vs of an input terminal, an output current of the differential amplifier increases suddenly. Therefore, a base current I1 increases, and a driving current ID increases. In this case, since the output voltage Vout rises, diodes D1, D2 are turned on and a forward current I2 flows, and I1 is decreased. Accordingly, by suppressing the driving current, a sudden increase of an input current Iin can be prevented.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a DC constant voltage circuit.
In particular, the present invention relates to a DC constant voltage circuit configured to suppress a sudden increase in input current.

0002

2. Description of the Related Art FIG. 2 is a circuit diagram of an example of a conventional DC constant voltage circuit (hereinafter referred to as a constant voltage circuit). In FIG. 2, 2 represents a differential amplifier, 3 represents an input terminal, and 4 represents an output terminal. A constant current source I1 and a Zener diode D3 connected in series are connected between the input terminal 3 and the ground, and the Zener diode D3 is connected to a reference voltage V.
S is occurring. The reference voltage VS is input to the inverting input terminal of the differential amplifier 2.

The output terminal of the differential amplifier 2 is connected to the base of a PNP type control transistor Q1. The collector of control transistor Q1 is connected to ground, and the emitter is connected to P.
It is connected to the base of the NP type output transistor Q2. The emitter of the output transistor Q2 is connected to the input terminal 3, and the collector is connected to the output terminal 4. The output voltage Vout output by the output transistor Q2 is determined by resistors R8 and R9 connected in series between the output terminal 4 and the ground.
The voltage is divided by and input to the non-inverting input terminal of the differential amplifier 2. The broken line portion 8 is a cross-over current control circuit which will be described later.

In the figure, an unregulated power supply voltage (hereinafter referred to as input voltage) Vin inputted to an input terminal 3 is stabilized and outputted as an output voltage Vout to an output terminal 4 via an output transistor Q2. Ru. In this case, the differential amplifier 2 connects the reference voltage VS generated by the Zener diode D3 and the output voltage Vout to the resistors R8 and R
9, the comparison error voltage is detected, and the output transistor Q2 is controlled via the control transistor Q1.

That is, when the input/output voltage difference decreases and the output voltage Vout decreases below a predetermined value, the non-inverting input terminal voltage of the differential amplifier 2 becomes lower than the reference voltage VS. As a result, the output voltage of the differential amplifier 2 decreases, the drive current ID of the control transistor Q1 increases, and the output transistor Q2 is driven so that the output voltage Vout approaches the input voltage Vin.

Next, FIG. 3 is a diagram showing the input/output characteristics of a conventional constant voltage circuit. Here, the input characteristics will be explained with reference to FIG. In the absence of the circuit indicated by the broken line portion 8 in FIG. 2, as the input voltage Vin input to the input terminal 3 rises, the output voltage Vout (dashed line) also rises, and if the input voltage Vin is, for example, 3. When the output voltage Vout reaches 2 V, the output voltage Vout is made constant at 3.0 V. On the other hand, the input current Iin (solid line) increases rapidly as the input voltage Vin rises until the output voltage Vout enters the stable region.
The maximum current flow is, for example, about 14 mA.

[0007] Next, the reason why the input current Iin suddenly increases (so-called peak current) in a region where the input/output voltage difference of the output transistor decreases due to such a decrease in the input voltage Vin will be explained.

FIG. 4 is a diagram showing the grounded emitter electrostatic property of a transistor. In FIG. 4, the horizontal axis shows the collector-etcher voltage VCE of the transistor, and the vertical axis shows the collector current IC. If the input/output voltage difference VCE of the output transistor Q2 is, for example, 3 [V] in a normal operating state, a base drive current IB3 is required to obtain the collector output current IO shown in the figure.

When the input/output voltage difference VCE drops to, for example, about 1 [V], a drive current indicated by IB5 in the figure is required in order to obtain the same output current as IO. When the input/output voltage difference VCE drops below 1 [V], an even larger drive current is required, and the upper limit of the drive current (IBMAX
), and a mountain current is generated.

The over-hill current control circuit 8 in FIG. 2 is provided to suppress such over-hill current. In FIG. 2, the PNP transistor Q9 is connected in a current mirror to the output transistor Q2. The collector of the transistor Q9 is connected to the collector of an NPN transistor Q10 which is connected in a current mirror manner to a diode-connected NPN transistor Q11. The emitters of transistors Q10 and Q11 are connected to ground.

Resistors R10 and R11 are connected in series, one end of resistor R10 is connected to input terminal 3, and one end of resistor R11 is connected to P.
Connected to the emitter of the NP type transistor. The collector of the transistor Q11 is connected to the connection point between the resistors R10 and R11. Transistor Q7 is diode-connected and current mirror-connected to PNP transistor Q8. The emitter of the transistor Q8 is connected to the output terminal 4, and the collector is connected to the base of the control transistor Q1. A constant current source I5 is connected between the collector of the transistor Q7 and the ground.

In the constant voltage circuit provided with the over-peak current control circuit 8 having the above configuration, over-the-peak current is suppressed in the following manner. That is, in the above configuration, since the transistors Q2 and Q9 form a current mirror circuit, a current proportional to the current flowing to the emitter-collector of the output transistor Q2 (output current I0) flows to the emitter-collector of the transistor Q9. On the other hand, transistor Q10,
Since Q11 also constitutes a current mirror circuit, a current proportional to the current flowing through the collector-emitter of transistor Q10 flows through transistor Q11 as current I4. That is, the current I4 flows depending on the output current I0.

Therefore, depending on the output current I0, the resistance R
10 voltage drops change. When the input voltage Vin is low and the output current I0 is small, the input/output voltage difference VCE is reduced by the resistance R.
In the astable region equal to the sum of the voltage drops across R10 and R11, transistor Q8 conducts. This reduces the base current of the control transistor Q1 and suppresses the drive current ID. Therefore, I shown by the dashed line in FIG.
It is possible to suppress the current across the mountains like in.

[0014]

[Problem to be Solved by the Invention] However, according to the above-mentioned constant voltage circuit, the control transistor Q is not included in the output circuit.
1, an output transistor Q2, and a current mirror transistor Q8 constitute a loop having a gain of three stages of amplification elements. Also, the output transistor Q2
is a large power transistor and serves as a large capacity load.

Therefore, the above output circuit has a maximum phase of 3
Since the angle can change up to ×90=270 [°], oscillation may occur. In particular, there is a drawback that oscillation is more likely to occur as the DC gain is increased in an attempt to stabilize the output voltage Vout.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a DC constant voltage circuit that can obtain a stable output voltage without causing oscillation.

[0017]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an output transistor via a control transistor at the output of a differential amplifier that compares the divided output DC voltage and a reference voltage. In a DC constant voltage circuit that obtains a constant voltage by controlling a base current, at least one diode and a current limiting resistor are connected in series between the output of the output transistor and the output of the differential amplifier; The diode is configured to conduct when the output voltage difference decreases.

[0018]

[Operation] When the input/output voltage difference of the DC constant voltage circuit becomes small, the diode becomes conductive and a forward current flows. This reduces the base current of the control transistor. Therefore, the control transistor controls the base current of the output transistor to be reduced.

[0019]

[Embodiment] Next, an embodiment of the present invention will be described. FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 1, the collector of output transistor Q2 is connected to the anode of diode D1 via current limiting resistor R1. The cathode of the diode D1 is connected to the anode of a Schottky barrier diode (SBD) D2, and the cathode of the diode D2 is connected to the base of the control transistor Q1. Emitter of control transistor Q1 and output transistor Q
A current limiting resistor R2 is connected to the base of 2.

According to this embodiment with the above configuration, the output voltage V
In a steady state when the input voltage Vin is input, where out is near the set value 5.0 [V], the output voltage V
The resistors R8 and R9 are connected so that the voltage at the non-inverting input terminal of the differential amplifier 2 obtained by dividing out by the resistors R8 and R9 has approximately the same voltage value as the reference voltage VS (for example, 1.25V) input to the inverting input terminal. The value of is set. Therefore, the base current of the transistor Q1 is zero or only a very small amount flows.

On the other hand, the output voltage of the differential amplifier 2 is Vin-
2VBE (however, VBE is transistor Q1, Q2
(base-emitter voltage). In a steady state, the value of the difference between the output voltage Vout and (Vin-2VBE) is equal to the forward voltage VF1 (for example, 0.6 V) of the diode D1 and the forward voltage VF2 (for example, 0.6 V) of the diode D2.
For example, D1
, D2 are either off or only a very small forward current flows.

On the other hand, when the output voltage Vout decreases due to a decrease in the input voltage Vin, and the voltage divided by the resistors R8 and R9 decreases below the reference voltage VS, the output current of the differential amplifier 2 tends to increase rapidly. Therefore, the base current I1 of transistor Q1 increases, and the base current of transistor Q2 increases. Therefore, the difference between the output voltage Vout and (Vin-2VBE) becomes larger than in the steady state, and the diodes D1 and D2 turn on.
A forward current I2 flows and reduces the base current I1.

The constant voltage circuit of this embodiment operates as described above, and when the input voltage Vin decreases, the drive current ID is suppressed to prevent overcurrent, and the input/output voltage difference is maintained at the set value. For balance, diodes D1 and D
2 characteristics and the values of the resistors R1 and R2 are selected.

According to this embodiment, the output circuit is composed of a resistor, a diode, and transistors Q1 and Q2. The output circuit according to the embodiment with the above configuration includes only two transistors that are amplification elements. For this reason,
The phase changes only up to 2×90=180 [°] at the maximum. Therefore, this output circuit is free from the risk of oscillation.
It can operate stably.

Furthermore, according to this embodiment, the peak current prevention circuit 1 is more efficient than the peak current prevention circuit 8 of the conventional DC constant voltage circuit.
Since the number of parts can be reduced by about half, there are also advantages such as lower parts costs and the ability to downsize the circuit board.

Furthermore, in this embodiment, an example has been described in which both the control transistor and the output transistor are of the NPN type, but each transistor may be of the PNP type. Further, the number of diodes connected between the output terminal and the base of the control transistor is not limited to two, and any number may be used as long as the diodes have the characteristics that can reduce the base current of the control transistor to a desired value.

[0027]

[Effects of the Invention] As described above, according to the present invention, a sudden increase in input current can be suppressed without oscillation.
It has the advantage of providing stable output voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional DC constant voltage circuit.

FIG. 3 is a diagram showing input/output characteristics of a conventional DC constant voltage circuit.

FIG. 4 is a diagram showing common emitter electrostatic properties of a transistor.

[Explanation of symbols]

Q1 Control transistor Q2 Output transistor D1, D4 Diode D2, D5 Schottky barrier diode R1
~R3 resistance

Claims (1)

[Claims] 1. A DC constant voltage circuit that obtains a constant voltage by controlling the base current of an output transistor via a control transistor at the output of a differential amplifier that compares a divided output DC voltage and a reference voltage, At least one diode and a current limiting resistor are connected in series between the output of the output transistor and the output of the differential amplifier, and the diode is configured to conduct when the input/output voltage difference of the output transistor decreases. Characteristic DC constant voltage circuit.