JPH04245778A - Decoding device - Google Patents

Abstract

PURPOSE:To offer a decoding device capable of rapidly processing the decoding operation of code data in which the number of significant code bits and an inserting position are not determined. CONSTITUTION:A shift register 11 for storing input code data and a shift register 12 for storing data transferred from the register 11 are arranged, a code analyzing part 20 analyzes the decoding mode of data stored in the register 12, and a shift/transfer control part 30 segments and transfers the data stored in the register 11 only by filling a data blank part with data in the register 12, so that decoding operation can rapidly be processed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device used for facsimile image restoration and the like.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 6, a device of this type has a parallel/serial converter 1 which serially outputs code data bit by bit, which is cut out word by word and inputted in parallel.
and a code analysis unit 2 that performs code analysis processing for determining a decoding mode using the code data output bit by bit from the parallel/serial conversion unit 1, and uses the analysis results of this code analysis unit 2 and reference. Restored image data has been drawn based on the detection results of change points in line image data (see, for example, Japanese Patent Laid-Open No. 105930/1983).

0003

[Problems to be Solved by the Invention] However, this configuration has a problem in that the decoding processing speed becomes slow. The above problem arises for the following reasons.

That is, for example, in the MH coding system or the MR coding system, the number of bits of the significant code indicating the decoding mode is not determined. For example, the code indicating the pass mode is 4 bits "1000", but VR (3
) is a 7-bit code indicating the decoding mode of "1100000". Further, the code indicating the code mode of VL(1) is 3 bits of "010". Moreover, the insertion positions of these significant codes within a word are not determined. In order to determine a significant code in which the number of bits and the insertion position are not determined, conventionally, the parallel/serial converted bit data string is shifted one bit at a time while being fed to the code analysis unit 2. Code analysis processing was performed for each 1-bit shift. As a result, 1
Only one bit of encoded data can be processed in one analysis operation, and this has hindered speeding up of the decoding process.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a decoding device that can process code data at high speed in which the number of bits of a significant code and the insertion position are not determined.

[0006]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a first register for holding input code data that is extracted word by word and transferred in parallel; A second register that holds three or more words of bit data to be transferred is used, and the decoding mode is determined by the first word of bit data transferred to this second register. At the same time, data bits that have undergone code analysis are pushed out and removed from the second shift register by serial shift, and data bits created by this pushing out are transferred to the first register. The data held in the memory is cut out by the number of bits that fills the blank space and transferred.

[0007]

[Operation] With the above-described configuration, the present invention allows unprocessed code data of a plurality of bits to be newly analyzed each time one analysis processing operation is completed. It becomes possible to process code data whose insertion position is not fixed at high speed.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic configuration of a decoding device according to an embodiment of the present invention, in which reference numeral 11 denotes a block 11 for holding input code data that is input in parallel one word at a time from an external device such as a modem. Register 1, 12 is a second register that holds three words or more of bit data transferred in parallel from the first register 10, and 20 is the first register to transfer among the bit data held by the second register. A code analysis unit 30 performs a code analysis process for determining a decoding mode using the bit data for one word, and the code analysis unit 30 uses the data bits that have been analyzed by the code analysis unit 20 to
The data held in the first register 11 is removed by serial shifting from the shift register 12 by serial shifting, and the data held in the first register 11 is cut out by the number of bits to fill the blank space. This is a shift and transfer control unit that transfers data in parallel.

[0010] Here, the first register 11 holds input code data for one word, and also divides the held code data in the LSB direction (direction toward the leading edge of the shift string) and MSB direction.
It is configured using shift registers that can shift the number of bits corresponding to a maximum of one word in each direction (toward the rear end of the shift column). second register 12
is configured using a shift register having a shift string of 3 words or more, and the arbitrary number of bits (however, 1
At the same time, one word's worth of bit data at the leading end of the shift string is input to the code analysis section 20 in parallel. The shift/transfer control unit 30 performs shift operations in the first and second registers 11 and 12 and data transfer between the first and second registers 11 and 12 based on the analysis results of the code analysis unit 30. control. Each part 11, 1 mentioned above
A part or all of 2, 20, and 30 can also be configured in software using, for example, a microcircuit computer, a so-called microcomputer.

The operation of the decoding device configured as described above will be explained below. In addition, in the following explanation,
For ease of understanding, the word length (number of bits) of the input code data in the first register 11 and the code analysis unit 20
The following description assumes that the word length of the input code data in both cases is 8 bits.

FIGS. 2 to 5 show the operation of the above-mentioned apparatus according to its state. First, in FIG. 2, the second register 1
The state is shown in which the 8-bit data "XXXXXXXX" shifted to the leading shift column of No. 2 does not contain a significant code specifying the composite mode as a result of analysis by the code analysis unit 20. In this case, the 8-bit data sent to the leading shift column “XXXXXX
XX'' is pushed out and removed from the second register 12 by shifting toward the front end of the shift column. This results in
The 8-bit unprocessed code data “00001000” located behind the pushed out data “XXXXXXXX” is newly set in the leading end shift column of the second register 12, and the code analysis unit 20 is subjected to analysis processing. At this time, in the illustrated example, the 4-bit code "1000" indicating the pass mode is determined from the data "00001000" that has been newly subjected to the analysis process. On the other hand, due to the above-mentioned extrusion and elimination, a data margin portion corresponding to 8 bits is generated on the rear end side of the second register 12. The 8-bit data "00011100" held in the first register 11 is transferred (loaded) in parallel to this blank space.
and replenishment.

FIG. 3 shows the path mode code "10" in FIG.
00" is determined, and shows the state of the operation that is performed subsequently.

Here, the 4-bit pass mode code "1000" that has been analyzed is pushed out and removed from the second register 12 by shift feeding, and as a result of this pushing out, a 4-bit pass mode code "1000" is generated at the rear end side of the second register 12. Four bits of data "0101" are cut out in address order from the first register 11 in the 4-bit data margin and transferred in parallel. On the other hand, the 4-bit pass mode code “100
0” is pushed out, the same number of bits behind it (4
The data “0110” (bit) is shifted and sent to participate in the analysis input data of the code analysis unit 20. This results in
In the illustrated example, after the pass mode code "1000" is pushed out, a 7-bit code "1100000" indicating the composite mode of VR(3) is determined.

FIGS. 4 and 5 show the state of the operation that continues after the VR(3) mode code "1100000" is determined in FIG. 3.

Similar to the above case, the 7-bit VR(3) mode code "1100000" that has been analyzed is the second one.
The 7-bit data is cut out from the first register 11 in the 7-bit data margin created at the rear end of the second register 12 by this extrusion and removal. are transferred in parallel. In this case, the first register 11 stores 1 word (8 bits) of data in the previous operation.
4 bits have already been cut out. Therefore, in this case, as shown in FIGS. 4 and 5, the remaining 4 bits of data "1001" and the next input word of code data "00111010" are extracted. The 3-bit data "010" is transferred to the 7-bit blank area in address order. on the other hand,
At the leading end of the shift column where the 7-bit pass mode code "1100000" was located, the same number of bits (
7 bits) data “10000010” is shifted and sent to participate in the analysis input data of the code analysis unit 20. In the illustrated example, after the VR (3-mode code ``1100000'' is pushed out), the 3-bit code ``010'' indicating the decoding mode of VL(1) is determined.

As described above, each time one analysis processing operation is completed, a plurality of bits of unprocessed encoded data can be newly subjected to analysis processing. As a result, code data in which the number of bits of the significant code and the insertion position are not determined can be processed at high speed.

[0018]

As is clear from the above description, the present invention includes a first register that holds input code data that is extracted word by word and transferred in parallel; A second register that holds three or more words of bit data is used, and a code for determining the decoding mode is determined based on the first word of bit data transferred to this second register. At the same time as performing the analysis process, the data bits that have been subjected to the code analysis process are pushed out and removed from the second shift register, and the data bits generated by this pushing out and removal are held in the first register. By cutting out and transmitting the data by the number of bits that fills the blank space, multiple bits of unprocessed encoded data can be newly analyzed each time one analysis processing operation is completed. This has the effect that code data in which the number of significant code bits and the insertion position are not determined can be processed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing the main parts of a decoding device according to an embodiment of the present invention.

[Figure 2] Diagram showing an example of the operation of the same main part by state

[Figure 3] Diagram showing an example of the operation of the same main part by state

[Figure 4] Diagram showing an example of the operation of the same main part by state

[Figure 5] Diagram showing an example of the operation of the same main part by state

FIG. 6 is a schematic configuration diagram of a conventional decoding device.

[Explanation of symbols]

11 First register 12 Second register 20 Code analysis section 30 Shift/transfer control section

Claims (1)

[Claims] Claims 1: A first register that holds input code data that is extracted word by word and transferred in parallel, and a second register that holds at least three words of bit data that is transferred from the first register. a register, a code analysis means that performs code analysis processing for determining a decoding mode using bit data of one word transferred first among the bit data held by the second register, and an analysis performed by the code analysis means. The processed data bits are pushed out and removed from the second shift register by serial shifting, and the data held by the first register is filled in the data margin created by this pushing out. A decoding device comprising a control means for extracting and transmitting bits corresponding to the number of bits.