JPH04243065A - Signal processing circuit for direct read after write type optical disk - Google Patents

Abstract

PURPOSE:To process an addition of margin bit at high speed by making a circuit wherein the margin bit is produced, to a ROM. CONSTITUTION:The values of J, K, V are stored in the ROM 270 and each value corresponding to data are inputted to an enable pattern selecting circuit 273 and a priority calculating circuit 274. A DSV is calculated by a circuit 272 and the result is supplied to the circuit 274, and the pattern, the priority of which is decided in the circuit 274, is selected by a decision circuit 275, then this pattern is added to the data as the margin bit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for processing digital signals of a write-once optical disc, that is, a write-once compact disc.

0002

2. Description of the Related Art Recently, audio compact discs have been widely used as laser-based optical storage media, and analog records are increasingly being replaced by compact discs.

On the other hand, as a storage medium for digital data, a so-called CD-ROM is used to record/play back computer data, etc., using a compact disk in the area of magnetic memory, which has conventionally been used as a large-capacity memory. It's starting to look like this. This CD-ROM can record computer data, still images, graphics, etc. in the audio signal area while maintaining system compatibility with audio compact discs, and has a recordable capacity of 540 MB, making it compatible with audio compact discs. Similarly, it is used for mass reproduction and distribution.

[0004] As mentioned above, these conventional compact discs include audio compact discs and CD-ROMs used for electronic publishing, etc., but these are all read-only ROMs (read-on-memory). ) type, in which the manufacturer of the compact disc records information on the disc in advance. In order to play back compact discs, many decoder playback devices are available from various manufacturers, but these devices are playback-only devices and do not have any writing circuitry.

Incidentally, a write-once optical disc that satisfies the compact disc standard has recently been proposed, and the so-called Orange Book standard, which establishes a format for recording and reproducing on this write-once disc, has also been proposed.

[0006]

As mentioned above, in the past, recording on compact discs was carried out by compact disc manufacturers, and the recording equipment was large-sized and used only for recording.

Furthermore, as mentioned above, conventional compact disc decoders and playback equipment are for playback only, and it is difficult to incorporate a recording device used by compact disc manufacturers into playback equipment.

Furthermore, in a normal CD system, the user prepares all data including margin bits in advance before manufacturing the disc, and writes the data by converting it into laser pulses. However, CD-WO
In write-once optical disk systems such as 1.0, the only thing the user has to prepare is the data, and the margin bits etc. need to be prepared by the system. Moreover, when writing in real time, DSV (Digital Sum) is used to suppress the generation of low frequency components for each pattern bit as much as possible.
This task must be done as fast as possible since it is necessary to calculate the value (Value). For this reason,
It is necessary to convert all the data for creating margin bits into ROM and hold it in an integrated circuit, and to optimize the combinational circuit and build a circuit for high-speed processing. An object of the present invention is to provide a circuit compliant with the so-called Orange Book for recording and reproducing data on a write-once compact disc, and to facilitate the manufacture of a recording/playback device for a write-once compact disc.

[0009]

[Means for Solving the Problems] A first aspect of the present invention is a signal processing circuit for writing data to a write-once optical disc, the storage means storing data to be written to the optical disc, and the storage means described above. non-volatile storage means storing predetermined parameter values corresponding to the data read from the
Non-volatile storage means that stores usable patterns based on this parameter value, means for calculating the digital total value, and pattern priority based on the digital total value in data units and the calculation result of the above calculation circuit. A priority calculation means for calculating a priority, and means for selecting a unique pattern to be output from outputs from a storage means storing the patterns based on the output of the priority calculation means.

A second aspect of the present invention is a signal processing circuit for adding margin bits to data to be written to a write-once optical disc, the circuit comprising: a storage means storing data to be written to the optical disc; Non-volatile memory that stores the length of the same value at the end of the data minus 1, the length of the same value at the beginning of the data, and the digital total value in data units, corresponding to the read data. means, a non-volatile storage means for storing usable patterns based on the length of the equivalence at the end of this data minus one and the length of the equivalence at the beginning of the data; calculating a digital total sum; means, a priority calculation means for calculating the priority of the pattern based on the digital total value in data units and the calculation result of the calculation circuit; and a storage means storing the pattern based on the output of the priority calculation means. means for selecting a unique pattern to be output from the output.

[0011]

[Operation] As described above, when adding margin bits, calculations are made in advance for all cases based on rules, and the results are stored in a non-volatile storage means, so that calculations can be performed at high speed. This allows writing on the write-once optical disc to be performed at high speed.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a signal processing semiconductor integrated circuit according to the present invention.

In FIG. 1, reference numeral 1 denotes a signal processing semiconductor integrated circuit according to the present invention. Data read out from the write-once optical disc 2 by the pickup 3 is input to the integrated circuit 1 from the RF circuit 4. In addition, integrated circuit 1
From there, an external static random access memory (hereinafter abbreviated as RAM) with a capacity of 64 Kbits8
The write data stored in is outputted to the RF circuit 4 in order to be written on the optical disc 2.

Reference numeral 20 denotes an EFM demodulation circuit, which converts the 14-bit EFM (Eight
to Fourteen Modulation
) The modulated EFM signal is demodulated into 8-bit data according to the conversion table and sent to the data bus 10. The data sent to the data bus 10 is transmitted to the reference clock circuit 9
The data is written into the RAM 8 designated by the address generated from the address generation circuit 95 based on 0.

25 is an EFM modulation circuit which modulates the 8-bit data read from the RAM 8 into 14-bit EFM data in order to reduce DC components, and also adds margin bits to make the data into 17-bit data. , sends data to the RF circuit 4. The data read from the RAM 8 is transferred from the data bus 10 to the EFM modulation circuit 25.
sent to. Data from the RAM 8 addressed by the address generated by the address generation circuit 95 is sent to the data bus 10 .

30 is an ATIP demodulation circuit;
The decosurator 5 demodulates the ATIP signal read from the pregroove created on the optical disc 2.

A CLV control circuit 40 outputs a signal for controlling the rotation of the optical disk to the servo circuit 7 based on the EFM signal from the EFM demodulation circuit 20 and/or the ATIP signal from the ATIP decosulator 5. The CLV control circuit of this embodiment also receives the FG output from the motor 6, and further outputs a rotation control signal based on this output.

Reference numeral 50 denotes a subcode generation and arithmetic circuit, which extracts a subcode from the EFM signal, performs a CRC operation on the subcode, and performs a CRC operation on data to be written to the optical disk to generate a subcode. This subcode generation and calculation circuit 50 includes a register 51 that receives the EFM signal from the EFM demodulation circuit 20 and extracts a CRC signal, a CRC calculation circuit 52, a readout register 53,
Write register 54, automatic addition/subtraction circuit 55, EFM
It includes a register 56 and an internal bus 57 for sending data to the modulation circuit 25.

70 is a CIRC modulation and demodulation circuit, and the E data read out from the RAM 8 via the data bus 10 is
Errors in the CIRC (Cross Interleaved Reed-Solomon) signal are detected and corrected from the FM demodulated signal, and the data is written into the RAM 8 again. Further CIRC
The modulation and demodulation circuit 70 connects the RAM 8 to the data bus 10.
A CIRC error correction code is added to the data to be written on the optical disc 2 that has been read out via the
Write to M8.

80 is an interface circuit, and RA
The audio or data read from the M8 via the data bus 10 is output, and the data into which the audio or data is input is written into the RAM 8.

Reference numeral 85 denotes a system controller interface circuit, which interfaces with the data bus of the system controller processor.

Next, each of the above-mentioned circuits will be further explained.

(1) EFM demodulation circuit 20 (FIGS. 2 and 3)
(See) The EFM demodulation circuit 20 includes an EFM signal input section and an EFM data extraction section. Figure 2 shows the EFM signal input section, and Figure 3 shows the EFM signal input section.
indicates an EFM data extraction section.

A 14-bit EFM modulated EFM signal read from the optical disc 2 is input to the SYNC pattern extraction circuit 22. Then, the external PLL circuit 15
A PLL is configured by the bit clock reproducing circuit 21 and the phase comparator circuit 211, and the 8 MHz VCO signal is outputted by the bit clock reproducing circuit 21 as a 4 MHz bit clock signal (PLCK). This PLCK is SY
It is applied as a timing signal to the NC extraction circuit 22, and the EFM signals H11, L11, and H2 are extracted from this circuit 21. This circuit is also equipped with a protection interpolation circuit 23,
The clock signal from this circuit 23 and the SYNC extraction circuit 2
2 is input to an OR circuit 24, and a synchronization signal (VSYNC) is output from this OR circuit 24. EFM signal data is input to the EFM conversion table circuit 212, and VSYNC and PLCK are respectively applied as a reference timing signal and a timing signal. This conversion table circuit 212 removes the margin bits and demodulates the data from 14 bits to 8 bits according to the conversion table. This data is data bus 10
and is written into the RAM 8 addressed by the address generated from the address generation circuit 95 based on the reference clock circuit 90.

(2) EFM modulation circuit 25 (see FIGS. 4 to 9) The EFM modulation circuit 25 includes an EFM output section and an EFM conversion section. FIG. 4 shows the EFM output section, and FIG. 5 shows the EFM conversion section.

The 8-bit data read from the RAM 8 and the 8-bit data from the subcode generation and arithmetic circuit 50 are input to the selector 261. In order to reduce the subcode DC component, the data is modulated into 14-bit EFM data, and margin bits are added to make the data into 17-bit data, and the data is sent to the RF circuit 4.

By the way, the CD system uses the EFM conversion method to record data on the optical disc 2. This avoids a situation where there are no pits on the optical disc 2 even if the data is all "0", for example. In other words, as shown in FIG. 7, 8-bit hexadecimal data is converted into a predetermined 14-bit length pattern, and 3-bit margin bits are added to this to create 1 byte recorded on the optical disc 2. The data consists of: In this EFM, the H/L state of the pattern is irrelevant, and only the length of the peak or valley is significant.

Furthermore, in this EFM conversion method, "3T,
11T rule.This rule states that the length of a peak or valley must be from 3 times the unit length to 11 times the unit length, and that a peak or valley with a length of 2T or less and a peak or valley with a length of 12T or more must be formed. Formation of valleys is prohibited, including margin bits.For this reason, the margin bits sandwiched between two pieces of data are naturally limited in their possible patterns.

[0030] Possible patterns of margin bits are shown in Fig. 8.
As shown. FIG. 8(A) shows the case when the last data pattern of the immediately preceding data pattern is "0", and FIG. 8(B) shows the case when the last data pattern of the immediately preceding data pattern contains "1".

In addition, in EFM conversion, DSV (Digital
Sum Value) is introduced, and restrictions are also imposed by this. DSV aims to balance the length of the peaks at as short intervals as possible, and is calculated at any time for each pattern bit, and by adjusting the margin bits, the value is brought as close to "0" as possible. This is what we are trying to do.

In a normal CD system, the user prepares all data including margin bits in advance before manufacturing the disc, and writes the data by converting it into laser pulses. However, in a write-once optical disc system such as CD-WO, the only thing the user has to prepare is the data, and margin bits and the like need to be prepared by the system. Furthermore, when writing in real time, it is necessary to calculate the DSV for each pattern bit, so this work must be performed as fast as possible.

For this reason, it is necessary to convert all data for creating margin bits into ROM and hold it in an integrated circuit, and to optimize the combinational circuit to construct a circuit for high-speed processing. EFM modulation circuit 25 in this embodiment
is constructed to satisfy the above requirements.

The EFM modulation circuit 25 in this embodiment will be further explained below.

Data read from RAM 8 is sent from data bus 10 to EFM modulation circuit 25. The selector 261 selects data or subcode data from the RAM 8 and outputs it to the EFM conversion circuit 262. The EFM conversion circuit 262 converts the 8-bit data into a 14-bit EFM signal according to the conversion table, and outputs the signal to the selector 263. 14-bit data for adding S0 and S1 is input to the selector 263. The selector 263 selects the EFM signal or S1, S based on the control signal from the system controller.
One of the O signals is sent to the margin bit adding circuit 264. The margin bit addition circuit 264 adds margin bits to the 14-bit data and outputs a 17-bit signal. This margin bit addition circuit 264 is composed of a ROM or a logic array that stores J, K, and V values corresponding to each data. Furthermore, this circuit 264 has J,
Construct a ROM or logic array that indicates usable patterns based on the K value. This circuit 264 includes a circuit for calculating DSV, a circuit for indicating the priority order of patterns based on the V value and DSV, and further selecting a unique pattern to be output.

FIG. 6 is a circuit diagram showing a specific embodiment of the EFM conversion circuit 262 and margin bit addition circuit 264 described above.

In FIG. 6, the ROM 270 stores J, K, and V values corresponding to each data and a conversion table for converting the hexadecimal 8-bit data into an EFM signal corresponding to the data.

Here, J stored in the ROM 270
The value is the length of the same value at the end of the data minus 1, the K value is the length of the same value at the beginning of the data, and the V value is a value indicating the DSV in data units.

However, as shown in FIG. 9, V is the data D
It does not directly indicate SV, but DSV varies from -8 to -
This number is assigned so that it can be easily stored in the ROM 270 by taking advantage of the fact that it takes only nine values: 6, -4, -2, 0, 2, 4, 6, and 8.

As mentioned above, the following two rules are imposed on the creation of margin bits.

(i) 3T, 11 rule (ii) Minimum value of DSV for suppressing low frequency components (close to 0)

[0042] This circuit is constructed so as to satisfy this rule.

The J value output from the ROM 270 is delayed by a delay 271. Then, the delayed J value of the previous data and the K value output from the ROM 270 are given to the possible pattern selection circuit 273. This possible pattern selection circuit 273 limits the selectable patterns according to the above rule (i), and transfers this data to the determination circuit 27.
Supply to 5.

Next, the V value output from the ROM 270 is supplied to a priority calculation circuit 274 and a DSV calculation circuit 274. The priority calculation circuit 274 follows the above rule (ii
), the data is prioritized according to the DSV minimum condition, and this data is supplied to the decision circuit 275. The decision circuit 275 selects the only margin bit pattern based on the best margin bit pattern at that time and the prioritized data, and outputs it to the selector 276. The selector 276 is supplied with the EFM pattern from the ROM 270, and the selector 276 adds a margin bit pattern after the EFM pattern to perform EFM output.

[0045] Also, for DSV calculation, the DSV calculation circuit 2
Each pattern is fed back to 72.

In this way, by configuring the EFM conversion circuit including a circuit for adding margin bits, calculations are made in advance for all cases based on rules when adding margin bits, and the results are stored in the chip in the ROM 270. By holding it in place, calculations can be performed at high speed. This allows writing on the write-once optical disc to be performed at high speed.

[0047] In the above embodiment, the memory is constructed from a ROM, but it may also be constructed from a circuit such as a logic array.

Next, the data to which margin bits have been added by the margin bit adding circuit 264 is output to the SYNC adding circuit 265. In this circuit, 7 bits of data are added and output only in the case of the SYNC signal.

The 17-bit or 23-bit (SYNC only) EFM data is sent to the selector circuit 251, pulse strategy circuit 252, and (n-1) strategy circuit 254.
will be sent to each. The pulse strategy circuit 252 converts the signal into A, B, and C according to Blue Book, and outputs it to the selector 251. (n-1) Strategy circuit 254
Then, n-1 processing is performed and the result is sent to the selector 251. The selector 251 is further supplied with outputs from a test pattern circuit 253 for testing the standard and a synchronization pulse generation circuit 255 for destroying data by writing twice to data that has been written once. The selector 251 selects and outputs one signal from the above-mentioned signals based on a control signal from the system controller. This data is output to the RF circuit 4, and the data is written from the pickup 3 onto the optical disc.

(3) ATIP demodulation circuit 30 (see FIGS. 10 to 24) The ATIP demodulation circuit 30 includes an ATIP input section and an ATIP signal processing section. Figure 10 shows the ATIP input section and Figure 11 shows the A
The TIP signal processing section is shown.

[0051] Write-once optical discs such as CD-WO have E
Before the FM pit is formed, an ATIP pregroove is formed so that its position information can be extracted. As shown in FIG. 12, this ATIP pregroove stores 42 bits of data in biphase format. Bi-phase format is a digital notation that expresses data as ``1'' when the data changes between high and low in a certain unit time length, and as ``0'' when there is no data. .

The structure of ATIP data is shown in FIG. 13, as shown in FIG.
It consists of a total of 42 bits, including time information of CD), seconds (BCD), frames (BCD), and 14-bit CRC data for the time information data.

Among these, the synchronization pattern is expressed by breaking the biphase format, and serves as a delimiter between each data. There are two types of synchronization patterns as shown in FIG. This depends on whether the previous signal was High or Low.

FIG. 15 shows an example of an actual waveform.

By the way, this bi-phase digital signal is input to the IC. And this ATIP
The demodulation circuit 30 detects a clock and synchronization pattern for data extraction, and detects data from this one input. The data extraction clock is used for data acquisition timing and CLV servo control.

First, the basic configuration of the ATIP demodulation circuit 30 will be explained with reference to FIGS. 10 and 11.

[0057] The AT read out from the pregroove created on the optical disk 2 by the ATIP decosurator 5
The IP signal is input to the C3150, C6300 extraction circuit 31, and this circuit 31 selects the C3 as the basic timing.
150 is output to the OR circuit 33. The output from the protection interpolation circuit 32 is input to the OR circuit 33, and C3150 is output from the OR circuit 33. This C3150 is S
It is given to the YNC pattern extraction circuit 34 as a capture timing signal. ATIP data is input to the SYNC extraction pattern circuit 34, and a bit clock is output from this circuit 34 to an OR circuit 36. The output from the protection interpolation circuit 35 is input to the OR circuit 36, and a timing signal (ASYNC) is output from the OR circuit 36.

Further, the ATIP data is input to the ATIP data extraction circuit 37. ASYNC is given to this circuit 37 as basic timing. The output from the ATIP extraction circuit 37 is given to the register 38 and the CRC calculation circuit 39 as 8-bit data. 8-bit data is sent from the register 38 to the CPU, and is also sent to the CR.
The result of error detection is sent from the C calculation circuit 39 to the CPU.

Further, this circuit will be further explained with reference to FIGS. 12 to 24.

The synchronization pattern is a 75Hz ATIP frame synchronization timing, and each data is ATIP frame synchronization timing.
It is sent to the CPU (system controller) as time information. Also,
A CRC calculation is performed using the ATIP time information and CRC data, and the result is also sent to the CPU (system controller).

First, a clock is extracted. As shown in FIG. 16, two types of clocks, C3150 and C6300, are extracted from the ATIP input.

The desired signal C3150 is a delimiter between each data. C6300 is obtained in the process of extracting this C3150. A desired signal C3150 is obtained by extracting an edge from the input ATIP waveform pattern, removing some signals from it, and adding some signals.

Extracting the edges of the ATIP input signal is shown in Figure 1.
A circuit as shown in 7 is used. Here, a D flip-flop (DFF) 311 using a basic clock (4 MHz system clock in the embodiment) and an exclusive OR circuit 312 are used.

As shown in FIGS. 17 and 18, DFF3
The input signal A is taken into the DFF 11 at the timing of the reference clock CK, and the DFF 311 outputs a signal B obtained by delaying the input signal A.

Then, the exclusive OR circuit 312 outputs B
and the input signal are given, and an output signal C is output.

The ATIP input edge extraction signal (DET) input from the outside basically becomes C3150. Among these, to remove the DET you want to remove, window A,
Provide B. Perform interpolation to create the INS you want to add. Furthermore, the DET signal is a signal extracted from the optical disk 2 rotated by a motor, and the interval between them varies depending on the rotational speed of the motor, and also fluctuates due to rotational unevenness and the like.

For this reason, as shown in FIG. 19, a reference counter 319, a register 321, a window A counter 318, and a register 320 are provided.

Of the DETs, that which falls within the window B from the reference counter 319 is defined as DETB. What is in window A from window A counter 318 is assumed to be DETA. These become C3150 signals as they are. The C3150 signal is a 3.15 KHz periodic pulse and indicates the length of each ATIP data. C63
The 00 signal is a 6.30 KHz periodic pulse. If the optical disk 2 is rotating correctly, each DET interval is 137.
This is equivalent to 2 clocks. 4.3218 between 3.15KHz
MHz counts the number of clocks. (See Figure 20)

The INS signal is added when there is no DET within the synchronization pattern, or when no DET is found due to abnormal disk rotation or data loss due to scratches on the disk surface.

[0070] The INS signal sends a new C
3150 is generated. For this reason, the reference register 321,
The previous value is stored in the window A register 320. The previous value and the current value output from the reference counter 319 are compared by the comparator 323, and when they agree, the I
Issue NS.

If DETB occurs, each counter 318, 319 is cleared before INS occurs, so there is no INS this time. In the case of DETA, this occurs after INS occurs, so INS is erased and DETA is utilized. Therefore, it has a width of 16 bits. This is because the delay value cannot be increased.

However, the timing of taking in the window A register 320 has a range up to 254, and the DET generated during this period does not become DETA, but is used for the next comparison.

In this way, C3150 and C6300 are generated. Change (CHANGE) and Window (Wi
ndow) will be described later.

C6300, C3 obtained by the above method
150 to return the biphase format of the ATIP input data to the normal format as shown in FIGS. 21 and 22.

As shown in FIG. 22, the ATIP input is input to the shift register 351, and the shift register 35
The output Q1 clocked at 1 by the C6300 and the output Q2 clocked by the next C6300 are exclusive ORed by the exclusive OR circuit 352 to generate the ATSD signal. Output ATSD from this exclusive OR circuit 352
is taken into the serial/parallel register 353 at C3150 timing. This imported value is a normal value. Pattern matching is performed separately for the SYNC pattern.

In the method described above, there are two possible ways to take C3150, as shown in FIG. At some point C31
After recognizing 50, C3 from the outside at the next appropriate point.
If there is no 150 (edge of ATIP signal), interpolate,
C3150 at an unnecessary point (edge of ATIP signal)
Since the method is to ignore the C3150, once either the A series or the B series is selected as the C3150, it cannot be changed.

[0077] The ATSD import timing at this time is shown in Figure 2.
As shown in 4, there are two types: a(Δ) and b(*).

At this time, the correct series is the A series a(Δ). In order to correctly return this to A system when it was B system,
Use captured data. As shown in Figure 24, the captured data (
Since all the values of b) are "1", the number of "1"s is counted, and if it is clearly large, this is regarded as the B series, and the C3150 series is taken again. A.T.
Among the data in the IP, ATIME indicates minutes and seconds frames in BCD display, and its maximum value is 99 minutes 59 seconds 7
In 5 frames, “1001100101011001
01110101" (binary representation), and this processing is possible because the MSB of the byte of seconds and frames is always "0".

[0079] At this time, if the number of data to be captured is greater than or equal to a certain number, "1"
19 and 20, the C3150 (ATI) found in the window (WINDOW)-C
P input edge) to start a new C3150 series. (See Figures 7 and 8)

(4) CLV control circuit 40 (see FIGS. 25 and 26) FIG. 25 shows the overall configuration of the CLV control circuit 40. first,
The basic configuration of the CLV control circuit 40 will be explained with reference to FIG. 25.

The EFM frame timing and ATIP timing signals from the EFM demodulation circuit 20 are input to the counter 42 via the parallel-serial conversion circuit 41. The EFM frame timing and ATIP timing signals are also output to selector 48. The signal subjected to speed differential control by the counter 42 is output to the selector 43. The FG output from the motor 6 is applied to an FG counter 46, and the output of this counter 46 is applied to the selector 43. Then, the EFM reference value fixed output is sent to the reference number setting circuit 47.
An ATIP reference value fixed output and an FG reference value are provided, respectively, and the output of this circuit 47 is provided to a subtracter 44. The output of the selector 43 is given to the subtracter 44 . The subtracter 44 outputs an optical disk rotation control signal (MDS) to the servo circuit 7 via the register 45. Further, the selector 48 outputs a phase difference control signal to an up/down counter 49, and this counter 49 outputs a phase control signal (MDP).

In this circuit, this measure is performed every EFM frame. That is, during a certain EFM frame, M
The DS signal is set to L or H. FIG. 26 illustrates a portion related to the EFM pattern servo that prompts the MDS output (spindle motor control signal). Further explanation will be given below with reference to this figure.

As mentioned above, in the EFM conversion method, there is a "3T-11T rule" which states that the length of the peaks or valleys of the EFM pattern must be between 3 and 11 times the unit length.

[0084] If data can be read normally from the EFM pit of optical disc 2, the disc must have been created correctly, so according to the 3T-11T rule, the shortest length is 3T and the longest length is 11T. be. Here, if there are peaks or valleys of 2T or less or peaks or valleys of 12T or more, it is assumed that this is not a loss of information due to scratches on the disk, etc., and if the disk rotates quickly,
This will happen if it is too late.

As a method for roughly adjusting the rotation of the disk using this relationship, as shown in FIG.
The peaks or valleys of the EFM pattern input to the D flip-flop 451 are detected by the exclusive OR circuit 452, and the length is counted by the counter 453 using the 4MHz clock of the reference clock (X'tal), and the length is 12T or more. , 2T
If the following is found, it is output to the register 454 and the rotation of the spindle motor is adjusted as follows.

[0086]

[Table 1]

According to this CLV circuit 30, the circuit that applies servo according to the EFM pit on the disk during reading and the circuit that applies servo according to the pregroove on the disk during writing are performed by the same circuit.

(5) Subcode generation and calculation circuit 50
(See Figure 27)

This sub-code generation and arithmetic circuit 50 receives the EFM signal from the EFM demodulation circuit 20 and performs CR
The C signal is input to a register 51 for extracting the C signal, and the extracted signal is output from the register 51 to an OR circuit 63. The OR circuit 63 is given the output from the protection interpolation circuit 62,
The VSSYNC signal is sent from this OR circuit 63 to the register 64.
It is given as a capture timing signal. EFM data is input to the register 64, and Q
The output is given to a serial-parallel conversion circuit 65. This circuit 65 sends 8-bit data to the CRC calculation circuit 52 and the read register 53, respectively. The CRC calculation circuit 52 outputs the CRC result to the CPU. Also, read data from the register 53 is output to the CPU.

Q to the write register 54 from the CPU.
Sub data is given, and data is sent from this register 54 to automatic addition/subtraction circuit 55 and registers 60 and 61. The automatic addition/subtraction circuit 55 and the register 60 perform automatic addition/subtraction of the time information of the Q subcode and provide the resulting value to the selector 59. The data of the register 61 is also applied to the selector 59, and the signal is selected by the selector 59 and output to the CRC calculation circuit 52 and the selector 58. The CRC calculation circuit 52 performs a CRC calculation on the input purchase data and outputs the data to the selector 58. Then, the data is sent from the selector 58 to the parallel-serial conversion circuit 57, the serially converted Q data is sent to the register 56, and the subcode data is output from the register 56.

(6) CIRC modulation and demodulation circuit 70 (
(See FIG. 28) From the CIRC modem circuit 70, the EFM demodulated signal read out from the RAM 8 via the data bus 10 is
Detects and corrects errors in the IRC signal, and then re-releases the data.
Write to AM8. Furthermore, CIRC modulation and demodulation circuit 7
0 adds a CIRC error correction code to the data read from the RAM 8 via the data bus 10 and written to the optical disk 2, and writes the data to the RAM 8 again.

(7) Interface circuit 80 (FIG. 29)
(See) Data from the RAM 8 is given to a register 81 and an interpolation circuit 82, and the register 81 gives 16-bit data to the interpolation circuit 82. The interpolation circuit 82 holds the pre-tooth value, interpolates the average value, and provides the interpolated data to the selector 83. The output from the register 81 is given to the selector 83, and the CD-DA data is output from the selector 83. Further, the register 81 outputs data for CD-ROM.

Furthermore, the data of the CD-ROM and CD-DA are supplied to AND circuits 86 and 87, respectively, and the pre-encoded data is supplied to the AND circuits 86 and 87.
8. Data is sent from the AND circuits 86 and 87 to the selector 85, and the data is written into the RAM 8 from the selector 85 via the register 84.

[0094]

[Effects of the Invention] As explained above, according to the present invention, when adding margin bits, calculations are made in advance for all cases based on rules, and the results are stored in a non-volatile storage means, so that calculations can be performed. Can be done at high speed. Therefore, writing on the write-once optical disc can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a block diagram showing a signal input section of the EFM demodulation circuit of the present invention.

FIG. 3 is a block diagram showing a data extraction section of the EFM demodulation circuit of the present invention.

FIG. 4 is a block diagram showing a signal input section of the EFM modulation circuit of the present invention.

FIG. 5 is a block diagram showing a signal conversion section of the EFM modulation circuit of the present invention.

FIG. 6 is a block diagram showing a specific embodiment of an EFM conversion circuit and a margin bit addition circuit of the EFM modulation circuit of the present invention.

FIG. 7 is a schematic diagram showing a data structure of an EFM modulation method.

FIG. 8 is a schematic diagram showing the data structure of margin bits in the EFM modulation method.

FIG. 9 is a schematic diagram showing a data structure of an EFM modulation method.

FIG. 10 is a block diagram showing the input section of the ATIP demodulation circuit of the present invention.

FIG. 11 is a block diagram showing an ATIP signal processing section of the present invention.

FIG. 12 is a schematic diagram showing the data structure of an ATIP pregroup signal.

FIG. 13 is a schematic diagram showing the data structure of an ATIP signal.

FIG. 14 is a schematic diagram showing the configuration of a synchronization pattern.

FIG. 15 is a schematic diagram showing an example of the data waveform of an actual ATIP signal.

FIG. 16 is a waveform diagram showing the relationship between the ATIP signal and the data extraction signal.

FIG. 17 is a circuit diagram showing an example of an ATIP signal edge detection circuit.

FIG. 18 is a waveform diagram showing each output signal of the ATIP signal edge detection circuit.

FIG. 19 is a block diagram showing a data processing circuit for ATIP signals.

FIG. 20 is a waveform diagram showing the relationship between output signals in data processing of the ATIP signal.

FIG. 21 is a waveform diagram showing the relationship between output signals in data processing of an ATIP signal.

FIG. 11 is a block diagram showing an example of an ATIP signal processing section of the present invention.

FIG. 23 is a waveform diagram showing the relationship between output signals in data processing of the ATIP signal.

FIG. 24 is a waveform diagram showing the relationship between output signals in data processing of the ATIP signal.

FIG. 25 is a block diagram showing a CLV control circuit of the present invention.

FIG. 26 shows the EFM of the CLV control circuit of the present invention.
FIG. 3 is a block diagram showing a pattern control part.

FIG. 27 is a block diagram showing a subcode generation and arithmetic circuit according to the present invention.

FIG. 28 is a block diagram showing a CIRC modulation and demodulation circuit of the present invention.

FIG. 29 is a block diagram showing an interface circuit of the present invention.

[Explanation of symbols]

20 EFM demodulation circuit 25 EFM modulation circuit 30 ATIP demodulation circuit 40 CLV control circuit 50 Subcode generation and calculation circuit 70 CIR
C modulation and demodulation circuit 80 interface circuit

Claims (2)

[Claims] 1. A signal processing circuit for writing data to a write-once optical disk, comprising: a storage means storing data to be written on the optical disk; and predetermined parameter values corresponding to data read from the storage means. a non-volatile storage means that stores patterns that can be used based on the parameter values; a means that calculates the digital total value; a digital total value in data units and the calculation result of the above calculation circuit; A postscript comprising priority calculation means for calculating the priority of the pattern based on the priority calculation means, and means for selecting the only pattern to be output from the output from the storage means storing the above-mentioned patterns based on the output of the priority calculation means. signal processing circuit for optical discs. 2. A signal processing circuit for adding margin bits to data to be written on a write-once optical disk, the storage means storing data to be written on the optical disk;
Corresponding to the data read from the storage means, store the value obtained by subtracting 1 from the length of the same value at the end of the data, the length of the same value at the beginning of the data, and the digital total value in data units. a non-volatile storage means that stores usable patterns based on the length of the equivalent value at the end of this data minus 1 and the length of the equivalent value at the beginning of the data; a digital total; a priority calculation means for calculating the priority of the pattern based on the digital total value in data units and the calculation result of the calculation circuit; and a priority calculation means for storing the pattern based on the output of the priority calculation means. A signal processing circuit for a write-once optical disc, comprising means for selecting a unique pattern to be output from outputs from a storage means.