JPH04242454A - Coincidence processing system for cache memory - Google Patents

Abstract

PURPOSE:To suppress the deterioration of performance of a processor for a data processor consisting of a multi-hierarchical cache memory by sending the information to a low order cache memory set closer to the processor for invalidation only when a high order cache memory has a hit. CONSTITUTION:A cache memory of a processor 6 consists of a built-in cache memory 4 of a 1-chip microprocessor 3 and an external cache memory 2 in a double hierarchical structure. When the information is written into a main storage 8, this information is transferred to the processor 3 via a control line 21 and an address line 22. When the coincidence of addresses is secured in the memory 2, the main storage write address information is put on both lines 21 and 22 and a date line 23 based on a start rule. Based on this information, the memory 4 checks whether the corresponding main storage data is stored in itself or not. If so, the stored data is invalidated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory matching processing method, and more particularly to a cache memory matching processing method in a data processing device in which processing devices sharing a main memory employ a multi-layered cache memory.

0002

2. Description of the Related Art In a data processing device in which processing devices share a main memory device, when part of the contents of the main memory is temporarily stored in a cache memory, the contents of the corresponding address on the main memory are shared with other processing devices. If the cache memory is replaced by the cache memory, a mismatch occurs with the contents of the cache memory, causing the system to malfunction.

[0003] In order to avoid this, cache matching processing, such as invalidating a corresponding portion (or the entire cache memory) of the cache memory, has been conventionally performed.

By the way, with recent advances in LSI technology, there are more and more microprocessors constructed from a single LSI chip with a built-in cache memory, but since a large capacity cache memory cannot be built into the chip, Each processing device may have a two-layer configuration in which a small-capacity cache memory is placed within the chip, and a large-capacity cache memory is placed outside the chip (inside the processing device) to improve performance.

In this case, when a main memory is referenced from the execution section of the microprocessor, the built-in cache memory is first referenced, and when there is no hit, the external cache memory is referenced. Only when this also does not result in a hit, a reference is made to the main memory via the system bus.

[0006] In cache matching processing in such a multi-layered cache memory, since the system bus is not directly connected to the microprocessor, it is not possible to know the main memory write address by other processing devices. Therefore, the following method has conventionally been used.

1. The small cache memory in the chip is completely invalidated without address selection. Generally, invalidation is not performed every time some writing is performed by another processing device, but only at the timing of task switching given by software.

2. System bus address information is introduced into the microprocessor from a dedicated input terminal of the microprocessor to invalidate the cache.

3. The presence or absence of information in the built-in cache memory is also stored in the external cache memory, and when another processing device writes to the main memory, the microprocessor and the external cache are sent only if the contents at that address are in the built-in cache memory. Send the address through the bus line between memories,
Invalidates the relevant portion of the built-in cache memory.

0010

[Problem to be Solved by the Invention] Among the conventional cache memory matching processing methods described above, the first method is as follows:
Since the invalidation frequency is not low, the cache hit rate decreases and the processor performance does not improve.

[0011] In the second method, although there is less concern about deterioration of processor performance, it is necessary to have a large number of extra input terminals, which is disadvantageous in terms of chip structure (size, reliability, etc.). The third method has the least performance degradation, but has the problem that it requires an address mapping/replacement algorithm and address information for the built-in cache memory in the external cache memory, which increases the amount of hardware.

0012

[Means for Solving the Problems] The system of the present invention provides a cache memory matching processing method in a data processing device in which each of the processing devices sharing the main storage device adopts a multi-layered cache memory configuration. When the upper cache memory connected by the bus erases old data in order to import main memory data, it supplies the address information to the lower cache memory closer to the processor to invalidate the old data, and When the main memory data rewritten by the processing device is held, the address information and data are controlled to be supplied to the lower cache memory and invalidated.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a data processing apparatus for explaining one embodiment of the present invention.

The cache memory of the processing device 6 includes a built-in cache memory 4 in the one-chip microprocessor 3;
It is composed of two layers of external cache memory 2.

External cache memory 2 is connected to system bus 1
The system monitors the movement of the system bus 1 through the control line 11 and the address line 12, and when another processing device 7 writes to the main storage device 8 through the system bus 1, the fact is transmitted through the control line 11. The address information is acquired through the address line 12, and it is checked whether the external cache memory 2 holds the information at the address. If it is retained, its contents are invalidated, but such a technique is a basic function of the external cache memory 2, and its mechanism is a known technique.

[0017] It is confirmed through the control line 21 and address line 22 between the external cache memory 2 and the one-chip processor 3 that the main memory 8 has been written and that the address is 1.
Notify chip processor 3. 1 chip processor 3
When viewed from above, the control line 21, address line 22, and data line 23 are directly connected to the system bus 1, and when main memory writing is performed by another processing device 7 connected to the system bus 1. Looks similar.

When an address match is found in the external cache 2, main memory write address information is placed on the control line 21 and address line 22 in accordance with the activation rules for the control line 21, address line 22, and data line 23. become.

Based on the above information, the built-in cache memory 4 checks whether the main memory data exists in its own cache, and if so, invalidates it.

This system operates correctly only when the rule holds that whenever main memory information exists in the built-in cache memory 4, it also exists in the external cache memory 2. To achieve this, external cache memory 2
also performs the following actions:

In other words, in order to enable new main memory data to be taken into the external cache memory 2 when a cache miss occurs, when other old data is erased, the old data (main memory data) is The address information (above) is placed on the control line 21 and address line 22 as cache invalidation information to instruct invalidation of the information that is (or may be) in the built-in cache memory 4.

In this embodiment, the notification of the main memory write address from the external cache memory 2 to the one-chip processor 3 is as follows:
1-chip processor 3 main memory/cache access path (control line 21, address line 22 and data line 23)
), but it can also be provided from a dedicated terminal as in the prior art described above. In a processor in which access to the built-in cache memory 4 by the processor execution unit 5 is inhibited when performing main memory write address verification for matching processing, giving an address from a dedicated terminal has no effect on suppressing performance degradation of the processor. be.

[0023]

[Effects of the Invention] As explained above, the present invention requires almost no increase in the amount of new hardware. On the other hand, compared to a method that checks the consistency of the built-in cache memory each time a main memory write is performed, this method sends addresses to the built-in cache memory much less frequently, and the frequency of accessing the external cache memory from a single-chip processor is much smaller. There is almost no interference or deterioration of processor performance.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data processing device for explaining one embodiment of the present invention.

[Explanation of symbols]

1 System bus 2 External cache memory 3 1 chip processor 4 Built-in cache memory 5 Processor execution unit 6,7 Processing equipment 8 Main memory 11, 21, 41 Control line 12, 22, 42 Address line 13, 23, 43 Data line

Claims (1)

[Claims] Claim 1: In a cache memory matching processing method in a data processing device in which each of the processing devices sharing a main storage device adopts a multi-layered cache memory configuration, the upper cache memory connected to the main storage device by a system bus is , when old data is erased to import main memory data, the address information is supplied to the lower cache memory closer to the processor to invalidate the old data, and the main memory data rewritten by another processing device is If the address information and data are held, the cache memory matching processing method is characterized in that control is performed so that the address information and data are supplied to the lower cache memory and invalidated.