JPH04241630A - System for optimizing register allocation by graph painting - Google Patents

Abstract

PURPOSE:To prepare an object program having a high executive performance. CONSTITUTION:A data conflict analyzing means 41 discriminates the presence/ absence of an overlap and the possibility of damaging the parallelization of instructions caused by the allocation of the same register regarding 'sections where variables hold effective data' in an intermediate code string and calculates an evaluated value in accordance with the presence/absence of the overlap and the potentiality of possibility of damaging parallelization. A graph plotting means 42 plots a graph by connecting the nodes corresponding to the 'sections where variables hold effective data' with sides based on the analyzed results of the means 41 and adding evaluated values to the sides. A graph painting means 43 assigns the different colors of the number corresponding to the number of usable registers to the nodes connected by the sides. A register allocating means 44 allocates the same register to the variables corresponding to the nodes for which the same color is assigned.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an optimization method for a compiler that generates a target program from a given source program. Regarding an optimization method in a compiler for a processor that assumes that the program has been determined at the time of program generation, in particular, in order to efficiently allocate registers for intermediate code strings generated by expanding a source program in the process of generating the target program. This paper concerns a register allocation optimization method using graph coloring, which employs a graph coloring method.

0002

[Prior Art] A compiler for a processor that consists of a single arithmetic unit and assumes that the instructions executed by the arithmetic unit are fixed at the time of generation of the target program. A method using a graph coloring method is known as a method for allocating registers.

[0003] In this method, processing is performed in the following steps.

[0004] ■ The interval in which each variable holds valid data is represented as a node in the graph.

[0005] If it is impossible to allocate the same register to the two variables in question due to overlap between two intervals, the two corresponding nodes are connected by an edge of the graph.

[0006] Using the above method, we analyze overlap for all sections, and in the graph obtained as a result,
Assign colors so that nodes connected to each other by edges do not have the same color.

■ Allocate one register to a plurality of variables corresponding to a plurality of nodes to which the same color is assigned.

[0008] Among the above-mentioned methods, there is a method that further enhances the effect of register allocation by giving priority to nodes in advance. In this method,
The priority of a node is determined by the frequency with which the variable corresponding to that node is used in the source program, and when registers are allocated in step ① above, registers are allocated in order from the node with the highest priority. (In this way, "priority" in the prior art was given to nodes).

[0009] Even in a compiler for a processor that has multiple arithmetic units operating in parallel and assumes that the instructions to be executed in each arithmetic unit are determined at the time of generation of the target program, registers using conventional graph coloring are used. The allocation optimization method was realized by directly applying the method described above in a compiler for a processor consisting of a single arithmetic unit.

0010

[Problem to be Solved by the Invention] In the conventional register allocation optimization method using graph coloring in a compiler for a processor having multiple arithmetic units, the above-mentioned method for a compiler for a processor having a single arithmetic unit is applied as is. As long as there is no overlap between the two intervals, an edge connecting the nodes will not be created, so even if two variables are located close to each other in the source program, there will be no overlap between the two intervals corresponding to those variables. Otherwise, the same registers can be allocated.

By the way, in the parallelization processing of instructions in a compiler having a plurality of arithmetic units, an attempt is made to arrange instructions so that instructions located close to each other in a source program are executed in parallel as much as possible. At this time, if the same register is allocated to variables included in these instructions, the instructions using these variables cannot be executed in parallel.

Therefore, the above-described conventional register allocation optimization method using graph coloring has a problem in that the execution performance of the target program generated by the compiler to which the method is applied deteriorates.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a register allocation optimization method using graph coloring that can generate a target program with high execution performance.

[0014]

[Means for Solving the Problems] The register allocation optimization method using graph coloring of the present invention has a plurality of arithmetic units operating in parallel, and the instructions to be executed in each arithmetic unit are determined at the time of generation of the target program. In the process of generating a target program for a processor that assumes that the For the section that holds , determine whether there is any duplication and the possibility of impairing parallelization of instructions by allocating the same register, and calculate an evaluation value depending on the presence or absence of duplication and the high possibility of impairing parallelization. A graph is created by connecting the nodes corresponding to the "interval where the variable holds valid data" with edges and adding evaluation values to the edges based on the analysis by this data conflict analysis means. a graph coloring means that assigns different colors according to the number of available registers to nodes connected by edges by this graph creation means; and a graph coloring means that assigns the same color to nodes connected by edges by this graph coloring means and register allocation means for allocating the same register to the variable corresponding to the node.

[0015]

[Operation] In the register allocation optimization method using graph coloring of the present invention, the data conflict analysis means detects "sections in which variables hold valid data" in the intermediate code string.
The graph creation means calculates the evaluation value according to the existence of duplication and the possibility of impairing parallelization of instructions by allocating the same register. Based on the analysis by the conflict analysis means, a graph is created by connecting nodes corresponding to "intervals in which variables hold valid data" with edges and adding evaluation values to the edges, and the graph coloring means creates the graph. The means assigns a number of different colors corresponding to the number of available registers to the nodes connected by edges, and the register allocation means assigns the same register to variables corresponding to the nodes to which the same color is assigned by the graph coloring means. Assign.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of the register allocation optimization method using graph coloring according to the present invention. The register allocation optimization method using graph coloring of this embodiment uses a source program 1 stored in a secondary storage device (not shown), a compiler 2, and an object that is compiled and stored in the secondary storage device. This program includes Program 3.

The compiler 2 includes a source program interpreter 21 that takes in a source program 1 from a secondary storage device, performs syntactic analysis and semantic analysis, and develops the analysis results into an intermediate code string 5 (see FIG. 2); An optimization unit 22 that performs optimization processing for code shortening etc. on 5.
, a serial assembly instruction string generator 23 that generates a serial assembly instruction string in which all the instructions to be executed in each of the plurality of arithmetic units are arranged in a line; and a serial assembly instruction string generator 23 that parallelizes the serial assembly instruction string. a parallel assembly instruction string generation unit 24 that generates a parallel assembly instruction string that becomes the program 3;
The target program output unit 25 outputs the target program 3 to a secondary storage device.

The register allocation processing section 4 in the optimization section 22 includes a data conflict analysis means 41, a graph creation means 42, a graph coloring means 43, and a register allocation means 44. This register allocation processing section 4 realizes the core processing of the register allocation optimization method using graph coloring of this embodiment.

2 and 3 are diagrams for explaining the processing of the register allocation processing section 4, FIG. 2 is a diagram showing an example of the intermediate code string 5, and FIG.
6 is a diagram illustrating an example of a graph 6 that is created by the graph coloring means 43 and is subject to "graph coloring" by the graph coloring means 43. FIG.

Next, the operation of the register allocation optimization method using graph coloring of this embodiment configured as described above will be explained.

The register allocation processing section 4 performs the following processing.

The data conflict analysis means 41 refers to the intermediate code string 5, detects sections in which each variable holds valid data, and analyzes whether or not there is overlap between these sections. If there is overlap, infinity is calculated as the evaluation value indicating the overlap. Furthermore, even if there is no such duplication, we analyze whether or not parallelism may be impaired if the same register is allocated to variables corresponding to these intervals in later register allocation, and we examine the possibility of this. If there is, an evaluation value is calculated depending on the size of the possibility.

The graph creation means 42 creates the graph 6 in the following manner. In other words, nodes of the graph 6 are assigned to "sections in which variables hold valid data" analyzed by the data conflict analysis means 41. In addition, the data conflict analysis means 41
An edge connects two nodes corresponding to two sections that have been analyzed as ``there is mutual overlap,'' and an evaluation value of infinity (an evaluation value indicating overlap; in FIG. ) is added to that side. Also, even if there are two sections that do not overlap,
The evaluation value calculated by the data conflict analysis means 41 (according to the possibility of impairing parallelism) is evaluation value) is added to that side.

The graph coloring means 43 uses the evaluation value added to the side of the graph 6 created by the graph creation means 42 as a priority, and colors the graph 6 as follows. First, perform graph coloring using all edges (assign different colors to nodes connected by edges for all edges), and ensure that the number of required colors is less than or equal to the number of available registers. Determine whether or not. If the number of required colors is less than or equal to the number of available registers, graph coloring is completed. If the number of required colors is not less than the number of available registers, remove the edges from graph 6 in order of decreasing evaluation value (low priority) and use the remaining edges to color the graph, and then fill in the necessary colors. The above process is repeated until the number of colors is less than or equal to the number of available registers.

The register allocation means 44 allocates a register to each variable by associating the same register with the node given the same color as a result of graph coloring by the graph coloring means 43.

Next, the register allocation processing by the register allocation processing section 4 will be explained using a specific example (see FIGS. 2 and 3).

For the intermediate code string 5 shown in FIG. 2, the graph creation means 42 creates a graph 6 as shown in FIG. (only shown). Node 61 in graph 6 is section 51 where variable A holds valid data (see Figure 2)
The node 62 is a node corresponding to the interval 52 in which the variable X holds valid data, and the node 63 is a node corresponding to the interval 53 in which the variable Y holds valid data. It is.

In the intermediate code string 5, there is an overlap between the section 51 in which the variable A holds valid data and the section 52 in which the variable X holds valid data. Therefore, the graph creation means 42 connects the node 61 and the node 62 to the side 6.
4, and infinity (in
f) to edge 64.

Since there is overlap between the interval 51 in which variable A holds valid data and the interval 53 in which variable Y holds valid data, node 61 and node 63 are connected by edge 66. , side 66 has an evaluation value of infinity (i
nf) is added.

Although there is no overlap between the interval 52 in which the variable X holds valid data and the interval 53 in which the variable Y holds valid data, the intermediate code instruction sequence 5 (therefore,
Even in source program 1), they are close to each other, so
Allocating the same register is likely to impair parallelism. Therefore, the data conflict analysis means 41 gives an evaluation value (here, "2") depending on the height of the possibility. As a result, the graph creation means 42 connects the node 62 and the node 63 with the edge 65, and adds 2 to the edge 65 as an evaluation value.

The graph coloring means 43 and register allocation means 44 perform graph coloring and register allocation as follows (see FIG. 4).

Based on the configuration of the graph 6, the graph coloring means 43 colors the nodes 61 to 6 connected by the sides 64 to 66.
Assign all 3 different colors. Therefore, the register allocation means 44 allocates separate registers to each node 61 to 63 if three or more registers are available.

However, if there are only two registers available, the graph coloring means 43 removes the added edge 65 with the smaller evaluation value from the graph 6, and adds the same color to nodes 62 and 63. A color is assigned to the node 61, and another color is assigned to the node 61. In this case, the register allocation means 44 allocates the same register to the nodes 62 and 63 (this may impair parallelism, but this is unavoidable due to the limit on the number of available registers).

[0035] Through the above processing, it is possible to perform register allocation that takes advantage of parallelism within the range of available register numbers.

[0036]

[Effects of the Invention] As explained above, the present invention is applicable to cases where there is a possibility that parallelization processing of instructions is hindered by allocating the same register to two nodes, and where there is no overlap in the sections corresponding to the nodes. However, by connecting these nodes with edges, the parallelism of the assembly instruction sequence (target program) can be increased. Furthermore, by giving priority to the edges of the graph, it is possible to deal with the case where there is a shortage of usable registers.

As a result of the above, register allocation using a simple graph coloring method (if the compiler's graph coloring method for a processor consisting of a single operation unit is applied as is to a processor consisting of multiple operation units) This method has the effect that it is possible to generate a target program having execution performance higher than that of the target program generated by register allocation using graph coloring.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an intermediate code string generated by a source program interpreter in FIG. 1;

FIG. 3 is a diagram showing an example of a graph created by the graph creation means in FIG. 1;

[Explanation of symbols]

1 Source program 2 Compiler 3. Purpose program 4 Register allocation processing section 5 Intermediate code string 6 Graph 21 Source program interpretation section 22 Optimization section 23 Serial assembly instruction sequence generator 24 Parallel assembly instruction sequence generator 25 Target program output section 41 Data conflict analysis means 42 Graph creation means 43 Graph coloring means 44 Register allocation means 51-53 section 61-63 Node 64-66 sides

Claims (1)

[Claims] Claim 1: An intermediate code string is generated in the process of generating a target program for a processor that has multiple calculation units operating in parallel and assumes that the instructions executed by each calculation unit are determined at the time of generation of the target program. In a compiler that optimizes register allocation using a graph coloring method, it is possible to determine whether or not there are duplicates and to allocate the same registers for "intervals in which variables hold valid data" in intermediate code strings. A data conflict analysis means that determines the possibility of impairing parallelization of instructions and calculates an evaluation value according to the presence or absence of duplication and the high possibility of impairing parallelization; A graph creation means that creates a graph by connecting nodes corresponding to "intervals in which variables hold valid data" with edges and adding evaluation values to the edges, and nodes connected by edges by this graph creation means. a graph coloring means for allocating a number of different colors according to the number of available registers; and a register allocation means for allocating the same register to variables corresponding to nodes to which the same color is allocated by the graph coloring means. A register allocation optimization method using graph coloring.