JPH04239909A - Method and device for arithmetic processing - Google Patents

Abstract

PURPOSE:To execute a multiplication instruction or an instruction realized with convergent operation during execution of another instruction realized with convergent operation in an arithmetic processing device which performs the pipeline processing. CONSTITUTION:A pipeline multiplier 3 consisting of three stages of higher-order and lower-order multiplying parts 4 and 5 and a binary conversion part 6, a temporary register 7 where data is temporarily held, and a control pipeline which has plural pipelines in the execution stage and following stages are provided, and the period when at least one operation block required for a second instruction processed by this operation block out of operation blocks is unused is detected during execution of a first instruction processed by plural operation blocks, and the second instruction is executed in parallel with execution of the first instruction.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an arithmetic processing device that performs pipeline processing, and in particular executes an instruction realized by convergence type operation and a multiplication instruction or an instruction realized by convergence type operation in parallel. The present invention relates to an arithmetic processing method and an arithmetic processing device for performing convergence-type arithmetic operations at high speed.

0002

2. Description of the Related Art FIG. 6 shows a block diagram of a data path section of a conventional arithmetic processing device. In FIG. 6, 100 is a register that supplies operands, 101 is a data ROM that stores initial values necessary for division, 102 is a multiplier that performs double precision multiplication, 103 is a binary number converter, and 104 is a multiplier that performs double precision multiplication.
is a temporary register for temporarily holding the operation result.

FIG. 7 shows a timing chart when a division instruction is implemented as a convergent operation in a conventional arithmetic processing device. The sequence of each arithmetic unit when executing a division instruction will be explained using FIGS. 6 and 7. Division in floating point arithmetic can be considered separately into an exponent part and a mantissa part, and the exponent part is determined by the difference between the exponent of the dividend X and the exponent of the divisor Y. Therefore, hereafter only operations on the mantissa part will be described. One of the mantissa division algorithms is the Newton-Raphson method, and the recurrence formula for finding the reciprocal of the divisor is shown in equation (1).

[0004] Ri=Ri-1×(2-Ri-1×Ym) (1
) Here, Ym indicates the mantissa part of the divisor, and Ri is the divisor Ym
It is assumed that the initial value R0 is given from the ROM. (1) Divisor Ym obtained from formula
Find the product of the final approximation value Rn of the reciprocal of and the mantissa part Xm of the dividend, and use this as the quotient. If the initial value R0 is given with a precision of 2-9, in order to satisfy the precision of double precision floating point, (1)
It is necessary to find up to R3 in the formula. The recurrence formula shown in equation (1) is Ri-1×Ym and Ri-1×(2-R
i-1×Ym) twice. Figure 6
In the data path section of the arithmetic processing unit shown in Fig.
This is realized by binary number conversion in cycles (2 clocks).

In FIGS. 6 and 7, operand Ym is read from register 100 at the L stage. In the first cycle of E stage, operand Ym is in ROM1.
01 and reads out the initial value R0, which is also written to the temporary register 104. In the second cycle of the E stage, the calculation of R0×Ym is executed. In the third cycle of the E stage, the calculation result R0×Ym from the previous cycle is input directly to the multiplier side of the multiplier 102 without passing through the binary converter 103, and is recoded as a value of 2-R0×Ym, and is converted to R0. At the same time as the multiplication is performed, the operand Ym is read from the temporary register 104. In the fourth cycle of the E stage, the calculation result R1 from the previous cycle is sent to the binary number converter 103 and converted, and the calculation result R1 is directly sent to the multiplier 102.
is input to the multiplier side and the calculation of R1×Ym is performed. In the 5th cycle of the E stage, the calculation result of the previous cycle R1×
Ym is directly input to the multiplier 10 without passing through the binary converter 103.
It is input to the multiplier side of 2, is recoded as a value of 2-R1×Ym, and is multiplied by the output result R1 of the binary converter 103. In the sixth cycle of the E stage, the calculation result R2 from the previous cycle is sent to the binary number converter 103 and converted, and the calculation result R2 is directly sent to the multiplier 1.
02 is input to the multiplier side and multiplied by R2×Ym. In the 7th cycle of the E stage, the calculation result R2×Ym from the previous cycle is directly input to the multiplier side of the multiplier 102 without passing through the binary number converter 103, and is recoded as a value of 2-R2×Ym and converted into a binary number. Output result R2 of converter 103
Execute the multiplication R2×(2−R2×Ym). In the 8th cycle of the E stage, the calculation result R3 is directly
It is input to the multiplier side of the multiplier 102 and performs Xm×R3. E
In the ninth cycle of the stage, the division result Xm×R3 is converted into a binary number and rounded, and the result is written to the register 100 in the S stage. As described above, double precision division is executed in 9 cycles (18 clocks).

FIG. 8 shows the structure of a control pipeline of a conventional arithmetic processing device. In FIG. 8, 111
112 is an I stage for decoding instructions, 112 is an L stage for sending operands necessary for operations from registers to arithmetic units, 113 is an E stage for executing operations, and 114 is for writing operation results to registers. The S stage 115 is a state machine that indicates the state of the arithmetic unit.

FIG. 9 is a timing chart showing the progress of a pipeline for each instruction in a conventional arithmetic processing device. In FIG. 9, the first division instructions 120 to 123 are in the I stage, L stage, E stage, and S stage, respectively.
During the periods 124 to 127, the second multiplication instructions are in the I stage, L stage, E stage, and
During the S stage, 128 indicates the I stage wait signal.

The operation of the conventional arithmetic processing device configured as described above when executing the instruction sequence shown in FIG. 9 will be described below. 8 and 9, when the first division instruction fdivd advances to the L stage 121, the state machine 115 sets the wait signal 128 to High for the I stage 111, and waits until the wait signal 128 becomes Low. Multiplication instruction fmul
d into the locked state. Next, the first division instruction fdivd
Proceeds to the E stage 122, where the convergent division shown in FIG. 7 is executed using the multiplier 102 and the binary converter 103. The state machine 115 sets the wait signal 128 for the I stage 111 to Low two cycles before the S stage 123 of the first division instruction fdivd.
and the E stage 122 of the first division instruction fdivd
In the final cycle, the second multiplication instruction fmuld is sent to the L stage 125. The first division instruction fdivd enters the S stage 123 and writes its operation result to the register 100. At the same time, the second multiplication instruction fmuld advances to the E stage 126 and starts executing the multiplication instruction. Next, the second multiplication instruction fmuld enters the S stage 127 and writes the result of the operation to the register 100.

[0009]

[Problem to be Solved by the Invention] However, in the above configuration, while the division instruction is in the E stage, subsequent instructions are in a pipe-locked state, and until the division instruction reaches the S stage, the next instruction cannot be executed. The command is not executed. That is, while an instruction realized by convergent operation is being executed, other instructions cannot be executed, resulting in a problem that the performance of the arithmetic processing device itself deteriorates.

[0010] Furthermore, in realizing convergent arithmetic operations, there was a problem in that the arithmetic execution speed could not be increased because arithmetic operations were performed with the same bit width regardless of the level of arithmetic precision.

In view of the above, the present invention improves performance by making it possible to execute other multiplication instructions or instructions realized by convergent arithmetic while executing an instruction realized by convergent arithmetic. It is an object of the present invention to provide an arithmetic processing method and an arithmetic processing device that can realize the above, and furthermore, an arithmetic processing device that can perform convergent arithmetic at high speed.

0012

Means for Solving the Problems In order to solve the above problems, the arithmetic processing method of the present invention provides a method for processing at least one of the arithmetic blocks during execution of a first instruction processed by a plurality of arithmetic blocks. When fetching a second instruction to be processed by the arithmetic block, detecting an unused period of the arithmetic block necessary for the second instruction during execution of the first instruction;
The second instruction is executed in parallel with the execution of the first instruction.

Further, the arithmetic processing device of the present invention includes a pipeline multiplier having a three-stage configuration of a high-order side multiplication section, a low-order side multiplication section, and a binary number conversion section, a register for supplying operands, and a temporary It is equipped with a temporary register that holds data, and a control pipeline that has multiple pipeline structures after the execution stage. This makes it possible to execute instructions realized as .

Further, the arithmetic processing device of the present invention includes the pipeline multiplier, the temporary register, and a control section that controls the sequence of the multiplier and the binary conversion section of the pipeline multiplier. , when executing an instruction realized as a convergent operation, if the operation precision is low, the operation is performed using either the high-order or low-order multiplication section and the binary conversion section; When the input bit width is larger than the input bit width of the multiplier on either side, the multiplier on the high-order side and the low-order side and the binary conversion section are used to perform the operation, so that the convergence type operation can be executed at high speed. It made it possible.

[0015]

[Operation] According to the above-described structure, when a multiplication instruction or a second instruction realized by a convergent operation instruction is fetched while a first instruction realized by a convergent operation is being executed, Detects the unused period of each stage of the pipeline multiplier that occurs due to repeated execution of the recurrence formula, and when the second instruction is a multiplication instruction, the first execution pipeline in which the first instruction exists is The second instruction is executed in parallel with the execution of the first instruction by supplying the second instruction to a separate second execution pipeline. If the second instruction is an instruction realized by a convergent operation, supplying the second instruction to the first execution pipeline in accordance with the progress of the execution stage of the first instruction in the first execution pipeline; A second instruction is executed during execution of the first instruction. The instruction fetched during the execution of the first instruction continues to be fetched during the period in which the unused period of each stage of the pipelined multiplier is detected.
Alternatively, it is executed by supplying it to the second execution pipeline, and the result of the operation is temporarily stored in a temporary register. When the execution of the first instruction is completed and the operation result of the first instruction is written to the register, the operation result written to the temporary register is also moved to the register. As a result, even during the execution of an instruction realized by convergent operation, the next operation instruction can be executed without continuing to lock the control pipeline.

[0016] Furthermore, in order to realize the convergent operation according to the present invention, with the above-described configuration, when the operation accuracy is low, the operation is performed using either the high-order side or the low-order side multiplication section and the binary conversion section. When the precision becomes larger than the input bit width of either the high-order side or the low-order side multiplier, the calculation is performed using the high-order side and low-order side multipliers and the binary conversion section. As a result, the convergence type calculation can be executed at high speed by the number of cycles that can be saved when the calculation accuracy is low.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a data path section of an arithmetic processing unit in a first embodiment of the present invention. In Figure 1,
1 is a register that supplies operands, 2 is a data ROM that stores initial values necessary for division, 3 is a pipeline type multiplier that performs double precision multiplication, and 4 to 6 are pipeline type multipliers 3, respectively. These are a low-order multiplication section, a high-order multiplication section, and a binary number conversion section. 7 is a temporary register for temporarily holding the calculation result.

FIG. 2 shows the case where the division instruction is realized as a convergent operation in the arithmetic processing device according to the first embodiment of the present invention.
When the arithmetic precision is low, the high-order side multiplier and the binary conversion section are used to perform the calculation, and when the arithmetic precision becomes larger than the input bit width of the high-order side multiplier, the high-order side and low-order side multipliers are used.
A timing chart when executing a sequence in which arithmetic operations are performed using a base number conversion unit is shown.

Regarding the arithmetic processing device configured as described above, the sequence of each arithmetic unit when executing the double-precision division instruction shown in FIG. 2 will be described. In the data path section of the arithmetic processing unit shown in Figure 1, double-precision floating-point multiplication is performed in two cycles (
This is realized by multiplication of 2 clocks) and binary conversion of 1 cycle (1 clock). In FIG. 2, operand Ym is read from register 1 at the L stage. In the first cycle of E1 stage, operand Ym is in ROM
2 and reads out the initial value R0, which is also written to the temporary register 7. In the second cycle of the E1 stage, the calculation R0×Ym is executed. At this time R
Focusing on the low precision of 0, double precision is not required as the input width of the multiplier. Therefore, the calculation can be executed only by the high-order side multiplier 5 with R0 as the multiplier side (recorder side) input and Ym as the multiplicand side input. E1 stage 3
In the cycle, the calculation result from the previous cycle is R0×Y
m is input directly to the multiplier side of the multiplier 3 without passing through the binary number converter 6, and is recoded as a value of 2-R0×Ym, R0
The operand Ym is read out from the temporary register 7 at the same time as the multiplication with . At this time, paying attention to the low precision of R0×Ym as in the previous cycle, only the high-order multiplier 5 executes the calculation. In the fourth cycle of the E1 stage, the calculation result R1 from the previous cycle is sent to the binary number converter 6 and converted, and the calculation result R1 is directly input to the multiplier side of the multiplier 3 for calculation of R1×Ym. . At this time, paying attention to the low precision of R1 as in the previous cycle, only the high-order multiplier 5 executes the calculation. In the fifth cycle of the E1 stage, the calculation result R1×Ym from the previous cycle is input directly to the multiplier side of the multiplier 3 without passing through the binary number converter 6, and is recoded as a value of 2-R1×Ym, and converted into a binary number. Multiplication with the output result R1 of the converter 6 is performed. At this time, since the accuracy of the calculation result R1×Ym of the previous cycle is greater than the multiplier side input width of the high-order side multiplier 5, the calculation is first performed in the low-order side multiplier 4, and then in the next cycle, the high-order side multiplier 5 Execute the calculation in .

The subsequent multiplications are performed using both the high-order side 5 and low-order side 4 multipliers in order to improve the calculation accuracy. E2d
In the first cycle of stage, R1×(2-R1×Y
At the same time, the operand Ym is read from the temporary register 7. In the second cycle of the E2d stage, the calculation result R of the previous cycle
2 is sent to the binary number converter 6 and converted, and the calculation result R2 is directly input to the multiplier side of the multiplier 3, and R2×
Perform low-order multiplication of Ym. In the third cycle of the E2d stage, the high-order side multiplication of R2×Ym is performed, and at the same time, R2, which has been converted into a binary number in the previous cycle, is written into the temporary register 7. In the 4th cycle of E2d stage,
The calculation result R2×Ym in the previous cycle is input directly to the multiplier side of the multiplier 3 without passing through the binary converter 6, and is calculated as 2−R2×
It is recoded as the value of Ym, R2 is read from the temporary register 7, and low-order side multiplication of R2×(2−R2×Ym) is performed. At the 5th cycle of E2d stage, R2
Operand Xm is read from register 1 at the same time as the high-order side multiplication of ×(2−R2×Ym) is performed. In the sixth cycle of the E2d stage, the calculation result R3 is directly input to the multiplier side of the multiplier 3 to perform a low-order side multiplication of Xm×R3. In the seventh cycle of the E2d stage, a high-order side multiplication of Xm×R3 is performed. At the E3d stage, the division result X
Perform binary conversion and rounding of m×R3, and write the result to register 1 in the S stage.

As described above, according to this embodiment, a pipeline multiplier consisting of a three-stage configuration of a high-order side multiplication section, a low-order side multiplication section, and a binary number conversion section, and a temporary register for temporarily holding data are used. By providing this, when the arithmetic precision is low in the sequence of division instructions, the high-order side multiplier and binary conversion section are used to perform the operation, and when the arithmetic precision becomes larger than the input bit width of the high-order side multiplier, the high-order side multiplier is used. It is possible to perform calculations using the low-order side multiplier and binary conversion section,
Double precision division can be executed in 13 cycles (13 clocks).

Furthermore, in the first cycle of the E2d stage, the low-order multiplier 4 is unused, and in the second cycle of the E2d stage, the high-order multiplier 5 is used, and in the third cycle of the E2d stage, the low-order multiplier 4 is unused. The side multipliers 4 are each unused. Therefore, the E1 stage 5
If the operand is read out in the cycle, multiplication can be executed while the multipliers 4 to 5 and the binary converter 6 are not used, and the result of the operation can be written to the temporary register 7. Similarly, if the operand is read in the second cycle of the E2d stage, multiplication can be executed during the unused period of each multiplier 4 to 6 and the binary conversion part 6 in the 3rd to 5th cycles of the E2d stage, and the operand is read in the 4th cycle of the E2d stage. If you read out
.about.5 and the binary number converter 6 are not used, the multiplication can be performed.

In this embodiment, the instruction realized by the convergence-type operation is a division instruction, but the same effect can be obtained by convergence-type operations such as square root operation instructions and elementary functions. Further, although the multiplication when the calculation precision is low is performed using the high-order multiplication section, the same effect can be obtained by using the low-order multiplication section.

FIG. 3 shows a structural diagram of a control pipeline of an arithmetic processing unit in a second embodiment of the present invention. In FIG. 3, 11 is an I stage for decoding instructions, 12 is an L stage for sending operands necessary for an operation from a register to an arithmetic unit, 13 is an E1 stage for executing an operation, and 14 and 15 are E2d and E3d stages for performing division/square root operations, respectively, 1
6 is an S stage for writing the calculation result to the register;
17 and 18 are the E2m stage and E3m stage for executing multiplication, respectively; 19 is an SQue for writing the operation result into a temporary register and then writing the operation result to the register; 20 is a state machine that indicates the state of the arithmetic unit. be.

FIG. 4 is a timing chart showing the progress of the pipeline for each instruction in the arithmetic processing device according to the second embodiment of the present invention. In FIG. 4, 31 to 36 are the first
During periods 37 to 43, the second multiplication instructions are in the I stage, L stage, E1 stage, E2d stage, E3d stage, and S stage, respectively.
44 to 49 are periods in which the third division instruction is in the I stage, L stage, E1 stage, E2d stage, and E3, respectively.
D stage, S stage period, 50-56 is the 4th stage
During periods 57 to 63, the fifth multiplication instructions are in the I stage, L stage, E1 stage, E2m stage, E3m stage, Sq0 stage, and S stage, respectively. stage, E3m stage, Sq0 stage,
Periods 64 to 66 are periods in which the sixth to eighth multiplication instructions are in the S stage, and periods 67 to 72 are periods in which the ninth multiplication instructions are in the I stage, L stage, E1 stage, E2m stage, and E3m stage, respectively. , 73 indicates an I stage wait signal during the S stage.

FIG. 5 shows that when a double-precision division instruction is realized as a convergent operation in the arithmetic processing device of this embodiment, the operation is performed using the multipliers on the high-order side and the low-order side and the binary conversion section, regardless of the calculation accuracy. A timing chart for executing the sequence is shown. If the second division instruction is fetched while the first division instruction in the sequence shown in FIG. 2 is being executed, if the second division instruction is executed in the sequence shown in FIG. The second division instruction can be executed during the unused period of the unit and the binary conversion unit.

The operation of the arithmetic processing device according to the second embodiment of the present invention configured as described above will be described below when the instruction sequence shown in FIG. 4 is executed. 3 and 4, the state machine 20 operates in I stage 1 when the first division instruction fdivd advances to L stage 32.
1, the wait signal 73 is made High, and the second multiplication instruction fmuld is executed until the wait signal 73 becomes Low.
to the locked state. Next, the first division instruction fdivd advances to the E1 stage 33 and executes the operation sequence shown in FIG. The state machine 20 executes a first division instruction f
In the fourth cycle of the E1 stage 33 of divd, the wait signal 73 for the I stage 11 is set to Low, and in the next cycle, the second multiplication instruction fmuld is sent to the L stage 38, and at the same time, the I stage 1 of the third division instruction fdivd is set to low.
1, the wait signal 73 is set to High. The first divide instruction fdivd then advances to the E2d stage 34 of the divide/square root operation execution pipe and the second multiply instruction fm
uld advances to E1 stage 39 and state machine 2
0 sets the wait signal 73 for the I stage 11 of the third division instruction fdivd to Low.

While the first division instruction fdivd is in the E2d stage 4 of the division/square root execution pipe, the second multiplication instruction fmuld proceeds through the multiplication execution pipes 17-18 according to information from the state machine 20. is completed, and the first division instruction fdivd is transferred to E2d stage 14 and E2d stage 14.
While in the 3d stage 15, the second multiply instruction fmuld
The instruction is retained in the SQue 19, and the operation result is temporarily stored in the temporary register 7. First division instruction fdi
At the same time that vd enters the S stage 36, the operation result of the second multiplication instruction fmuld in the SQue 19 is written from the temporary register 7 to the register 1. While the first divide instruction fdivd is in the E2d stage 34, the third divide instruction fdivd advances from the I stage 44 to the E1 stage 46, and at the same time as the first divide instruction fdivd advances to the E3d stage 35, the third divide instruction fdivd advances to the E3d stage 35. fdivd is E
Proceed to 2d stage 47. The first division instruction fdivd is in the E2d stage 34 and the third division instruction fdi
While vd is in the E1 stage 46, each stage of the multiplier is executing an operation, so other multiplication instructions, division instructions, and square root operation instructions cannot be executed. The state machine 20 sets the wait signal 73 for the I stage 11 to Lo two cycles before the third division instruction fdivd moves to the E2d stage 47.
w, and the fourth multiplication instruction fmuld is set to L in the next cycle.
At the same time as moving to the stage 51, the wait signal 73 for the I stage 11 is set to High. Third division instruction fd
At the same time as ivd moves to the E2d stage 47, the fourth multiplication instruction fmuld moves to the E1 stage 52 and sets the wait signal 73 for the I stage 11 to Low. While the third divide instruction fdivd is in the E2d stage 47, the 2
A multiplication instruction is accepted every cycle, and the fourth to eighth multiplication instructions fmuld all remain in the Sque 19, and the operation results are temporarily stored in the temporary register 7.

The third division instruction fdivd is at S stage 4.
9, the fourth multiplication instruction f in SQue19 at the same time
The operation result of muld is written from temporary register 7 to register 1. Next, the 5th in SQue 19
, the operation result of the sixth multiplication instruction fmuld is written from temporary register 7 to register 1, and then SQue
The operation results of the seventh and eighth multiplication instructions fmuld in step 19 are written from temporary register 7 to register 1. The ninth multiplication instruction fmuld is the third division instruction fdi
At the same time as vd enters S stage 49, E1 stage 69
, the ninth multiplication instruction fmuld is executed at E3m stage 7.
1, the operation results of the seventh and eighth multiplication instructions fmuld are written into register 1. As a result, all the operation results of the instructions executed before the ninth multiplication instruction fmuld can be written to register 1, and the ninth
The multiplication instruction fmuld can be moved to the S stage 72 after the E3m stage 71.

As described above, according to this embodiment, after the E2 stage, the control pipeline is divided into a division/square root operation instruction execution pipeline and a multiplication instruction execution pipeline, and the operation results are temporarily stored in a temporary register. By providing the SQue, it is possible to detect the unused period of each stage of the pipeline multiplier even during execution of a division instruction, which is a convergent operation, and to execute multiplication instructions and division instructions in parallel. In addition, if the second division instruction is fetched while the first division instruction is being executed, the sequence of the second division instruction is processed using the high-order and low-order multipliers and the binary conversion section, regardless of the arithmetic precision. By performing the same operation, the second division instruction can be executed in parallel while the first division instruction is being executed.

In this embodiment, the instruction realized by the convergence-type operation is a division instruction, but the same effect can be obtained by convergence-type operations such as square root operation instructions and elementary functions. In addition, in this embodiment, there are two pipelines after the execution stage, but there may be more than one pipeline, or even just one pipeline can be used if the state machine can control the execution of instructions before the execution stage. You can get the effect. Furthermore, in this embodiment, the case where a convergence type operation is executed has been described, but the first
When processing is performed using multiple blocks when executing an instruction, the same effect can be obtained by detecting the unused period of the block and executing the second instruction during the unused period. .

[0032]

[Effects of the Invention] As explained above, according to the present invention,
By detecting the unused period of each multiplication unit and binary conversion unit during the execution of an instruction realized by convergent operation, the next operation instruction can be executed without continuing to lock the control pipeline. Furthermore, in executing convergent operations, by changing the combination of multipliers depending on the level of accuracy, high-speed execution of convergent operations becomes possible. Therefore, by using the arithmetic processing method and arithmetic processing device of the present invention, performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data path section of an arithmetic processing device in a first embodiment of the present invention.

FIG. 2 is a timing chart during high-speed execution of a division instruction in the arithmetic processing device of the first embodiment.

FIG. 3 is a structural diagram of a control pipe of an arithmetic processing unit in a second embodiment of the present invention.

FIG. 4 is a timing chart showing the progress of the pipeline for each instruction in the arithmetic processing device of the second embodiment.

5 is a timing chart diagram of a division instruction to be executed in parallel with the division instruction shown in FIG. 2 of the first embodiment in the arithmetic processing device of the second embodiment; FIG.

FIG. 6 is a block diagram of a data path section of a conventional arithmetic processing device.

FIG. 7 is a timing chart diagram when a division instruction is implemented as a convergent operation in a conventional arithmetic processing device.

FIG. 8 is a structural diagram of a control pipe of a conventional arithmetic processing device.

FIG. 9 is a timing chart showing the progress of a pipeline for each instruction in a conventional arithmetic processing device.

[Explanation of symbols]

1 Register 2 Data ROM 3 Pipeline multiplier 4 Low-order side multiplication section 5 of pipeline multiplier
High-order side multiplication section 6 2 of pipeline type multiplier
Base number converter 7 Temporary register 11 I stage 12 L stage 13 E1 stage 14 E2d stage 15 of division/square root operation execution pipe E3d of division/square root operation execution pipe
Stage 16 S stage 17 E2m stage 18 of the multiplication execution pipe
E3m stage 19 SQ of multiplication execution pipe
ue 20 state machine

Claims (5)

[Claims] 1. When a second instruction to be processed by at least one of the arithmetic blocks is fetched during execution of a first instruction to be processed by a plurality of arithmetic blocks, An arithmetic processing method characterized by detecting an unused period of an arithmetic block required for a second instruction during execution, and executing the second instruction in parallel with execution of the first instruction. 2. A plurality of pipelines are provided after the execution stage of the control pipeline, and during execution of a first instruction to be processed by a plurality of calculation blocks, the instruction is processed by at least one of the calculation blocks. When a second instruction is fetched, an unused period of an operation block required for the second instruction is detected during execution of the first instruction,
means for supplying the second instruction to a second execution pipeline different from the first execution pipeline in which the first instruction exists and executing the second instruction in parallel with execution of the first instruction; An arithmetic processing device characterized by being provided. 3. A plurality of pipelines are provided after the execution stage of the control pipeline, and during execution of a first instruction processed by a plurality of arithmetic blocks, the instruction is processed by at least one arithmetic block among the arithmetic blocks. When a second instruction is fetched, an unused period of an operation block required for the second instruction is detected during execution of the first instruction,
The control pipeline is characterized by providing means for executing the second instruction in parallel with the execution of the first instruction by setting the state of the control pipeline to the execution state with respect to the second instruction before the execution stage. Arithmetic processing unit. 4. A pipelined multiplier having a configuration of at least three or more stages, wherein while a first instruction realized by a convergent operation is being executed, a second instruction realized by a multiplication instruction or a convergence operation instruction is executed. When an instruction is fetched, means is provided for detecting an unused period in each stage of the pipeline multiplier while executing the first instruction, and executing the second instruction during the same period. A processing unit that performs 5. A pipelined multiplier consisting of a three-stage configuration of high-order side and low-order side multipliers and a binary number conversion section, and a sequence of the multiplication section and the binary number conversion section is controlled and realized as a convergent operation. When executing an instruction, if the arithmetic precision is low, the multiplier on either the high-order side or the low-order side and the two
Calculation is performed using the base conversion unit, and when the calculation precision becomes larger than the input bit width of either the high-order side or low-order side multiplication unit, the calculation is performed using the high-order side and low-order side multiplication units and the binary conversion unit. 1. An arithmetic processing device comprising: a control unit configured to perform control.