JPH04239161A - Resin-sealed type semiconductor device - Google Patents
Resin-sealed type semiconductor deviceInfo
- Publication number
- JPH04239161A JPH04239161A JP188691A JP188691A JPH04239161A JP H04239161 A JPH04239161 A JP H04239161A JP 188691 A JP188691 A JP 188691A JP 188691 A JP188691 A JP 188691A JP H04239161 A JPH04239161 A JP H04239161A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor element
- resin
- semiconductor
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 239000002952 polymeric resin Substances 0.000 claims description 2
- 229920003002 synthetic resin Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 230000035515 penetration Effects 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 1
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、樹脂封止型半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】0002
【従来の技術】従来の樹脂封止型半導体装置についてそ
の製造工程に沿って説明する。図５，図６を参照すると
、配線導体１が形成されたプリント基板２を、リードフ
レーム３の基板パッド４に貼り付け、かつプリント基板
２上に半導体素子５をＡｇペースト等で固着した後、金
線等のボンディングワイヤー６により、半導体素子５の
電極パッドとプリント基板２上の配線１の一方の電極及
び配線導体１の他方の電極とリードフレーム３の外部リ
ード７とを電気的に接続する。2. Description of the Related Art A conventional resin-sealed semiconductor device will be explained along with its manufacturing process. Referring to FIGS. 5 and 6, the printed circuit board 2 on which the wiring conductor 1 is formed is attached to the substrate pad 4 of the lead frame 3, and the semiconductor element 5 is fixed on the printed circuit board 2 with Ag paste or the like. The electrode pad of the semiconductor element 5, one electrode of the wiring 1 on the printed circuit board 2, the other electrode of the wiring conductor 1, and the external lead 7 of the lead frame 3 are electrically connected by a bonding wire 6 such as a gold wire. .
【０００３】さらに、その後、トランスファーモールド
法等により、エポキシ樹脂等で樹脂封止する。その後、
リードフレームから切り離して図５のような樹脂封止型
半導体装置が得られる。このような従来技術は、樹脂封
止型半導体装置の中でも、特に同一封止パッケージの中
に、複数の半導体素子を搭載するハイブリッドＩＣに用
いられていた。[0003]Furthermore, thereafter, the resin is sealed with epoxy resin or the like by a transfer molding method or the like. after that,
A resin-sealed semiconductor device as shown in FIG. 5 is obtained by separating it from the lead frame. Such conventional technology has been used in resin-sealed semiconductor devices, particularly in hybrid ICs in which a plurality of semiconductor elements are mounted in the same sealing package.
【０００４】0004
【発明が解決しようとする課題】この従来の樹脂封止型
半導体装置では、半導体素子の高消費電力化に伴う、低
熱抵抗化の要求に対し、半導体素子をガラスエポキシ等
のプリント基板上に搭載するため、半導体素子を鉄−ニ
ッケル合金や銅等のリードフレームに直接、銀ペースト
等で固着した場合に比べて、半導体装置の熱放散性が悪
く、半導体素子の信頼性を著しく劣化させるため、高消
費電力の半導体素子を搭載することが困難であった。ま
た、この従来の構造では、１つの半導体素子の大きさに
対応して、１つのプリント基板が必要となるため、半導
体素子の多様化に対応するためには、多数のプリント基
板が必要となり、コスト高になってしまうという欠点を
有していた。[Problems to be Solved by the Invention] In this conventional resin-sealed semiconductor device, the semiconductor element is mounted on a printed circuit board made of glass epoxy or the like in order to meet the demand for lower thermal resistance as the power consumption of semiconductor elements increases. As a result, the heat dissipation of the semiconductor device is poorer than when the semiconductor element is directly fixed to a lead frame made of iron-nickel alloy, copper, etc. using silver paste, etc., and the reliability of the semiconductor element is significantly deteriorated. It was difficult to mount semiconductor elements with high power consumption. Furthermore, in this conventional structure, one printed circuit board is required to correspond to the size of one semiconductor element, so in order to cope with the diversification of semiconductor elements, a large number of printed circuit boards are required. This has the disadvantage of high cost.
【０００５】[0005]
【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、半導体素子搭載台と、半導体素子に対応する
形状の貫通孔および表面に設けられた配線体を有し、裏
面を前記半導体素子搭載台に接着された絶縁性フィルム
と、前記半導体素子搭載台の前記貫通孔部に接着された
半導体素子と、前記配線導体と前記半導体素子とを結ぶ
第１ボンディングワイヤーと、前記配線導体と第２ボン
ディングワイヤーで結ばれた外部リードとを有するとい
うものである。[Means for Solving the Problems] A resin-sealed semiconductor device of the present invention has a semiconductor element mounting base, a through hole having a shape corresponding to the semiconductor element, and a wiring body provided on the front surface, and an insulating film adhered to a semiconductor element mounting base; a semiconductor element adhered to the through-hole portion of the semiconductor element mounting base; a first bonding wire connecting the wiring conductor and the semiconductor element; and the wiring conductor. and an external lead connected by a second bonding wire.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明する
。図１は本発明の第１の実施例の断面図、図２は樹脂封
止前の状態を示す平面図でリードフレームの１こまの１
／４の部分を示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 is a plan view showing the state before resin sealing, showing one frame of the lead frame.
/4 part is shown.
【０００７】本実施例の半導体装置は、配線導体１を有
し、かつ半導体素子５に対応する大きさで中心部を切断
された絶縁性フィルム９を、リードフレーム３の一部で
あり従来例で述べたところの基板パッドである半導体素
子搭載台部１０に熱圧着などにより接合しているため、
半導体素子５を直接、半導体素子搭載台部１０に銀ペー
スト等により、固着させることができる。このため、従
来例のようにプリント基板に、半導体素子を搭載した場
合に比べて、半導体装置の熱放散性が向上し、２５％以
上の熱抵抗低減が可能になった。また、絶縁性フィルム
９は、厚さ５０μｍ程度のポリイミド等の高分子樹脂に
より構成されており、無電解メッキ等により銅などの配
線導体１が形成されている。さらに、この絶縁性フィル
ム９上の配線導体１を介して、半導体素子５と外部リー
ド７が金線等の第１，第２のボンディングワイヤー６ａ
，６ｂにより、電気的に接続されるという構造を有して
いる。In the semiconductor device of this embodiment, an insulating film 9 having a wiring conductor 1 and cut at the center to a size corresponding to the semiconductor element 5 is a part of a lead frame 3 and is different from the conventional example. Since it is bonded to the semiconductor element mounting base 10, which is the substrate pad mentioned in , by thermocompression bonding or the like,
The semiconductor element 5 can be directly fixed to the semiconductor element mounting base 10 using silver paste or the like. Therefore, compared to the case where a semiconductor element is mounted on a printed circuit board as in the conventional example, the heat dissipation of the semiconductor device is improved, and it becomes possible to reduce the thermal resistance by 25% or more. The insulating film 9 is made of a polymer resin such as polyimide and has a thickness of about 50 μm, and the wiring conductor 1 made of copper or the like is formed by electroless plating or the like. Furthermore, the semiconductor element 5 and the external lead 7 are connected to the first and second bonding wires 6a such as gold wires via the wiring conductor 1 on the insulating film 9.
, 6b, it has a structure in which it is electrically connected.
【０００８】図３は本発明の第２の実施例を説明するた
めの平面図であり樹脂封止直前の状態を示している。図
４は絶縁性フィルムの形成方法を説明するための平面図
で、半導体素子搭載台部１０に接合する前の絶縁性フィ
ルムの平面図である。FIG. 3 is a plan view for explaining a second embodiment of the present invention, showing the state immediately before resin sealing. FIG. 4 is a plan view for explaining the method of forming the insulating film, and is a plan view of the insulating film before being bonded to the semiconductor element mounting base 10. As shown in FIG.
【０００９】第１の実施例との構造上の相違は、配線導
体１が絶縁性フィルム９ｂの貫通孔側の縁まで延びてい
ることである。第１の実施例よりは第１ボンディングワ
イヤーを短くできる。The structural difference from the first embodiment is that the wiring conductor 1 extends to the edge of the insulating film 9b on the through-hole side. The first bonding wire can be made shorter than in the first embodiment.
【００１０】次に、この実施例の製造方法について説明
する。Next, the manufacturing method of this embodiment will be explained.
【００１１】まず図４に示すような絶縁性フィルム９ａ
を準備する。ポリイミドフィルムの中心部１３から４方
へ放射状に延びる配線導体１ａを多数設ける。次に切断
ライン１２の位置でポリイミドフィルムを切断し矩形状
貫通孔を設ける。次に、リードフレーム３の半導体素子
統裁部１０に熱圧着などにより接合する。半導体素子５
をマウントし、半導体素子５のボンディングパッドと配
線導体１ａの一端を第１ボンディングワイヤー６ａで接
続し、配線導体１ａの他端とリードフレームの内部リー
ドとを第２ボンディングワイヤー６ｂで接続する。樹脂
封止を行ない、個片化することにより樹脂封止型半導体
装置を得る。First, an insulating film 9a as shown in FIG.
Prepare. A large number of wiring conductors 1a are provided extending radially in four directions from the central portion 13 of the polyimide film. Next, the polyimide film is cut at the cutting line 12 to form a rectangular through hole. Next, it is bonded to the semiconductor element binding portion 10 of the lead frame 3 by thermocompression bonding or the like. Semiconductor element 5
The bonding pad of the semiconductor element 5 and one end of the wiring conductor 1a are connected by a first bonding wire 6a, and the other end of the wiring conductor 1a and the internal lead of the lead frame are connected by a second bonding wire 6b. A resin-sealed semiconductor device is obtained by performing resin sealing and dividing into pieces.
【００１２】切断ライン１２の位置を加減することによ
り、半導体素子５の大きさに合わせて、貫通孔を形成で
きるので、１種類のフィルムで、種々の半導体素子に対
応することができ、第１の実施例に比べて、大幅なコス
ト低減を図れるという利点を有している。By adjusting the position of the cutting line 12, a through hole can be formed according to the size of the semiconductor element 5, so one type of film can be used for various semiconductor elements. This embodiment has the advantage of being able to significantly reduce costs compared to the embodiment.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、配線導体
を有する絶縁性フィルムに、半導体素子に対応する貫通
孔を設けたものを半導体素子搭載台に接合し、貫通孔部
に露出した半導体素子搭載台に半導体素子をマウントす
る構造にしたことにより、半導体素子搭載台が、ヒート
スプレッダーとして有効に機能し、半導体装置の熱放散
性が大幅に向上したことにより従来品と比べて、２５％
以上の熱抵抗低減ができ、高消費電力の半導体素子の搭
載が可能になった。Effects of the Invention As explained above, the present invention provides an insulating film having a wiring conductor provided with a through hole corresponding to a semiconductor element, which is bonded to a semiconductor element mounting base, and a semiconductor element exposed in the through hole. By adopting a structure in which the semiconductor element is mounted on the element mounting stand, the semiconductor element mounting stand functions effectively as a heat spreader, and the heat dissipation of the semiconductor device is significantly improved, resulting in a reduction of 25% compared to conventional products.
This reduction in thermal resistance has made it possible to mount semiconductor elements with high power consumption.
【図１】本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
【図２】本発明の第１の実施例の説明に使用する部分断
面図で、樹脂封止直前の状態を示している。FIG. 2 is a partial cross-sectional view used to explain the first embodiment of the present invention, showing a state immediately before resin sealing.
【図３】本発明の第２の実施例を説明するための部分平
面図である。FIG. 3 is a partial plan view for explaining a second embodiment of the present invention.
【図４】本発明の第２の実施例の製造方法を説明するた
めの部分平面図である。FIG. 4 is a partial plan view for explaining the manufacturing method of the second embodiment of the present invention.
【図５】従来例の断面図である。FIG. 5 is a sectional view of a conventional example.
【図６】従来例の説明に使用する部分平面図である。FIG. 6 is a partial plan view used to explain a conventional example.
１ 配線導体
２ 基板
３ リードフレーム
４ 基板パッド
５ 半導体素子
６ ボンディングワイヤー
６ａ 第１ボンディングワイヤー６ｂ 第
２ボンディングワイヤー７ 外部リード
８ 封止樹脂
９ 絶縁性フィルム
１０ 半導体素子搭載台
１１ 吊りリード
１２ 切断ライン1 Wiring conductor 2 Board 3 Lead frame 4 Board pad 5 Semiconductor element 6 Bonding wire 6a First bonding wire 6b Second bonding wire 7 External lead 8 Sealing resin 9 Insulating film 10 Semiconductor element mounting stand 11 Hanging lead 12 Cutting line
Claims (2)
応する形状の貫通孔および表面に設けられた配線導体を
有し、裏面を前記半導体素子搭載台に接着された絶縁性
フィルムと、前記半導体素子搭載台の前記貫通孔部に接
着された半導体素子と、前記配線導体と前記半導体素子
とを結ぶ第１ボンディングワイヤーと、前記配線導体と
第２ボンディングワイヤーで結ばれた外部リードとを有
することを特徴とする樹脂封止型半導体装置。1. A semiconductor element mounting base, an insulating film having a through hole shaped to correspond to the semiconductor element and a wiring conductor provided on the front surface, the back surface of which is adhered to the semiconductor element mounting base, and the semiconductor element mounting base. The device includes a semiconductor element bonded to the through-hole portion of the element mounting base, a first bonding wire connecting the wiring conductor and the semiconductor element, and an external lead connected to the wiring conductor with a second bonding wire. A resin-sealed semiconductor device characterized by:
である請求項１記載の樹脂封止型半導体装置。2. The resin-sealed semiconductor device according to claim 1, wherein the insulating film is a polymer resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP188691A JPH04239161A (en) | 1991-01-11 | 1991-01-11 | Resin-sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP188691A JPH04239161A (en) | 1991-01-11 | 1991-01-11 | Resin-sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04239161A true JPH04239161A (en) | 1992-08-27 |
Family
ID=11514056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP188691A Pending JPH04239161A (en) | 1991-01-11 | 1991-01-11 | Resin-sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04239161A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334968A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Lead frame for semiconductor device |
| JPH02307253A (en) * | 1989-05-22 | 1990-12-20 | Nec Corp | Resin-sealed semiconductor device |
-
1991
- 1991-01-11 JP JP188691A patent/JPH04239161A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6334968A (en) * | 1986-07-29 | 1988-02-15 | Nec Corp | Lead frame for semiconductor device |
| JPH02307253A (en) * | 1989-05-22 | 1990-12-20 | Nec Corp | Resin-sealed semiconductor device |
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