JPH04237212A - Output buffer device - Google Patents

Abstract

PURPOSE:To attain a high speed and to allow the output buffer device to hardly cause an electromagnetic disturbance by suppressing an H level output in the H level output state so as to decrease a changing time from the H level output to an L level output. CONSTITUTION:The buffer device consists of 1st n-channel MOS transistors(TRs) 2,12 whose drains connect to a VDD power supply and whose sources connect to an output terminal and 2nd n-channel MOS TRs 3,13 whose drains connect to the said output terminal and whose sources connect to ground and also of output terminal final stage output circuits 4,14 inputting a signal whose polarity is inverted to a gate signal with respect to the 1st n-channel MOS TRs 2,12 to the gates of the 2nd n-channel MOS TRs 3,13.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TTL level interface output buffer device for a MOS type semiconductor integrated circuit device.

0002

2. Description of the Related Art Most large-scale integrated circuits are made of MOS type semiconductors, and among them, CMOS type semiconductor integrated circuits are most commonly used because they have features such as low power consumption.

On the other hand, some electronic components connected to semiconductor integrated circuits have CMOS level interfaces, but T
Many have TL level interfaces. Traditionally, CMO
The output buffer circuit of the TTL level interface output terminal of the S-type semiconductor integrated circuit is a CMO circuit as shown in FIG.
The same circuit configuration as the output buffer circuit for the S level interface was used.

In FIG. 5, reference numeral 22 denotes an H-level drive output stage p-channel MOS transistor, and 23 denotes an L-level drive output stage n-channel MOS transistor. FIG. 6 shows a schematic diagram of the output waveform of the output buffer circuit having the circuit configuration shown in FIG. In this FIG. 6, 24 is OUT
This is the output waveform of the terminal. In the conventional circuit, the L level output goes up to the GND (= 0V) level, and the H level output goes up to the VD level.
Full amplitude is achieved with respect to the power supply voltage up to the D (=5V) level.

[0005]

[Problem to be Solved by the Invention] In the output buffer circuit of this conventional circuit configuration, when driving an electronic component at the TTL level interface level as an external load, the time required for the output to change from H level to L level is That is, there was a problem that the output propagation delay time tpHL was large.

[0006] This means that the H level of the output is equal to the VDD level (
5V), whereas the input switching voltage at the TTL interface level is approximately 1.3V, which is a switching level that is considerably lower than the potential level of 1/2 of the power supply voltage. This is because the level output propagation delay time tpHL requires a change in the output terminal voltage (approximately 3.7 V) indicated by vHtoL in FIG.

Furthermore, if we try to reduce the L level output propagation delay time tpHL with this circuit configuration, the L level output propagation delay time tpHL will be reduced.
It is necessary to increase the driving capability of the level drive output stage n-channel MOS transistor and to increase the time rate of change of the output potential dvHtoL/dt when the output changes from the H level to the L level. However, increasing the time rate of change of the output not only increases the power supply noise level that occurs, but also increases the frequency of harmonic components included in the output waveform, which can prevent malfunctions of electronic equipment. This increases the energy of electromagnetic radiation that causes electromagnetic interference. Therefore, in the conventional circuit configuration, increasing the output change speed may cause electronic equipment equipped with this semiconductor integrated circuit to malfunction, and it has been difficult to drive the load of the TTL level interface at high speed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a TTL level interface output buffer device that is high-speed, less likely to cause electromagnetic interference, and has high reliability. .

[0009]

Means for Solving the Problems An output buffer device according to claim 1 of the present invention includes a first n-channel MOS element having a drain connected to a power source and a source connected to an output terminal, and a drain connected to the output terminal. an output terminal that inputs a signal whose polarity is inverted with respect to the gate signal of the first n-channel MOS element to the gate of the second n-channel MOS element; It has a final stage output circuit.

The output buffer device according to a second aspect of the present invention includes a first n-channel MOS element having a drain connected to a power source and a source connected to an output terminal, and a drain connected to the output terminal and a source connected to a ground. Under the condition that the output terminal side is high impedance, the gate signals of both the first and second n-channel MOS elements are controlled to L level,
Under the condition that the output terminal side is not high impedance,
the gate of the first n-channel MOS device and the second
The output terminal has a final stage output circuit in which the gates of the n-channel MOS devices are controlled by gate signals having mutually inverted polarities.

[0011]

According to the present invention, with the above configuration, the H level output amplitude in the H level output state can be suppressed, and the change time from the H level output to the L level output can be shortened.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an output buffer device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a push device configured using the present invention.
- This is a first embodiment of a pull type TTL level interface output buffer device. In the figure, 1 indicates an output buffer device, and this output buffer device 1 includes a first n-channel MOS element, e.g., an n-channel MOS transistor 2, whose drain is connected to a VDD power supply and whose source is connected to an output terminal. a second n-channel MOS element, for example, an n-channel MOS transistor 3, with the output terminal connected to and the source grounded;
A signal whose polarity is inverted with respect to the gate signal of the first n-channel MOS transistor 2 is sent to the second n-channel MOS transistor 2.
It has a final stage output circuit 4 whose output terminal is input to the gate of the S transistor 3.

The second n of this final stage output circuit 4
Three CMOS inverters 7 consisting of a P-channel MOS transistor 5 and an n-channel MOS transistor 6 are connected in series to the gate of the channel MOS transistor 3, and the input voltage is input to the leftmost CMOS inverter 7. . The output terminal of the leftmost CMOS inverter 7 and the gate of the first n-channel MOS transistor 2 are connected via a CMOS inverter 8.

FIG. 2 shows a second embodiment of a tri-state output type TTL level interface output buffer device constructed using the present invention. The output buffer device 11 of the second embodiment also has a first n
It has an output terminal final stage output circuit 14 consisting of a channel MOS transistor 12 and a second n-channel MOS transistor 13.

In the output buffer device 11 of the second embodiment, under the condition that the output terminal side is high impedance, the gate signals of both the first and second n-channel MOS transistors 12 and 13 go to L level. Under controlled conditions where the output terminal side is not high impedance,
The gate of the first n-channel MOS transistor 12 and the gate of the second n-channel MOS transistor 13 are controlled by gate signals having opposite polarities.

In both the output buffer devices 1 and 11 of the first embodiment and the second embodiment, the p-channel MOS transistor used in the H-level drive output stage in the conventional embodiment is replaced with an n-channel MOS transistor 2. , 12 to form an H level drive output stage.

Next, the operation of the final stage output circuit of the first embodiment and the second embodiment will be explained. FIG. 3A shows the potential of the substrate of the H level drive output stage n-channel MOS transistors 2 and 12 of the output buffer circuit to which the present invention is applied.
The circuit diagram at the D level, FIG. 3(B), shows the outline of the output waveform of the OUT terminal.

FIG. 4A shows the potential of the substrate (P-type well) of the H-level drive output stage n-channel MOS transistors 2 and 12 of the output buffer circuit to which the present invention is applied. The circuit diagram connected to the potential of FIG. 4B shows the outline of the output waveform of the OUT terminal.

In the circuit of FIG. 3A, in the H level output state, the potential of the gate G of the 2nd and 12th H level drive output stage n-channel MOS transistors is at the VDD level (=5V), and the potential of the source S is The difference voltage VGS from the potential is the threshold voltage VT which takes into account the substrate bias effect.
The H level output potential of the OUT terminal, which is the source, is determined by the potential equal to '(VT'> VT). Although the value of VT' varies depending on manufacturing conditions, it is approximately 1.8V. Therefore, the H level output is approximately 3.2V,
The potential difference (indicated by VHtOL in the figure) from the TTL interface switching voltage of 1.3V is approximately 1.9V. This is about 50 V compared to the difference potential of 3.7 V in the conventional embodiment.
% smaller. Therefore, the switching speed from H level to L level can be increased approximately twice as fast as the driving capability of the 3rd and 13th L level drive output stage n-channel MOS transistors as in the conventional embodiment. At the same time, the output amplitude is suppressed from 5V in the conventional embodiment to approximately 3.2V, so the energy of electromagnetic waves, which is proportional to the square of the amplitude, is significantly reduced in the device of the present invention, preventing electromagnetic interference. It is possible to suppress the occurrence of such problems.

In the circuit of FIG. 4A, since there is no potential difference between the substrate and source of the 2nd and 12th H level drive output stage n-channel MOS transistors, the threshold voltage is constant, and the H level output potential of the OUT terminal is VDD. The level will be lower than the level by VT. When VT = 0.7V, the output H level potential is 4.3V, and T
The difference voltage VHtOL from the TL interface switching voltage of 1.3V is 3.0V. Similar to the circuit shown in FIG. 3A, this circuit has the effect of increasing the switching speed and suppressing electromagnetic interference compared to the conventional embodiment.

Furthermore, in the circuit of FIG. 4(A),
Since there is no basic bias effect of the n-channel MOS transistors in the H-level drive output stage of 2 and 12, as shown in FIG.
This circuit has the advantage that the speed of change from L level output to H level output is faster than the above circuit.

[0023] Furthermore, the H level of the output is 4.3V,
CMOS level interface H level input standard 3
．． Since voltage margin is secured for 5V,
This output buffer device can also be applied as an output for a CMOS level interface, and has the same effect of increasing speed and suppressing electromagnetic interference as for the TTL interface level.

In applying the present invention, FIG. 3(A),
It is also possible to adopt either type of circuit configuration shown in FIG. Either circuit can be selected and used depending on the usage conditions.

[0025]

As described above, the output buffer circuit of the present invention has the advantage of being able to operate at high speed and being less likely to cause electromagnetic interference.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a push-pull type TTL level interface output buffer device of the present invention.

[Figure 2]
Circuit diagram of tri-state output type TTL level interface output buffer device of the present invention

FIG. 3 is a circuit diagram of the final stage output circuit of the output buffer device to which the present invention is applied;
And a schematic diagram of the output waveform of its OUT terminal

FIG. 4 is another circuit diagram of the final stage output circuit of the output buffer device to which the present invention is applied, and a schematic diagram of the output waveform of its OUT terminal.

[Figure 5] Circuit diagram of a conventional output buffer device

[Figure 6] Figure 5
Schematic diagram of the output waveform of the output buffer device

[Explanation of symbols]

1 Output buffer device 2 First n-channel MOS device 3 Second n-channel MOS device 4 Final stage output circuit 11 Output buffer device 12 First n-channel MOS device 13 Second n-channel MOS device 14 Final stage output circuit

Claims (2)

[Claims] 1. A first n-channel MOS element whose drain is connected to a power supply and whose source is connected to an output terminal; and a second n-channel MOS element whose drain is connected to the output terminal and whose source is grounded.
An output buffer device comprising an n-channel MOS device and having an output terminal final stage output circuit for inputting a signal whose polarity is inverted with respect to the gate signal of the first n-channel MOS device to the gate of the second n-channel MOS device. . 2. A first n-channel MOS element whose drain is connected to a power supply and whose source is connected to an output terminal; and a second n-channel MOS element whose drain is connected to the output terminal and whose source is grounded.
When the output terminal side is high impedance, the first and second
Under the condition that both gate signals of the n-channel MOS device are controlled to L level and the output terminal side is not set to high impedance, the gate of the first n-channel MOS device and the gate of the second n-channel MOS device are controlled to L level. An output buffer device having an output terminal and a final stage output circuit controlled by gate signals having mutually inverted polarities.