JPH04235428A - Method and circuit for phase fluctuation correction and data transmitter-receiver - Google Patents

Abstract

PURPOSE:To receive data without fail while allowing its phase fluctuation when the phase of the data from other data transmitter-receiver has large fluctuation. CONSTITUTION:Input data (a) are normally latched at a fall point of a clock signal (e) in a flip-flop (FF)1. When the large phase fluctuation occurs in the input data (a) while a FF7 is reset, the phase of the input clock (a) itself also largely fluctuates, the simultaneous occurrence of the differentiation result from respective differentiation circuits 2 and 3 is detected in a gate 6 and the FF7 is inversed. As a result, a inversed clock (i) can be obtained as the new clock signal (e) instead of an input clock (b) from a selector 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase fluctuation correction method and a phase fluctuation correction circuit in a data transmission/reception device, and also to a data transmission/reception device as the device itself. The present invention relates to a phase fluctuation correction method and a phase fluctuation correction circuit capable of receiving and processing received data while tolerating the phase fluctuation even when the phase of received data fluctuates significantly due to some cause, and further relates to a data transmitting/receiving device. It is something.

0002

2. Description of the Related Art Generally, a data transmitting/receiving device is provided with its own clock source, and based on a timing clock signal from that clock source, data received from other data transmitting/receiving devices is received and processed, and transmitted data is processed by other data transmitting/receiving devices. Most processes, such as data being transmitted to a data transmitting/receiving device, are performed in synchronization with the timing clock signal. By the way, when receiving data from another data transmitting/receiving device, a timing clock signal different from the timing clock signal from the clock source is first used for data reception. That is, depending on the timing signal extracted from data from another data transmitting/receiving device, the phase of a separately generated timing clock signal (the period is the same as the timing clock signal from the clock source) may be different from the clock signal and its timing signal. The received data is once latched by this phase-controlled timing clock signal, and then processed in a predetermined manner in synchronization with the timing clock signal from the clock source. It is something.

[0003] Regarding this type of technology, Japanese Patent Application Laid-Open No. 1983-63123 can be mentioned. In this case, while the input signal is delayed by each of multiple delay lines with different delay times, the relative phase difference between the input signal and the reference signal is detected. Depending on the relative phase difference obtained, either the input signal before delay or the plurality of delayed input signals is selected.

0004

[Problems to be Solved by the Invention] By the way, a problem when a data transmitting/receiving device receives data from another data transmitting/receiving device is that the phase of the data from the other data transmitting/receiving device varies over time due to jitter, etc. , and there are cases where it fluctuates significantly. The phase adjustment circuit disclosed in the above-mentioned publication is reasonably effective in dealing with such phase fluctuations, but due to the circuit configuration, analog delay means are used in addition to logic circuit elements. Therefore, the structure is inappropriate for implementing the entire structure into an LSI.

[0005] The first object of the present invention is to tolerate the phase fluctuations even if the phase of data from other data transmitting/receiving devices fluctuates variously and significantly over time due to jitter or the like. The present invention provides a phase variation correction method that can receive such data.

[0006] A second object of the present invention is to provide a method suitable for implementing the phase fluctuation correction method, and furthermore, to
The present invention provides a phase fluctuation correction circuit that is easy to implement.

[0007] A third object of the present invention is to tolerate the phase fluctuations even if the phase of data from other data transmitting/receiving devices fluctuates variously and significantly over time due to jitter or the like. The present invention provides a data transmitting/receiving device capable of receiving data.

[0008]

[Means for Solving the Problems] The first object is to provide a current timing clock signal extracted from serial reception data including jitter and a timing clock for data reception/transmission processing that is independently generated within the device. Whenever it is detected that the phase difference with the signal deviates from a certain range and there is no phase difference, at the time of detection, the current timing clock signal is replaced with a signal whose phase is 180 degrees from that signal. This is accomplished by selecting a different preliminary timing clock signal as the new working timing clock signal. The second purpose is to provide a selector that selectively outputs either a timing clock signal extracted from serial reception data including jitter or an inverted signal of that signal as a working timing clock signal, and a working timing clock from the selector. Rising (or falling) of the signal
a first differentiating circuit that detects the rising edge (or falling edge) of a timing clock signal for data reception/transmission processing that is generated independently within the device; a gate that logically ANDs the detection outputs from each of the two differentiating circuits in order to detect simultaneous appearance; This is achieved by providing at least a flip-flop in which is used as a selection control signal for the selector.

[0009] The third object is achieved by equipping an existing data transmitting/receiving device with a phase fluctuation correction circuit configured in this manner.

0010

[Operation] A timing signal extracted from serial data including jitter from another data transmitting/receiving device is phase-controlled, and a preliminary timing signal whose phase is 180 degrees different from that of the current timing clock signal for initial reception processing is obtained. A clock signal is created, and among these, the current timing clock signal is selectively output from the selector, and
It is designed to be used to latch data from other data transmitting/receiving devices. On the other hand, in parallel with the above operation, the rising edge (or falling edge) of the current timing clock signal is generated by the first differentiating circuit and by the data reception/transmission processing independently generated within the own device. The rising (or falling) of the timing clock signal is the second
They are detected by differentiating circuits, and the simultaneous appearance of these detection results is monitored by a gate. Now, there is originally a predetermined phase difference between the current timing clock signal and the timing clock signal for data reception/transmission processing, but if in this situation, data from other data transmitting/receiving devices If a large phase variation occurs in either direction, the first,
The simultaneous appearance of the detection results from the second differentiating circuit can be detected. If a simultaneous appearance is detected, that is, if the flip-flop for selector control is inverted every time it is detected that there is no phase difference between these timing clock signals, the current Instead of the timing clock signal, a preliminary timing clock signal whose phase is 180 degrees different from that signal is selected and outputted by the selector as a new working timing clock signal, and is used to latch received data from other data transmitting/receiving devices. It is meant to be used.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to FIGS. 1 to 3.

First, the data transmitting/receiving apparatus according to the present invention will be described. FIG. 1 shows a schematic configuration of a phase fluctuation correction circuit as a main part thereof. In this case, the input clock b in FIG. 1 is a timing clock signal for initial reception processing whose phase is controlled based on the timing signal extracted from the input data a from another data transmitting/receiving device, and the internal clock g is a timing clock signal for this data. Each corresponds to a timing clock signal for data reception and transmission processing that is generated independently within the transmitting and receiving device. By processing these input clock b and internal clock g in a predetermined manner, even if the phase of input data a from other data transmitting/receiving devices fluctuates widely over time due to jitter, etc., The input data a is latched by a D-type flip-flop (hereinafter referred to as FF) 1 while allowing phase fluctuations. FIG. 2 also shows the input/output signal waveforms at each of the main parts in FIG. 1 in the case where there is no large phase variation in the input data a from another data device. The circuit configuration shown in FIG. 1 and its operation will be described below with reference to FIG. 2.

That is, FF7 for controlling the selector 4
In the normal state, the input clock b is passed through the selector 4 and is differentiated as the current timing clock signal e by the current clock differentiation circuit 2, and the current clock differentiation circuit 2 outputs the current clock differential signal f. is now available. On the other hand, the internal clock g is also differentiated by the internal clock differentiating circuit 3, so that the internal clock differentiating circuit 3 can obtain an internal clock differentiating signal h. As can be seen from FIG. 2, in this example, the rising edge of the clock is detected by differentiation, but it goes without saying that the falling edge may also be detected. Further, the current clock differentiating circuit 2 and the internal clock differentiating circuit 3 have the same configuration, and are easily constructed from pure gates (delay gates, exclusive OR gates, AND gates, etc.).

Now, whether or not the current clock differential signal f and the internal clock differential signal h have the same phase relationship is detected by the AND gate 6, but in the normal state, the input clock b and the internal clock differential signal The phase relationship of the clock g is approximately 180 degrees out of phase, so the current clock differential signal f and the internal clock differential signal h are connected to the AND gate 6.
Even if they are ANDed, a signal indicating the simultaneous appearance of these signals f and h is not obtained as an AND gate output from the AND gate 6, and the FF 7 remains in the reset state. In this state, input data a is selected by selector 4.
At the falling edge of the current timing clock signal e from the input clock b, that is, the input clock b is latched into the FF1, and output data is obtained from its Q output.

The above is the operation when there is no large phase variation in the input data a, but FIG. 3 shows each of the main parts in FIG. 1 when the input data a has a large phase variation. This shows the input/output signal waveforms at . The operation up to the middle is the same as that shown in FIG. 2, but if a large phase change occurs in the input data a,
The inverted input clock i is selected as the current timing clock signal e from.

That is, the inverted input clock i is obtained by inverting the input clock b by the inverter 5 and is input to the selector 4, but in the normal state, the input clock a is input from the selector 4. As already mentioned, it is obtained as the current timing clock signal e. However, if it is assumed that a large phase variation occurs in the input data a in such a state, it is clear that the phase of the input clock a itself will also vary greatly in order to follow the phase variation. When the magnitude of the phase fluctuation approaches approximately 180 degrees, the current clock differential signal f and the internal clock differential signal h appear simultaneously, and this simultaneous appearance is detected by the AND gate 6, and based on the detection result, the FF 7 is In other words, it is reversed to the set state. When FF7 is inverted, its Q
Since the selector 4 is selectively controlled by the output d, the inverted input clock i is obtained as the current timing clock signal e from the selector 4 in place of the input clock a, and its rising phase is compared with that of the internal clock g and is monitored. In this state, the input data a is latched by the FF 1 at the falling edge of the current timing clock signal e from the selector 4, that is, the inverted input clock i, and output data is obtained from the Q output d. If a large phase fluctuation occurs in the input data a in such a state, FF7
is inverted again and restored to its original state, in preparation for large phase fluctuations in the input data a.

[0017]

As explained above, in the case according to claim 1, even when the phase of data from another data transmitting/receiving device varies widely and significantly over time due to jitter, etc. The data can be received while allowing the phase fluctuation, and in the case according to claim 2, the phase fluctuation is suitable for implementing the phase fluctuation correction method, and furthermore, the phase fluctuation can be easily integrated into an LSI. According to claim 3, the fluctuation correction circuit further allows for the phase fluctuation even if the phase of data from another data transmitting/receiving device fluctuates variously and significantly over time due to jitter or the like. Thus, a data transmitting/receiving device capable of receiving the data can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of an example of a phase fluctuation correction circuit as a main part of a data transmitting/receiving device according to the present invention.

FIG. 2 is a diagram showing input/output signal waveforms at each of the main parts in FIG. 1 when no large phase fluctuation occurs in input data from other data devices.

FIG. 3 is a diagram showing input/output signal waveforms at each of the main parts in FIG. 1 when no large phase fluctuation occurs in input data from other data devices.

[Explanation of symbols]

1 D type flip-flop (FF) 2
Current clock differentiation circuit 3 Internal clock differentiation circuit 4 Selector 5 Inverter 6 AND gate

Claims (3)

[Claims] Claim 1: The phase difference between the current timing clock signal extracted and created from serial reception data containing jitter and the timing clock signal for data reception and transmission processing that is generated independently within the device is constant. Each time it is detected that the phase difference deviates from the range of
At the time of detection, a preliminary timing clock signal having a phase difference of 180 degrees from the current timing clock signal is selected as a new current timing clock signal instead of the current timing clock signal. 2. A selector that selectively outputs either a timing clock signal extracted and created from serial received data containing jitter or an inverted signal of the signal as a working timing clock signal, and a working timing clock from the selector. A first differentiating circuit detects the rising edge (or falling edge) of a signal, and a second differential circuit detects the rising edge (or falling edge) of a timing clock signal for data reception and transmission processing that is generated independently within the device. a differentiating circuit, a gate for ANDing the detection outputs from each of the first and second differentiating circuits in order to detect the simultaneous appearance of the detection outputs, and the degree to which an AND output indicating the simultaneous appearance can be obtained from the gate. A phase fluctuation correction circuit comprising at least a flip-flop which is placed in an inverted state and whose output is used as a selection control signal for the selector. 3. A selector that selectively outputs either a timing clock signal extracted and created from serial received data including jitter or an inverted signal of the signal as a working timing clock signal, and a working timing clock from the selector. A first differentiating circuit detects the rising edge (or falling edge) of a signal, and a second differential circuit detects the rising edge (or falling edge) of a timing clock signal for data reception and transmission processing that is generated independently within the device. a differentiating circuit, a gate for ANDing the detection outputs from each of the first and second differentiating circuits in order to detect the simultaneous appearance of the detection outputs, and the degree to which an AND output indicating the simultaneous appearance can be obtained from the gate. A data transmitting/receiving device comprising a phase fluctuation correction circuit including at least a flip-flop which is placed in an inverted state and whose output is used as a selection control signal for the selector.