JPH0423401B2 - - Google Patents
Info
- Publication number
- JPH0423401B2 JPH0423401B2 JP62234907A JP23490787A JPH0423401B2 JP H0423401 B2 JPH0423401 B2 JP H0423401B2 JP 62234907 A JP62234907 A JP 62234907A JP 23490787 A JP23490787 A JP 23490787A JP H0423401 B2 JPH0423401 B2 JP H0423401B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- sio
- nonlinear
- amorphous film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000005476 soldering Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000001552 radio frequency sputter deposition Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Thermistors And Varistors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野】
本発明は、サーミスタ、又はバリスタなどとし
て使用される非線形抵抗体の電極のハンダ付けの
際の表面保護構造を付与した非線形抵抗体の電極
の形成方法に関するものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a nonlinear resistor electrode used as a thermistor, a varistor, etc., provided with a surface protection structure during soldering. This relates to a forming method.
従来の非線形抵抗体の製作においては、電極を
付与する場合に、Agガラスフリツトのペースト
を塗布し、乾燥し、焼付けを行うか、またはNi
メツキして非線形抵抗体の電極を形成し、これに
リード線をカシメ、または、はんだ付けし、この
リード線を付けたものの全面に樹脂コーテイング
している。
In the conventional fabrication of nonlinear resistors, when applying electrodes, a paste of Ag glass frit is applied, dried, and baked, or a paste of Ni glass frit is applied, dried, and baked.
Electrodes of the nonlinear resistor are formed by plating, lead wires are caulked or soldered to this, and the entire surface of the object to which the lead wires are attached is coated with resin.
サーミスタやバリスタなどに使用される従来の
非線形抵抗体は、はんだ付けを終了したものに樹
脂コーテイングしただけである。したがつて、製
造工程中にはんだ付け用のフラツクスなどにより
非線形抵抗焼結体の一部が還元されると、非線形
抵抗焼結体の特性が変化し、製造目的とする非線
形抵抗製品特性の値にならず、製品歩留りが低下
する。
Conventional nonlinear resistors used in thermistors, varistors, etc. are simply coated with resin after soldering. Therefore, if a part of the nonlinear resistance sintered body is reduced by soldering flux during the manufacturing process, the characteristics of the nonlinear resistance sintered body will change, and the values of the nonlinear resistance product characteristics that are intended for manufacturing will change. This results in lower product yields.
また、樹脂コーテイングでは、その樹脂コーテ
イングの耐蝕性、耐久性が低いので、実使用環境
条件が制約される。 Furthermore, since the resin coating has low corrosion resistance and durability, the actual usage environmental conditions are restricted.
本発明は上記の問題点を解決するためになされ
たもので、SiO2、SiO、Si3N4、SiO2-xNx、
Al2O3、TiO2、Ta2O5からなる群のうちの１種以
上の耐熱性無機絶縁性のアモルフアス膜で表面を
50nｍ〜1μｍの厚さに電極形成部を除いて被保護
部となる部分を被覆、または電極形成部と被保護
部となる部分を含めて全面を被覆した後に電極形
成部の前記アモルフアス膜をエツチングで除去し
た後、アモルフアス部で被覆されていない前記電
極形成部に電極を形成したものである。
The present invention was made to solve the above-mentioned problems, and includes SiO 2 , SiO, Si 3 N 4 , SiO 2-x N x ,
The surface is coated with a heat-resistant inorganic insulating amorphous film of one or more of the group consisting of Al 2 O 3 , TiO 2 , and Ta 2 O 5 .
The amorphous film on the electrode forming area is etched after coating the protected area excluding the electrode forming area to a thickness of 50 nm to 1 μm, or coating the entire surface including the electrode forming area and the protected area. After removing the amorphous portion, an electrode is formed on the electrode forming portion that is not covered with the amorphous portion.
本発明による非線形抵抗体は、非線形抵抗焼結
体がダイシングされたチツプの状態のときから表
面の被保護部が耐熱性無機絶縁性のアモルフアス
膜で被覆されているから、はんだ付け工程におい
ても還元作用により非線形抵抗特性に悪影響を及
ぼすようなこともなく、また、使用状態において
も耐蝕性も耐久性も良好となる。
In the nonlinear resistor according to the present invention, since the surface to be protected is coated with a heat-resistant inorganic insulating amorphous film even when the nonlinear resistance sintered body is in the state of a diced chip, it can be reduced even during the soldering process. The action does not adversely affect the nonlinear resistance characteristics, and the corrosion resistance and durability are also good even under use.
耐熱性無機絶縁性のアモルフアス膜の厚さが
50nｍよりも薄いと耐蝕性および耐久性が悪くな
り、1μｍよりも厚くなると膜にクラツクが入り
易くなるとともに、膜形成に要する時間が莫大な
ものになり不経済である。 The thickness of the heat-resistant inorganic insulating amorphous film is
If it is thinner than 50 nm, the corrosion resistance and durability will deteriorate, and if it is thicker than 1 μm, cracks will easily occur in the film, and the time required for film formation will be enormous, which is uneconomical.
第１図は電極を付した本発明にかゝる非線形抵
抗体の拡大斜視図で、１はチツプに分割された非
線形抵抗体、２は厚さ50nｍ〜1μｍのSiO2からな
る耐熱性無機絶縁性アモルフアス膜、３，４は電
極である。
Figure 1 is an enlarged perspective view of a nonlinear resistor according to the present invention with electrodes attached, where 1 is a nonlinear resistor divided into chips, and 2 is a heat-resistant inorganic insulator made of SiO 2 with a thickness of 50 nm to 1 μm. 3 and 4 are electrodes.
この第１図に示される製品は次の手順で製作さ
れる。 The product shown in FIG. 1 is manufactured by the following procedure.
先ず非線形抵抗体てあるサーミスタ焼結体を目
的製品に応じて0.5〜10mmの厚さにスライスして
ウエハー状にする。 First, the thermistor sintered body, which is a nonlinear resistor, is sliced into wafers with a thickness of 0.5 to 10 mm depending on the intended product.
このウエハー状のサーミスタ焼結体１の表面
に、SiO2、SiO、Si3N4、SiO2-xNx、Al2O3、
TiO2、Ta2O5からなる群のうちの１種以上の耐
熱性無機絶縁性のアモルフアス膜２、実施例では
SiO2膜を50nｍ〜1μｍの厚さにRFスパツタリン
グ、低温CVDなどで条件をコントロールして被
覆する（第２図１図示）
次に電極を形成しようとする箇所をエツチング
により除去し（第２図２図示）その耐熱性無機絶
縁性のアモルフアス膜２で被覆されていない箇所
に、Ni、Al、Ti、Pt、Au、Ag、Pd、Ta、Cu
のいづれかの金属でスパツタリング、メツキ、ま
たは蒸着により電極３，４を形成する。 On the surface of this wafer-shaped thermistor sintered body 1, SiO 2 , SiO, Si 3 N 4 , SiO 2-x N x , Al 2 O 3 ,
In the example, a heat-resistant inorganic insulating amorphous film 2 of one or more of the group consisting of TiO 2 and Ta 2 O 5
A SiO 2 film is coated to a thickness of 50 nm to 1 μm using RF sputtering, low-temperature CVD, etc. under controlled conditions (see Figure 2). Next, the area where the electrode is to be formed is removed by etching (see Figure 2). 2) Ni, Al, Ti, Pt, Au, Ag, Pd, Ta, Cu
The electrodes 3 and 4 are formed of any one of these metals by sputtering, plating, or vapor deposition.
なお、第２図２に示すように電極を形成しよう
とする箇所を除いて耐熱性無機絶縁性のアモルフ
アス膜を形成する方法を採つてもよい。 Incidentally, as shown in FIG. 2, a method may be adopted in which a heat-resistant inorganic insulating amorphous film is formed except for the area where the electrode is to be formed.
この耐熱性無機絶縁性のアモルフアス膜２で被
覆され、電極３，４が形成されているウエハー状
のーミスタ焼結体素材１をサーミスタ製品寸法に
切断し、これにリード線（図示せず）をカシメ、
または、はんだ付けして製品とするか、または、
さらにそ上に樹脂コーテイングを施す。 The wafer-shaped -mister sintered body material 1 covered with this heat-resistant inorganic insulating amorphous film 2 and on which the electrodes 3 and 4 are formed is cut into the dimensions of the thermistor product, and a lead wire (not shown) is connected to it. caulking,
Or solder it into a product, or
Furthermore, a resin coating is applied on top.
改良の効果を見るために、アモルフアス膜２を
付けた本発明の製造方法によるチツプと、アモル
フアス膜２のない従来の製造方法によるチツプ
を、スライスした20mm×20mm×0.3mmの同じ負の
温度特性を持つ非線形抵抗焼結体基板上に形成
し、ダイシングソーによつて分割した。 In order to see the effect of the improvement, a chip manufactured by the manufacturing method of the present invention with the amorphous amorphous film 2 and a chip manufactured by the conventional manufacturing method without the amorphous film 2 were sliced into 20 mm x 20 mm x 0.3 mm chips with the same negative temperature characteristics. It was formed on a nonlinear resistance sintered substrate with a sintered body and divided using a dicing saw.
この試験のために用意した試験チツプの形状は
第１図と類似しており、１mm×１mm×0.3mmで中
心に配置した電極３は直径が0.3mm、厚さ2μｍで
メタルマスクを用いて真空蒸着されたニツケルで
あり、電極４は同様に厚さ2μｍの全面蒸着され
たニツケルである。 The shape of the test chip prepared for this test is similar to that shown in Figure 1, and the electrode 3, which is 1 mm x 1 mm x 0.3 mm and placed in the center, has a diameter of 0.3 mm and a thickness of 2 μm, and is placed under vacuum using a metal mask. The electrode 4 is also made of nickel which is deposited on the entire surface with a thickness of 2 μm.
アモルフアス膜２は蒸気基板に第２図１の様に
真空度10-2mmHgのアルゴン中で石英板をターゲ
ツトに、13.56MHz・350Wの高周波電力を印加
し、室温の基板上にRFスパツタリング法によつ
てSiO2を0.1μｍの厚さに堆積させて形成した。こ
の時、従来技術を代表する部分の全面と新技術を
代表する部分の中心電極部分にアモルフアス膜が
堆積せぬように、あらかじめ水溶性のインクを印
刷・乾燥し保護した。これは、本発明でエツチン
グを用いてアモルフアス膜の不要部分を除去する
ものと異なるが、エツチング液によつて従来技術
を代表する部分の表面が変質し、比較を困難にす
ることを避けるための処置である。このあと、純
水洗浄によつて上記インクを剥離した後、電極
３，４を形成した。 The amorphous film 2 is produced by applying high frequency power of 13.56 MHz and 350 W to a quartz plate in argon at a vacuum degree of 10 -2 mmHg as shown in Fig. 1, and then applying RF sputtering to the substrate at room temperature. It was formed by depositing SiO 2 to a thickness of 0.1 μm. At this time, water-soluble ink was printed and dried in advance to protect the entire surface of the part representing the conventional technology and the center electrode part of the part representing the new technology to prevent an amorphous film from accumulating. This is different from the present invention, which uses etching to remove unnecessary parts of the amorphous film, but it is necessary to avoid the etching solution from altering the surface of the parts typical of the prior art, making comparison difficult. It is a treatment. Thereafter, the ink was removed by washing with pure water, and then electrodes 3 and 4 were formed.
従来技術を代表するものおよび本発明による新
技術を代表するチツプを各５個ずつ選別し室温か
ら150℃までの範囲で抵抗値の温度依存性を測定
し記録した。 Five chips representing the conventional technology and five chips representing the new technology of the present invention were selected, and the temperature dependence of the resistance value was measured and recorded in the range from room temperature to 150°C.
この後、前記チツプを260℃・10秒間、ハンダ
中に浸漬し再度特性を測定し、比較を行つた。従
来技術を代表するチツプは１桁から２桁の範囲で
室温の抵抗値が低下し、初期には負の大きな温度
係数を持つていたものが全て小さな正の温度係数
を示すようになつた。一方、本発明を代表するチ
ツプは、室温抵抗値、温度係数とも測定誤差内で
初期値からの変化が認められなかつた。劣化した
従来技術によるチツプは150℃の高温空気中放置
で１週間後に初期値の1/2程度迄、室温抵抗値が
回復した。また、これらの著しく劣化したチツプ
はニツケル電極３の周辺をサンドブラストによつ
て研磨することによつて初期値の95％迄回復し
た。以上から保護されていない表面がハンダ処理
により還元されて焼結体内部よりも低い抵抗値と
なつたことが分かる。 Thereafter, the chips were immersed in solder at 260°C for 10 seconds, and the characteristics were again measured and compared. The resistance of chips representing the prior art at room temperature has decreased by one to two digits, and all chips that initially had large negative temperature coefficients now have small positive temperature coefficients. On the other hand, in the chip representing the present invention, no change from the initial value was observed in both the room temperature resistance value and the temperature coefficient within the measurement error. When chips made using the conventional technology had deteriorated and were left in high-temperature air at 150°C, the room temperature resistance value recovered to about half of its initial value after one week. Moreover, these significantly deteriorated chips were restored to 95% of their initial value by polishing the periphery of the nickel electrode 3 by sandblasting. It can be seen from the above that the unprotected surface was reduced by the soldering process and had a lower resistance value than the inside of the sintered body.
本発明によるチツプはその後、真空中200℃・
1000時間の高温放置や125℃・２気圧・100時間の
プレツシヤークツカー試験においても測定誤差内
の変動に留まつた。 The chip according to the invention is then heated at 200°C in vacuum.
Even after 1000 hours of high temperature storage and 100 hours of pressure testing at 125°C and 2 atm, the fluctuations remained within the measurement error.
本発明を代表させた前記チツプにおいても、ア
モルフアス膜２によつておおわれていない非線形
抵抗焼結体チツプ側面は上記と同様にハンダ処理
によつて還元され、焼結体内部と異なり、低い抵
抗率を持つ表面層に変質していることが、４端子
プローブ法による測定から判明した。しかしなが
ら、電極３からアモルフアス膜２に沿つて側面に
いたる導電路は還元雰囲気から守られて内部と同
じ高抵抗率のままであり、その導電路の全抵抗値
への寄与は極めて少ないので、この場合側面をア
モルフアス膜で保護する必要はなく、製造方法は
複雑化しない。 Also in the chip representing the present invention, the side surface of the nonlinear resistance sintered chip that is not covered with the amorphous film 2 is reduced by the soldering process as described above, and has a low resistivity, unlike the inside of the sintered body. It was found from measurements using the four-terminal probe method that the surface layer had changed in quality. However, the conductive path from the electrode 3 to the side surface along the amorphous film 2 is protected from the reducing atmosphere and remains at the same high resistivity as the inside, and its contribution to the total resistance is extremely small. In this case, there is no need to protect the sides with an amorphous film, and the manufacturing method is not complicated.
上記の例で使用した非線形抵抗焼結体チツプの
焼結密度は約95％、表面荒さは平均2μｍ程度の
荒いものであつた。このような粗面にスパツタリ
ングされた0.1μｍの薄膜は焼結体表面を均一に覆
うことはない。薄膜抵抗や厚膜抵抗の保護膜とし
て本発明で用いたと同様な成分の薄膜を用いるこ
とは良く知られている。しかし、これらは活性な
抵抗体前部をピンホール無しに被覆することが要
点であり、これに対し本発明は多くのピンホール
を許容する製造方法である。また、上記の例で示
した如く、必要部分のみを被覆することに特徴が
ある。 The sintered density of the nonlinear resistance sintered chip used in the above example was approximately 95%, and the surface roughness was approximately 2 μm on average. A thin film of 0.1 μm sputtered on such a rough surface does not uniformly cover the surface of the sintered body. It is well known that a thin film having the same components as those used in the present invention is used as a protective film for a thin film resistor or a thick film resistor. However, the key to these is to cover the active resistor front without pinholes, whereas the present invention is a fabrication method that tolerates many pinholes. Further, as shown in the above example, the method is characterized in that only necessary parts are covered.
前記の比較実験や耐久試験条件は、非線形抵抗
焼結体全体を樹脂で被覆する従来技術が耐えられ
ないレベルを本発明がクリアしていることを示す
ものである。遥かに高い信頼性と、より生産性の
高い広範な実装技術に適合した非線形抵抗焼結体
チツプを経済的に製造する手段を提供できる利点
を持つ。 The comparative experiments and durability test conditions described above demonstrate that the present invention has cleared the level that the conventional technology of coating the entire nonlinear resistance sintered body with resin cannot withstand. It has the advantage of providing a means to economically manufacture nonlinear resistance sintered chips that are much more reliable and compatible with a wider range of packaging techniques that are more productive.
本発明による非線形抵抗体は非線形抵抗焼結体
がスライスされたチツプの状態の時から表面の被
保護部が耐熱性無機絶縁性のアモルフアス膜２で
被覆されているから、ハンダ付け工程においてフ
ラツクスなどによる還元作用により非線形抵抗特
性に悪影響を及ぼすようなことはない。
In the nonlinear resistor according to the present invention, since the surface to be protected is covered with a heat-resistant inorganic insulating amorphous film 2 from the time when the nonlinear resistance sintered body is in the state of a sliced chip, flux etc. The reduction effect caused by this does not adversely affect the nonlinear resistance characteristics.
以上のように、本発明の表面保護構造を付与す
る電極の形成方法は使用状態においても耐蝕性も
耐久性も良好となるという利点もあり、本発明は
産業の発達に寄与するところ極めて大なるものが
ある。 As described above, the method of forming an electrode provided with a surface protection structure according to the present invention has the advantage that it has good corrosion resistance and durability even when in use, and the present invention will greatly contribute to the development of industry. There is something.
第１図は本発明にかゝる非線形抵抗体の斜視
図、第２図はその製造を示す説明図である。
１……非線形抵抗体、２……アモルフアス、３
及び４……電極。
FIG. 1 is a perspective view of a nonlinear resistor according to the present invention, and FIG. 2 is an explanatory view showing its manufacture. 1...Nonlinear resistor, 2...Amorphous, 3
and 4...electrode.
Claims (1)
TiO2、Ta2O5からなる群のうちの１種以上の耐
熱性無機絶縁性のアモルフアス膜で表面を50nｍ
〜1μｍの厚さに電極形成部を除いて被保護部と
なる部分を被覆、または電極形成部と被保護部と
なる部分を含めて全面を被覆した後に電極形成部
の前記アモルフアス膜をエツチングで除去した
後、アモルフアス部で被覆されていない前記電極
形成部に電極を形成することを特徴とする非線形
抵抗体の電極の形成方法。1 SiO 2 , SiO, Si 3 N 4 , SiO 2-x N x , Al 2 O 3 ,
The surface is coated with a heat-resistant inorganic insulating amorphous film of one or more types from the group consisting of TiO 2 and Ta 2 O 5 to a thickness of 50 nm.
The amorphous film on the electrode forming part is coated with a thickness of ~1 μm to cover the area to be protected except for the electrode forming area, or the entire surface including the electrode forming area and the protected area is etched. A method for forming an electrode of a nonlinear resistor, comprising forming an electrode on the electrode forming portion that is not covered with the amorphous portion after removing the amorphous portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62234907A JPS6480002A (en) | 1987-09-21 | 1987-09-21 | Nonlinear resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62234907A JPS6480002A (en) | 1987-09-21 | 1987-09-21 | Nonlinear resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6480002A JPS6480002A (en) | 1989-03-24 |
| JPH0423401B2 true JPH0423401B2 (en) | 1992-04-22 |
Family
ID=16978163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62234907A Granted JPS6480002A (en) | 1987-09-21 | 1987-09-21 | Nonlinear resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6480002A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2800341B2 (en) * | 1990-01-19 | 1998-09-21 | 松下電器産業株式会社 | Method for manufacturing voltage non-linear resistor element |
| JP2560891B2 (en) * | 1990-07-09 | 1996-12-04 | 株式会社村田製作所 | Varistor manufacturing method |
| US5569495A (en) * | 1995-05-16 | 1996-10-29 | Raychem Corporation | Method of making varistor chip with etching to remove damaged surfaces |
| JP5413600B2 (en) * | 2010-03-17 | 2014-02-12 | 三菱マテリアル株式会社 | THERMISTOR ELEMENT AND MANUFACTURING METHOD THEREOF |
| CN113257503B (en) * | 2021-05-13 | 2023-01-03 | 中国科学院新疆理化技术研究所 | All-inorganic flexible thermosensitive device and preparation method thereof |
| WO2023140054A1 (en) * | 2022-01-19 | 2023-07-27 | 三菱マテリアル株式会社 | Thermistor element and method for manufacturing same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5013868A (en) * | 1973-06-12 | 1975-02-13 | ||
| JPS61181104A (en) * | 1985-02-06 | 1986-08-13 | シャープ株式会社 | Platinum temperature measuring resistor |
| JPS6335084A (en) * | 1986-07-30 | 1988-02-15 | Toshiba Corp | Processing circuit for multiple system color television signal |
-
1987
- 1987-09-21 JP JP62234907A patent/JPS6480002A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5013868A (en) * | 1973-06-12 | 1975-02-13 | ||
| JPS61181104A (en) * | 1985-02-06 | 1986-08-13 | シャープ株式会社 | Platinum temperature measuring resistor |
| JPS6335084A (en) * | 1986-07-30 | 1988-02-15 | Toshiba Corp | Processing circuit for multiple system color television signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6480002A (en) | 1989-03-24 |
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