JPH0423062A - Method and device for arbitration of digital data processor - Google Patents

Abstract

PURPOSE:To improve the availability at a high speed and to access with the subject method and device by reading the data out of a common memory and writing the data in a decided and selected reading pipeline register before the end of the pipeline cycle. CONSTITUTION:When the selected processors 9 - 12 try to write the data, each request flag is selected by an arbitration circuit 20. The same time, the results of selection are supplied to an address selector 16, a write data selector 17, and a selector circuit of a write flag signal pipeline register 19. Then an address pipeline register 2, a data pipeline register 4, and a write flag signal pipeline register 8 of each processor are selected. The data are written into a shared memory 25.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is for arbitrating between processors when digital data processing units (hereinafter referred to as processors) that access shared memory in a single memory space are driven in parallel. The present invention relates to a digital data processing unit adjusting device.

2. Description of the Related Art When multiple processors access shared memory, exclusive control is naturally required. The conventional method normally used at this time is to give bus occupancy to that processor and use DM.
A (direct memory access) transfer, etc. was common. For example, a processor assigned a certain priority generates an interrupt, stops the CPU, acquires a bus, and then performs a burst transfer. An example is when data read from a hard disk is written to memory via a bus. This method is often used in normal microcomputer systems, and it improves the apparent bus usage efficiency because the wasted time from the first interrupt to bus acquisition is offset by the efficiency of continuous transfer. ”- can be made.

Problems to be Solved by the Invention In cases where each processor does not have a buffer memory, there is a method called cycle stealing, which detects bus availability and exchanges data. This is typically used for low-speed data transfers, each time repeating the process of interrupting and acquiring the bus to transfer small units of data.

Problems to be Solved by the Invention However, with the conventional method of mounting buffer memory on each processor, it is difficult to achieve high-speed processing by incorporating multiple processors into one LSI chip. , there is a problem of hardware increase in that each processor requires a certain amount of buffer memory.

In addition, in order to make maximum use of hardware resources for parallel processing, inefficiencies such as ordinary parsing (DMA) and cycle stealing must be avoided. In other words, with the conventional method, there was a problem in that it was not possible to satisfy both bus efficiency and hardware amount at the same time.

In view of these problems, the present invention provides an efficient and high-speed mutual exclusive access to the shared memory while each processor shares the external memory in the 1st, 81st, etc. in which a plurality of internal processors are built into one chip. It is an object of the present invention to provide a digital data processing unit arbitration device that can perform arbitration with little increase in hardware.

Means for Solving the Problems In the present invention, at least each of a plurality of processors is provided with a request flag indicating that access to a shared memory is requested, a shared memory address holding pipeline register to be accessed, and a write data pipeline register. (at the time of writing), a read data pipeline register (at the time of reading), and a write flag signal pipeline register indicating whether it is a write or a read, and the request flags of each processor are made to compete with each other using the synchronized clock for pipeline processing. The priority of the processors is determined using the synchronous clock, and the shared memory address, write data, and write flag signal of the determined selected processor are outputted to the pipeline using a synchronous clock at the time of d write, and the shared memory address bus is sent to the shared memory address bus in the next pipeline cycle. and the data bus and write signal line (R/W), and when reading, the shared memory address and read/write flag signal are sent to the shared memory address bus, data bus, and write signal line (R/W) in the next pipeline cycle using a synchronous clock. R/W), reads data from the shared memory, and writes it to the read pipeline register of the selected block by the end of the pipeline cycle.

That is, for example, at the time of write 37, the data to be written by the processor whose request flag is active among the processors, the address of the shared memory to be written, and information on whether to write or read are sent to the respective write data pipelines. The register, the 7-trace pipeline register, and the write flag signal are written to the pipeline register and supplied to the data bus, address bus, and write input terminal of the shared memory, respectively, in the next pipeline cycle.

Also, at least multiple processors each/? , a request flag indicating that the processor() is requesting access to shared memory, an address register to hold the atrus, a read data register (when writing), and a first read data pipe. A line register (when reading) and a write flag indicating whether to write or read are prepared, and the request flags of each processor are made to compete with each other using a synchronized clock to determine the priority of the processor. ! When writing in the pipeline cycle of the II clock, Riko decides to write the contents of the address register of the selected processor to the address pipeline register, writes the contents of the write data register to the data pipeline register, and writes the contents of the write flag signal. After that, in the next pipeline cycle, the output of the address pipeline register L, the contents of the data bus pipeline register, and the write flag signal pipeline register are stored in the address of one memory. It is applied to the bus, data bus, and write signal line (R/W), and at the time of reading, the request flags of each processor are made to compete with each other using a synchronous clock to determine the priority of the processor, and at the same time, the pipeline of the synchronous clock is When writing to a cycle, the contents of the address register of the selected processor are stored in the address pipeline register, and the contents of the write flag signal indicating a read are stored in the write flag signal pipeline register, and then in the next pipeline cycle. The output of the address pipeline register and the contents of the write flag signal pipeline register described above are applied to the address bus, data bus, and write signal line (R/W) of the shared memory, respectively, by the end of the pipeline cycle of this synchronous clock. The data on the data bus just read from the shared memory is latched into a second read data pipeline register.

The contents of this second read data pipeline register are determined and written to the first read data pipeline register of the selected processor when a read request is made in the next pipeline cycle. In both the first means and the second means, if each processor has only a single function of writing or reading, the corresponding register is omitted and the write flag signal is set to a fixed value.

In addition, when multiple processors compete to access shared memory, the processor with the lowest priority is assigned to a device that performs an interface for data transfer, etc. of the host computer, and at that time, that interface is connected to the host computer by using a FIFO register. and F
By detecting the storage state of data in the IFO register, if the contents of the FIFO register become nearly empty during transfer to the host computer, or if the contents of the FIFO register are almost full during transfer to the host computer, By detecting this and increasing the priority previously given to the processor that performs the interface from the lowest to the highest, the processing speed seen from the outside can be increased, albeit apparently.

In addition, when multiple processors compete to access shared memory, each processor is provided with a memory management mechanism, and if each processor accesses only a separate fixed range of areas within each shared memory, processors can mutually control each other. When two or more processors access the same fixed range of memory at the same time, in addition to determining the priority of conflicts between processing units, some processors Processing areas that stop shared memory access or access each other in Bromo-Sosa 1111
It is possible to further improve the bus access efficiency by providing means for processing either of the two signals first.

Furthermore, in each of the above means, if the predetermined priority of each processor is not the lowest, the processing procedure is predetermined so that the request flag is not activated every pipeline clock. This can prevent other processors from suspending processing for an extremely long time due to waiting for access.

Effect of the Invention With the above-described configuration, the present invention selects one of the plurality of digital data processors for each memory cycle time of the shared memory based on the request flag and priority of each processor. At this time, the address pipeline register of each processor requesting access to the shared memory contains the pipelined address, and the write flag pipeline register contains a write flag that identifies whether the operation is a pipelined read or write operation. Each signal is output. Then, the address and R/W signal of the selected processor are supplied to the shared memory address line and the 1 (/W line) every memory cycle.

At the same time, if the write flag signal at the time when the selected request flag is accepted is a write operation, it will be sent from the write data pipeline register, and if it is a read operation, it will be sent from the read pipeline register of each processor. A write or read operation is performed on each register input to the shared memory. In this way, the memory to be accessed is determined for a given clock cycle, or in other words, for each memory cycle, and at the same time it is determined whether the access is a write or a read. Naturally, when a large number of processors issue requests at the same time, memory access is waited for according to the priority assigned to each processor, and the shared memory is accessed with almost no waste.

In addition, in order to increase speed, each processor's address (pipeline) register, write data (pipeline)
After passing through the selector means from the register and write flag (pipeline) register, the data is supplied to the address, data, and R/W lines of the shared memory through the respective pipeline registers, and data read from the shared memory is also supplied. It can also be configured such that the data is once latched in the pipeline register and then written to the read pipeline register of each processor.

Next, in such a processing system where multiple processors compete to access the shared memory, an interface is provided to send the data that has been processed to the host computer, or to transfer the data to be processed from the host computer in the reverse direction. think about. At this time, inside the processing device system,
For example, if the system includes a data processing block that reads and writes data that has been processed to a medium using a mechanical system, the processor that performs the interface is the exit for the processed data or the population of the unprocessed data. Naturally, it is best to set the priority to the lowest level for a series of processes on the same data. However, when looking at the processing system from the host computer, it is a problem that data transfer is forced to wait, and in order to avoid this, when a transfer between posts is about to occur, the processor accompanying the mechanical system is given priority. Even if it does not lower the priority, it lowers the priority of processors that do not have problems, raises the priority of the processor that performs the interface, and prioritizes transfers from the host computer over bus usage efficiency. Transfer waiting can be detected by installing a FIFO register between the host computer and detecting the storage state of data in the FIFO register, and if the contents of the FIFO register become nearly empty during transfer to the host computer. Alternatively, when the contents of the FIFO register are almost full during transfer to the host computer, this can be detected and the priority of the interfacing processor is raised from the lowest to the 4th priority, and the external -1-1- It is possible to increase the apparent processing speed. This makes it possible to increase both the bus usage efficiency and the apparent efficiency by -1.

Similarly, the following processing can be performed for the purpose of speeding up the processing. When multiple digital data processing units compete to access shared memory, the processors and the cows may destroy each other's data depending on the processing procedure. For this reason, when processing the same data in a sequence from processor A to processor B to processor C, a memory management mechanism is provided in each block LJ processor, and each block LJ processor has a shared memory IJF. It is common to only access address ranges. Naturally, when all jobs in the address range being accessed by a certain processor are completed, it is sufficient to access the address range in which processing by another processor has been completed. However, if the amount of work to be processed by a certain processor B is highly variable, the process that requires the longest processing time may become a bottleneck, resulting in poor overall performance.

At this time, if priority is given to speeding up, when the processing of processor B finishes early, processor 13 will be The address range being processed by A is entered, and the areas for which processing has been completed are sequentially processed.

By adding such a mechanism, the processor 1
The effective processing times of 3 are averaged, and the cases where the processor B is forced to wait for processing by the immediately preceding processor B can be reduced, and bus access efficiency can be further improved.

In addition, in order to increase speed, in each of the above means, if the predetermined priority of each digital processing unit is not the lowest, processing is performed so that the request flag is not activated every pipeline clock. By predetermining the procedure, it is possible to prevent other processing units from suspending processing for an extremely long time due to waiting for access.

Example Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, l is an address generation circuit.

Reference numeral 2 denotes an address pipeline register that holds addresses generated by the address generation circuit. 3 is a data generation circuit. 4 is a write data pipeline register that holds data generated by the data generation circuit described above.

5 is a read data pipeline register.

6 is a read data processing circuit that processes the data stored in the read data pipeline register. Reference numeral 7 denotes a request flag indicating that a request is being made to read the contents of the write data pipeline register with the intention of writing, or a request is being made to write the contents of the read data pipeline register with the intention of reading. Further, 8 is a write flag signal pipeline register that distinguishes whether writing is requested or reading is requested. Further, 9 is the first processor, 10 is the second processor, 11 is the third processor, and 12 is the fourth processor. Also 1
3 is a control microprocessor, generally called a microcontroller. Also 1
4 is a logic circuit that creates a request flag input signal, a write flag signal, and a pipeline register input signal from the access signal of the microcontroller. 15 is a fifth processor of the present invention, which includes a logic circuit 14, a microprocessor 13, an address pipeline register 2', a write data pipeline register 4', a read data pipeline register 5', and a request flag. 7" write flag signal pipeline register 8'. Also, 16 is an address selector circuit, 17 is a write data selector circuit, and 18 is a read data pipeline register 5.
This is a write clock generation circuit. 19 is a selector circuit for the write flag signal pipeline register.

20 is an arbitration circuit for signals of each request flag 7;
Determine the priority and select one processor each clock cycle. 21 is a modulation/demodulation circuit and a disk drive circuit. Further, 22 is a 5C5I interface, and 23 is a host computer and its 5C5I interface.
It is an interface. Further, 24 is a clock and control signal generation circuit. Clock signals and control signals are supplied to each processor, register, etc., but are omitted here because the diagram would be complicated. Similarly, the control lines from the 13 microcontrollers and the read data lines to the microcontrollers are also omitted. 25 again
is memory, which is shared memory by each processor.

The operation of this embodiment will be explained below using FIG.

When each of the processors 9 and 10111.12.15 accesses the shared memory 25, the request flag 8 of each processor is activated. This request flag is determined by the arbitration circuit 20 at each memory cycle time, and one processor is selected according to the priority assigned to each processor.

At this time, if the request flag is accepted, an acknowledge signal is returned and the request flag of the selected processor is cleared. Also, if the request flag is not accepted at this time, the processor enters an internal standby state to prevent loss of internal data. If the processor selected in this way is trying to write data, for example,
At the same time as each request flag is selected by the arbitration circuit 20, a selection signal based on the selected result is supplied to the selector circuit 2 of the address selector circuit 16, write data selector circuit 17, and write flag signal pipeline register 19, respectively. Address pipeline register 2, data pipeline register 4, write flag signal pipeline register 8 for each pipelined processor
Select.

The output of the write flag signal pipeline register 8 is active and is applied to the R/W line of the shared memory 25, so data is written to the shared memory 25. Similarly, if the output of the write flag signal pipeline register 8 is not active, data is read from the shared memory 25. When the request flag is accepted, a write pulse is applied from the clock generation circuit 18 to the input pipeline register 5 of the selected processor. In this way, reading and writing are determined for each memory cycle. For example, if the access time of the shared memory 25 is 100 ns, each processor will randomly access the memory every 100 ns according to the priority.

Next, another embodiment of the present invention will be explained with reference to FIG.

In FIG. 2, 26 is an address pipeline register, 27 is a write data pipeline register, 28 is a read data pipeline register, and 29 is a write flag signal pipeline register. The other means are the same as those in FIG. 1 and will therefore be omitted.

Next, the operation of this embodiment will be explained with reference to FIG. Basically, the operation is the same as that shown in FIG. 1, but the data selected by the address selector 16 is further pipelined by the address pipeline register 26 for another 19099 minutes, and is similarly selected again by the write data selector circuit 17. The written data also passes through the write data pipeline register 27, and the selector circuit 19 of the write flag signal pipeline register also passes through another stage of the write flag signal pipeline register 29 and pipelines one more clock. Further, data read from the shared memory 25 is also sent to each processor after passing through yet another stage of read data pipeline register 2B.

Another embodiment of the invention is shown in FIG. A feature of the processor shown in the figure is that it is a write-only processor and there is no write pipeline flag.

Therefore, the write signal is directly output.

Another embodiment of the present invention is shown in FIGS. 4(a) and 4(b).
Shown below. In FIG. 4(a), 30 is a FIFO register, and 31 is a logic circuit that uses a combinational gate to detect whether the data stored in the FIFO register is about to overflow or become empty. The example is FIFO
Assuming that the register has 16 bytes, an overflow warning is output when 14 bytes of data exist, and an empty warning No. 1 is output to the arbitration circuit 20' when there is only 2 hides of data.
I'm going to appear on J. If data is transferred from the host computer to the device of the present invention and the data reaches 14 bytes in the i' IFO register of 30, an overflow warning will cause the priority assigned to this processor in the arbitration circuit of 20'. Switch the degree from the lowest position to the 1st position. Similarly, when data is transferred to the host computer, if there are only 2 bytes of data in the 300 FIFO register, an empty warning signal is output to the arbitration circuit 20', and the priority of the processor is similarly increased.

Figure 4 (+) shows this part enlarged a little more.

Further, FIG. 5 shows another embodiment of the present invention, and 32 is a memory management mechanism (MY U ). Further, 33 is an Atonenos comparison circuit. Further, 34 is a sequence control circuit. Typically, these processors use 1J when accessing memory.
MMtJ32 in two processors by accessing other areas but specifying the lower address as a processing procedure.
are set so that the same area amount is accessed, and the address comparison circuit 33 compares the lower addresses to prevent overtaking of processing. At this time, if the processor 11 has caught up with the processing, the sequence control circuit 34 is stopped and the processing is stopped.

Another embodiment of the present invention will be described with reference to FIG.

In the figure, 35 is a 1/2 cycle clock generation circuit.

By making the shared memory access operation of the sequential control circuit take half the time of the system cycle tie 11, the shared memory is not accessed every time.

Effects of the Invention The present invention allows various processors to access the shared memory with the priority required for the work being processed each time the memory is accessed. Therefore, each processor does not need to have a buffer memory, and can access the shared memory at high speed and with high bus usage efficiency. In particular, external memory access can be optimized when a large number of processors are incorporated into one LSI chip to achieve high-speed processing. This hardware is minimal and can also achieve high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the digital data processing unit arbitration apparatus according to the present invention, FIG. 2 is a block diagram of an embodiment of the digital data processing unit arbitration apparatus according to the present invention, and FIG. 3 is a block diagram of an embodiment of the digital data processing unit arbitration apparatus according to the present invention. FIG. 4(a) is a block diagram showing an embodiment of the digital data processing unit arbitration device in the present invention, and FIG. 4(b) is a block diagram showing an embodiment of the digital data processing unit arbitration device in the present invention. Block diagram describing (a) in detail, No. 5
FIG. 6 is a block diagram showing one embodiment of the digital data processing unit arbitration device of the present invention, and FIG. 6 is a block diagram showing another embodiment of the shared memory access method of the above embodiment. DESCRIPTION OF SYMBOLS 1... Address generation circuit, 2... Address pipeline register, 3... Data generation circuit, 4... Write data pipeline register, 5... Read data pipeline register, 6... Read data processing circuit, 7... Request flag, 8... Write flag signal pipeline register, 9... First processor, 10... Second processor, 11...
Third processor, 12... Fourth processor, 13... Control microprocessor, 14...
・Logic circuit, 15...Fifth processor, 16・
...Address selector circuit, 17...Write data selector circuit, 18...Write clock generation circuit,
19... Selector circuit for write flag signal pipeline register, 20... Arbitration circuit for request flag signal,
21...Modulation/demodulation circuit and disk drive circuit, 2
2...5CSI interface, 23...host computer and its 5C5I interface, 2
4...Clock and control signal generation circuit, 25...Memory 1) Tadashi Michi No. 3 Figure 5 LLI Processor Syndrome Processor No. 4

Claims (7)

[Claims] (1) For each of at least a plurality of processors, a request flag indicating that access to the shared memory is requested, a shared memory address holding pipeline register to be accessed, a write data pipeline register (at the time of writing), and a read A data pipeline register (at the time of reading) and a write flag signal pipeline register indicating write or read are provided, and the request flags of each of the processors are made to compete with each other using a synchronized clock for pipeline processing to determine the priority of those processors. At the time of writing, the shared memory address, write data, and write flag signal of the selected processor are output in a pipeline using a synchronous clock, and in the next pipeline cycle, the address bus and data bus of the shared memory are written. When reading, the shared memory address and read/write flag signals are sent to the address bus, data bus, and write signal line (R/W) of the shared memory in the next pipeline cycle using a synchronous clock. ) and reading data from said shared memory and writing it to a read pipeline register of a determined selected processor by the end of said pipeline cycle. (2) an address generation means, an address pipeline register that holds the address generated by the address generation means, a write data pipeline register that holds the data generated by the data generation means and the data generation means, and a read data pipeline register that holds the address generated by the address generation means; a data pipeline register and read data processing means for processing data stored in the read data pipeline register;
A request flag indicating that a read of the contents of the write data pipeline register is being requested with the intention of writing or a request is being made to write the contents of the read data pipeline register with the intention of reading, and whether the write is requested. and a write flag signal pipeline register that distinguishes whether a read is requested, and when the write based on the request flag is not accepted, the address pipeline register is set by continuing the processing of the address generation means and the data generation means. and a means for preventing the contents of the write data pipeline register and the write flag signal pipeline register from being damaged, or a means for preventing the contents of the write data pipeline register and the write flag signal pipeline register from being damaged, or by continuing processing of the address generation means when the read based on the request flag is not accepted. a plurality of digital data processing unit groups provided with a register and means for preventing the contents of the write flag signal pipeline register from being damaged; and each of the address pipelines of the plurality of digital data processing unit groups. A selection means is provided for selecting one system from each output of the register and supplies it to an address bus of a separately provided shared memory, and from among each output of each of the write data pipeline registers of the plurality of digital data processing unit groups. Selecting means for selecting one system from among the plurality of digital data processing unit groups is provided to supply the data bus of the shared memory, or a selection means for selecting one system from the plurality of digital data processing unit groups is provided. selection means for supplying the input signal to at least one input of the read data pipeline register of the plurality of digital data processing units, and selecting one of the output signals of the write flag signal pipeline register of the plurality of digital data processing unit groups; The selected content is supplied to the write control line of the shared memory, and the selection means and the write/read procedure control the request flags according to the predetermined priority of each digital data processing unit. Select the content whose contents are active, supply the value of the selected address pipeline register to the address bus of the shared memory in the next pipeline cycle, and at the same time supply the value of the selected address pipeline register to the write signal line of the shared memory. The content of the write flag signal pipeline register is supplied, and if the content of the selected write flag signal pipeline register is a write request, the value of the selected write data pipeline register is supplied to the data of the shared memory. When the write flag signal pipeline register indicates a read request, the data bus of the shared memory reads the contents written in the shared memory, and the corresponding It writes to the read data pipeline register of the digital data processing unit,
A digital data processing unit arbitration device, wherein the request flag is cleared when the request of the request flag corresponding to the digital data processing unit is accepted. (3) an address generating means and an address register that holds the address generated by the address generating means;
a data generating means; a write data register for holding data generated by the data generating means;
read data processing means for processing data stored in the read data pipeline register and the first read data pipeline register; and read data processing means for processing data stored in the read data pipeline register and the first read data pipeline register; Indicates that a request is being made, or requests at a point before the pipeline to write the read data to the first read data pipeline register after being read and pipelined with the intention of being read again. and a write flag that distinguishes whether writing is requested or reading is requested, and when the writing based on the request flag is not accepted, the address generating means and the data generating means are provided. means for preventing the contents of the address register and the write data register from being damaged by the continuation of the processing of the means, or for preventing the contents of the address register and the write data register from being damaged by the continuation of the processing of the address generating means when reading by the request flag is not accepted. A selection of selecting one system from among a plurality of digital data processing unit groups provided with means for preventing content from being damaged, and each output of each of the address registers of the plurality of digital data processing unit groups. selecting means for supplying the selected content to the input of a separately provided address pipeline register, and selecting one system from among the outputs of each of the write data registers of the plurality of digital data processing unit groups; means for selecting one of the plurality of digital data processing units; supply to at least one input of each of the selected first read data pipeline registers, and select one of the output signals of the write flags of the plurality of digital data processing unit groups; A selection means is provided to supply the selected content to the input of a separately provided write flag signal pipeline register, further supply the contents of the write flag signal pipeline register to a write control line of a separately provided shared memory, and The output of the address pipeline register is supplied to the address bus of the shared memory, and the output of the data pipeline register is supplied to the data bus of the shared memory, or the output of the data pipeline register is supplied to the data bus of the shared memory, or the read contents that have been written to the shared memory is supplied to the second read data pipeline register for recording or reading, and the selection means for selecting one system and the write/read procedure are based on predetermined priorities of each digital data processing unit. The content of the request flag is selected as active according to the request flag, and an output signal indicating writing of the write flag of one system of the selected digital data processing unit is sent to the write flag pipeline in the next pipeline cycle. Writing to the register Further, in the next pipeline cycle, the output signal of the write flag pipeline register is supplied to the write control line of the shared memory, and at the same time, the output signal of the selected digital data processing unit is supplied to the write control line of the shared memory. When the write flag indicates a write request, the contents of the selected address register are written to the address pipeline register in the next pipeline cycle, and the contents of the selected write data register are written to the write data pipeline register. Write and, in the next pipeline cycle, supply the contents of the address pipeline register to the address bus of the shared memory and supply the value of the write data pipeline register to the data bus of the shared memory, or alternatively select An output signal indicating that the write flag of one system of the digital data processing unit has been read is written to the write flag pipeline register in the next pipeline cycle, and then written to the write flag pipeline register in the next pipeline cycle. An output signal is supplied to the write control line of the shared memory, and at the same time, the contents of the selected address register are written to the address pipeline register in the next pipeline cycle, and further in the next pipeline cycle. The contents of the address pipeline register are supplied to the address bus of the shared memory, and the contents of the shared memory are read onto a data bus and written to the second read pipeline register, and then in the next pipeline cycle. The content of the second read pipeline register is written to the first read pipeline register of the digital data processing unit selected at the time a read request is selected, and the digital data processing unit A digital data processing unit arbitration device, characterized in that the request flag is cleared when the request of the request flag corresponding to the request flag is accepted. (4) Among the processing units, a write-only read-only digital data processing unit omit either the write data pipeline register or the read data pipeline register, and correspondingly, the write flag is not provided and a fixed signal is used. A digital data processing unit arbitration device according to claim 1 or claim 2. (5) In a digital data processing unit arbitration device in which a plurality of digital data processing units each having a set access priority compete to access a shared memory,
At least a function for interfacing a host computer is assigned to one of the digital data processing units, and the digital data processing unit for interfacing is set in advance to have the lowest priority, and A FIFO register is provided between the digital data processing unit and the host computer, and means is provided for detecting the storage state of data in the FIFO register, so that if the contents of the FIFO register become nearly empty during transfer to the host computer. or when the contents of the FIFO register become nearly full during transfer to the host computer, this is detected and the priority given in advance to the FIFO register is set from the lowest to the highest priority. Digital data processing unit arbitration device. (6) In a digital data processing unit arbitration device in which a plurality of digital data processing units compete to access a shared memory, each digital data processing unit includes a memory management mechanism, and the memory management mechanism When each unit accesses only a separate fixed range of areas within the shared memory, each processing digital processing unit independently determines the priority of mutual contention, and at the same time two or more of the digital data processing units When accessing the same fixed range area of the memory, the memory management mechanism accesses the same fixed range area in addition to determining mutual conflict priority in the above case. The method further includes means for stopping access to the shared memory of some of the digital data processing units, or for setting a procedure for mutually accessing processing areas of the digital data processing units. Features: Digital data processing unit arbitration device. (7) A means is provided for not activating the request flag at every pipeline clock for at least one of the predetermined digital data processing units that does not have the lowest priority. A digital data processing unit arbitration device according to claim 1, 2, 4, or 5.