JPH0423043A - Fuzzy arithmetic circuit - Google Patents

Fuzzy arithmetic circuit

Info

Publication number
JPH0423043A
JPH0423043A JP12544190A JP12544190A JPH0423043A JP H0423043 A JPH0423043 A JP H0423043A JP 12544190 A JP12544190 A JP 12544190A JP 12544190 A JP12544190 A JP 12544190A JP H0423043 A JPH0423043 A JP H0423043A
Authority
JP
Japan
Prior art keywords
outputs
arithmetic circuit
output
amplifiers
operational amplifiers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12544190A
Other languages
Japanese (ja)
Inventor
Kohei Hasegawa
長谷川 公平
Yasumasa Suga
恭正 菅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Heavy Industries Ltd
Original Assignee
Sumitomo Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Heavy Industries Ltd filed Critical Sumitomo Heavy Industries Ltd
Priority to JP12544190A priority Critical patent/JPH0423043A/en
Publication of JPH0423043A publication Critical patent/JPH0423043A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a new fuzzy arithmetic circuit with the high responsiveness by providing two operational amplifiers, a comparison signal, a control part, and a function generating circuit and actuating the operational amplifiers only in a linear area of the arithmetic circuit. CONSTITUTION:When an input signal V1 is inputted to the operational amplifiers OP1 and OP2 respectively, the outputs P1 and P4 of the amplifiers OP1 and OP2 cross the voltage of 0 level at the positions decided by the comparison voltage levels VR and VL respectively. Thus both outputs P1 and P4 rise or fall. These output characteristics are turned into the outputs P2 and P5 having the changed slopes by the regulators VR1 and VR2. The comparators DC1 and DC2 are set at a contact voltage level -VBE and then turned into the outputs P3 and P6 at the negative and positive sides centering on the cross positions decided by the comparison voltage levels VR and VL respectively. At a function generating part FG, the outputs P3, P6 and P7 are inputted to the bases of transistors 5 - 7 respectively and synthesized. Thus the trapezoidal output characteristic VOUT is obtained. Therefore a fuzzy arithmetic circuit using the amplifiers OP1 and OP2 can maintain high speed responsiveness.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明はファジィ演算回路に関し、特にファジィ演算の
前半において台形状のメンバシップ関数を発生するため
の演算回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fuzzy arithmetic circuit, and particularly to an arithmetic circuit for generating a trapezoidal membership function in the first half of a fuzzy arithmetic operation.

[従来の技術] 最近、ファジィ推論を用いた制御方法、いわゆるファジ
ィ制御は広汎な分野にわたって応用が考えられ、実用化
されつつある。例えば、ある被制御機器の制御に熟練操
作者の熟練技術を反映させ。
[Background Art] Recently, control methods using fuzzy inference, so-called fuzzy control, have been considered for application in a wide range of fields and are being put into practical use. For example, the skill of a skilled operator is reflected in the control of a certain controlled device.

非熟練者でも容易に操作を可能とする。あるいは自動運
転を可能とする手法の一つとして実用化が試みられてい
る。それに伴なって、ファジィ演算を専用に実行するハ
ードウェアについても研究が進み、ディジタル方式、ア
ナログ方式いずれについても提供されはじめてきている
。ファジィ演算回路は一般に、推論部、結論部により構
成される。
Even an unskilled person can easily operate it. Alternatively, attempts are being made to put it into practical use as a method to enable autonomous driving. Along with this, research has progressed into hardware that specifically executes fuzzy operations, and both digital and analog systems are beginning to be provided. A fuzzy arithmetic circuit generally includes an inference section and a conclusion section.

推論部は前件部処理と後件部処理とに分けられ、前件部
処理によって得られるメンバシップ関数に基づいて後件
部処理が行われる。
The inference section is divided into antecedent part processing and consequent part processing, and consequent part processing is performed based on the membership function obtained by the antecedent part processing.

[発明が解決しようとする課題] これまでのものは1例えばディジタル方式のものについ
て言えば、その離散的な性質から信号の連続性が時間、
レベル共に維持されないという問題点がある。一方、ア
ナログ方式の場合には、すベてトランジスタで構成され
ているために回路が複雑になるという問題点がある。
[Problems to be Solved by the Invention] Up until now, for example, in the case of digital systems, due to their discrete nature, the continuity of the signal is limited over time.
There is a problem that the level is not maintained. On the other hand, in the case of an analog system, there is a problem in that the circuit is complicated because it is entirely composed of transistors.

本発明はファジィ演算回路の中でも特に、前件部メンバ
シップ関数発生の演算回路に着目し、演算増幅器とトラ
ンジスタとの組合わせにより簡単な構成で高速のファジ
ィ演算に寄与するアナログ形の演算回路を提供しようと
するものである。
Among fuzzy arithmetic circuits, the present invention focuses on arithmetic circuits that generate membership functions in the antecedent part, and has developed an analog arithmetic circuit that contributes to high-speed fuzzy arithmetic operations with a simple configuration by combining operational amplifiers and transistors. This is what we are trying to provide.

[課題を解決するための手段] 本発明によれば、入力信号と第1の比較信号。[Means to solve the problem] According to the invention, an input signal and a first comparison signal.

入力信号と第2の比較信号とをそれぞれ入力とする第1
.第2の演算増幅器を含んで第1.第2の出力特性を示
す第1.第2の差動増幅部と、前記第1.第2の演算増
幅器のゲインを可変とする調整部と、該調整部の出力及
び第3の比較信号とを人力として台形状の関数を発生す
る回路とを含むファジィ演算回路が得られる。
a first signal receiving the input signal and the second comparison signal as inputs;
.. the first . The first one shows the second output characteristic. a second differential amplification section, and the first. A fuzzy arithmetic circuit is obtained that includes an adjustment section that makes the gain of the second operational amplifier variable, and a circuit that generates a trapezoidal function using the output of the adjustment section and the third comparison signal manually.

[作 用] 上記構成において、第1.第2の演算増幅器は。[Work] In the above configuration, first. The second operational amplifier is.

台形状の関数における2つの斜線を与え、第1゜第2の
比較信号は2つの斜線と電圧零レベルとの交点を決定す
る。また、調整部は2つの斜線の傾きを決定する。関数
発生回路は調整部からの2つの出力と第3の比較信号と
を合成して台形状の関数を発生する。
Given two diagonal lines in a trapezoidal function, the first and second comparison signals determine the intersection of the two diagonal lines and the voltage zero level. The adjustment unit also determines the slopes of the two diagonal lines. The function generation circuit generates a trapezoidal function by combining the two outputs from the adjustment section and the third comparison signal.

[実施例] 以下に1図面を参照して本発明の詳細な説明する。[Example] The invention will now be described in detail with reference to one drawing.

第1図は本発明によるアナログ形ファジィ演算回路の要
部であるメンバシップ関数発生部を示す。
FIG. 1 shows a membership function generating section which is a main part of an analog type fuzzy arithmetic circuit according to the present invention.

このメンバシップ関数発生部は、第2図に示す太線の如
き台形状のメンバシップ関数を発生するためのものであ
る。
This membership function generating section is for generating a trapezoidal membership function as shown by the thick line in FIG.

本回路は、第2図に示す台形状のメンバシ・ンプ関数を
構成する直線aの如き第1の出力特性を示しその立上が
り位置VRが可変の第1の演算増幅器OPIと、直線C
の如き第2の出力特性を示しその立下がり位置VLが可
変の第2の演算増幅器OP2と、直線aの傾きθ7を調
整するための調整器VRIと、直線Cの傾きθLを調整
するための調整器VR2と、トランジスタTri、Tr
2による第1の比較器DCIと、トランジスタTr3、
Tr4による第2の比較器DC2と、関数発生部FGと
から成る。関数発生部FGは3つのトランジスタTr5
〜Tr7から成る。比較器DC1、DC2及び関数発生
部FGは、直線a、直線Cの他に、電圧零レベルを示す
直線b(第2図)。
This circuit consists of a first operational amplifier OPI which exhibits a first output characteristic such as a straight line a constituting a trapezoidal member pump function shown in FIG. 2, and whose rising position VR is variable;
A second operational amplifier OP2 exhibiting a second output characteristic as shown in FIG. Regulator VR2 and transistors Tri and Tr
2 and a transistor Tr3,
It consists of a second comparator DC2 based on Tr4 and a function generator FG. The function generator FG includes three transistors Tr5.
~ Consists of Tr7. Comparators DC1, DC2 and function generator FG are connected to straight line a and straight line C, as well as straight line b indicating the zero voltage level (FIG. 2).

台形の上辺を規定する直線d(第2図)を合成して台形
状のメンバシップ関数を出力する。
Straight lines d (FIG. 2) defining the upper side of the trapezoid are combined to output a trapezoidal membership function.

次に、動作について説明する。Next, the operation will be explained.

第1図において、入力信号V1が入力されると演算増幅
器OPI、OP2は差動増幅型であるので、これらの出
力特性は第3図(a)の出力P1(演算増幅器0PI)
、第3図(b)の出力P4(演算増幅器0P2)で表わ
される。出力P1は。
In Fig. 1, when the input signal V1 is input, the operational amplifiers OPI and OP2 are of differential amplification type, so their output characteristics are the output P1 (operational amplifier 0PI) in Fig. 3(a).
, is represented by the output P4 (operational amplifier 0P2) in FIG. 3(b). The output P1 is.

演算増幅器OPIの他方の比較電圧VRで決まる位置で
電圧零レベルと交差して立上がる。一方。
It crosses the voltage zero level and rises at a position determined by the other comparison voltage VR of the operational amplifier OPI. on the other hand.

出力P4は、演算増幅器OP2の他方の比較電圧VLで
決まる位置で電圧零レベルと交差して立下がる。
The output P4 crosses the voltage zero level and falls at a position determined by the other comparison voltage VL of the operational amplifier OP2.

次に、上記の各出力特性は、調整器VRI、VR2を調
整することで第3図(a)の出力P2.第3図(b)の
出力P5で示すように傾きを変えることができる。この
段階では電圧零レベルとの交差位置は変化しない。
Next, each of the above output characteristics can be changed to the output P2 in FIG. 3(a) by adjusting the regulators VRI and VR2. The slope can be changed as shown by output P5 in FIG. 3(b). At this stage, the intersection position with the voltage zero level does not change.

比較器DCIでは、トランジスタTr2のベースが接地
電位とされることで、第3図(a)の出力P2がトラン
ジスタTrlのベース・エミッタ間電圧VBE分だけ減
少方向にシフトされ、比較電圧VRで決まる交差位置よ
り負側では定電圧−VBEとなる。その結果、出力はP
3で表わされるようになる。同様の理由で、比較器DC
2では、第3図(b)の出力P5が電圧VBE分だけ減
少方向にシフトされ、比較電圧■して決まる交差位置よ
り正側では定電圧−VBEとなる。その結果、出力はP
6で表わされるようになる。
In the comparator DCI, by setting the base of the transistor Tr2 to the ground potential, the output P2 in FIG. 3(a) is shifted in the decreasing direction by the base-emitter voltage VBE of the transistor Trl, and is determined by the comparison voltage VR. On the negative side of the intersection position, the voltage becomes constant -VBE. As a result, the output is P
It will be expressed as 3. For the same reason, the comparator DC
2, the output P5 in FIG. 3(b) is shifted in the decreasing direction by the voltage VBE, and becomes a constant voltage -VBE on the positive side of the crossing position determined by the comparison voltage 2. As a result, the output is P
It will be expressed as 6.

関数発生部FGでは、トランジスタTr5のベースに出
力P3が、トランジスタTr6のベースには出力P6が
、トランジスタTr7のベースには第3の比較電圧P7
(VP  VBE)(但し。
In the function generator FG, the output P3 is applied to the base of the transistor Tr5, the output P6 is applied to the base of the transistor Tr6, and the third comparison voltage P7 is applied to the base of the transistor Tr7.
(VP VBE) (However.

■、は台形状関数の上辺の電圧値)で規定される出力P
7がそれぞれ入力され合成されることにより、第4図に
示すように、出力P3とP6との合成出力が電圧VBI
E分だけ上方にシフトされ1合成結果出力V。UTとし
て一点鎖線で示す台形状の出力特性が得られる。
■, is the voltage value on the upper side of the trapezoidal function)
7 are inputted and combined, the combined output of outputs P3 and P6 becomes voltage VBI, as shown in FIG.
1 synthesis result output V is shifted upward by E. As UT, a trapezoidal output characteristic shown by a dashed line is obtained.

以上の説明で理解できるように1本発明による演算回路
では演算増幅器が線形領域のみで動作するようにした点
に特徴がある。通常、第2図に示すような台形状の関数
を発生しようとする場合。
As can be understood from the above description, the arithmetic circuit according to the present invention is characterized in that the operational amplifier operates only in the linear region. Usually, when trying to generate a trapezoidal function as shown in FIG.

演算増幅器とダイオードとの組合わせで実現されている
が、これまでのものは演算増幅器が線形領域だけでなく
飽和領域でも動作する。この場合。
It is realized by a combination of an operational amplifier and a diode, but in the conventional ones, the operational amplifier operates not only in the linear region but also in the saturation region. in this case.

演算増幅器の応答可能な周波数帯域が線形領域での使用
時の周波数帯域に比べ1桁程度低くなる。
The frequency band in which the operational amplifier can respond becomes about one order of magnitude lower than the frequency band when used in the linear region.

これに対し1本発明の演算回路では、上述した理由によ
り演算増幅器の持つ高周波数帯域を損うことがなく、シ
たがって高速応答性を実現することができる。
On the other hand, the arithmetic circuit of the present invention does not impair the high frequency band of the operational amplifier due to the above-mentioned reasons, and therefore can realize high-speed response.

なお、実施例の説明では、出力PL、P4の傾きを調整
する手段として、可変抵抗器を用いているが、ディジタ
ルポテンショあるいはアナログマルチプレクサ等を用い
てディジタル値でリモート設定可能に構成しても良い。
In the description of the embodiment, a variable resistor is used as a means for adjusting the slope of the outputs PL and P4, but it may also be configured to allow remote setting using digital values using a digital potentiometer or an analog multiplexer. .

[発明の効果] 以上説明してきたように1本発明は演算増幅器を用いた
新しいタイプのファジィ演算回路であり。
[Effects of the Invention] As explained above, the present invention is a new type of fuzzy arithmetic circuit using an operational amplifier.

簡単な構成で高速応答性を持たせることができる。A simple configuration can provide high-speed response.

しかも1台形状の関数の斜線部分に対応する特性の傾き
及び電圧零レベルとの交差位置を容易に調整できる。
Moreover, the slope of the characteristic corresponding to the hatched portion of the trapezoidal function and the intersection position with the voltage zero level can be easily adjusted.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明によるファジィ演算回路の要部であるメ
ンバシップ関数発生部の回路図、第2図は第1図に示さ
れた回路で発生されるメンバシップ関数の一例を示した
図、第3図、第4図はそれぞれ、第2図に示したメンバ
シップ関数の発生過程を説明するための出力特性図。 図中、OPI、OF2は演算増幅器、FGは関数発生部
。 第1図 第2図 第3図 (a) (b) 第4図 厳
FIG. 1 is a circuit diagram of a membership function generating section which is a main part of a fuzzy arithmetic circuit according to the present invention, and FIG. 2 is a diagram showing an example of a membership function generated by the circuit shown in FIG. 1. 3 and 4 are output characteristic diagrams for explaining the generation process of the membership functions shown in FIG. 2, respectively. In the figure, OPI and OF2 are operational amplifiers, and FG is a function generator. Figure 1 Figure 2 Figure 3 (a) (b) Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1)入力信号と第1の比較信号,入力信号と第2の比較
信号とをそれぞれ入力とする第1,第2の演算増幅器を
含んで第1,第2の出力特性を示す第1,第2の差動増
幅部と、前記第1,第2の演算増幅器のゲインを可変と
する調整部と、該調整部の出力及び第3の比較信号とを
入力として台形状の関数を発生する回路とを含むことを
特徴とするファジィ演算回路。
1) First and second operational amplifiers that include first and second operational amplifiers that receive the input signal and the first comparison signal, and the input signal and the second comparison signal, respectively, and exhibit first and second output characteristics. a circuit that generates a trapezoidal function using the output of the adjustment section and a third comparison signal as input; A fuzzy arithmetic circuit comprising:
JP12544190A 1990-05-17 1990-05-17 Fuzzy arithmetic circuit Pending JPH0423043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12544190A JPH0423043A (en) 1990-05-17 1990-05-17 Fuzzy arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12544190A JPH0423043A (en) 1990-05-17 1990-05-17 Fuzzy arithmetic circuit

Publications (1)

Publication Number Publication Date
JPH0423043A true JPH0423043A (en) 1992-01-27

Family

ID=14910167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12544190A Pending JPH0423043A (en) 1990-05-17 1990-05-17 Fuzzy arithmetic circuit

Country Status (1)

Country Link
JP (1) JPH0423043A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212063A (en) * 2008-03-06 2009-09-17 Panasonic Electric Works Denro Co Ltd Circuit breaker

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212063A (en) * 2008-03-06 2009-09-17 Panasonic Electric Works Denro Co Ltd Circuit breaker

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