JPH04229657A - Semiconductor element for electric power use provided with insulated gate - Google Patents

Abstract

PURPOSE:To enhance the turn-off ability of the title element without lowering its turn-on ability by a-method wherein a gate part for turn-off use or for turn-on use is distributed so as to have two or more kinds of threshold voltages in individual parts on a pellet. CONSTITUTION:The title element is provided with a p-type emitter layer 11, an n-type base layer 1, a p-type base layer 2 and an n-type emitter layer 3. A channel region 8 for turn-off use is formed around the n-type emitter layer 3; a channel region 9 for turn-on use is formed around the p-type base layer 2. At a thyristor, provided with an insulated gate, in which many unit elements A, B on which insulated gate electrodes 7 have been formed on the regions have been arranged, the threshold voltage of turn-off channel regions 81 in each element A and the threshold voltage of turn-off regions 82 in each element B are set to different values. Thereby, while an excellent turn-off characteristic is being maintained, the turn-off ability of the title element can be enhanced.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device with an insulated gate.

0003

[Prior Art] GTO thyristors, IGBTs, and MOSFETs have conventionally been used as power semiconductor devices with insulated gates.
etc. are known. In one of the GTO thyristors with an insulated gate, both the turn-on and turn-off gate parts have an insulated gate structure and one common gate terminal is provided.
MCT (Mos Controlled Thyri)
There is something called stor. This uses the outer peripheral part of the p-type base layer as a turn-on channel (n-channel), and the p-type emitter layer formed in the p-type base layer is further connected to the cathode electrode together with the n-type emitter layer.
A type layer is provided, and the outer periphery of the n-type emitter layer is used as a turn-off channel (p channel).

[0004] Such turn-on channels and turn-off channels are arranged in a substantially uniformly distributed manner on the element pellet to prevent current concentration when cutting off a large current. In this case, the threshold of the p-channel section for turn-off is designed to be the same value throughout the pellet in order to ensure uniform turn-off throughout the pellet and to ensure maximum turn-off capability. Similarly, the turn-on n-channels are designed to have equal threshold voltages to ensure uniform turn-on of the entire pellet.

By the way, there is a large difference in the waveform of the gate current flowing during turn-off between a current-driven GTO thyristor in which the gate electrode is directly connected to the p-type base layer and an MCT having an insulated gate structure. In a current-driven GTO thyristor, the gate current iG can be easily controlled by an external gate circuit, and therefore diG /dt can be set small. On the other hand, in the case of an MCT, diG /dt depends on whether the voltage applied to the insulated gate terminal exceeds the gate threshold voltage, so its control range is narrow. In reality, diG/dt is approximately determined at the time of device design. This is an essential difference between an MCT that has a built-in gate circuit and a GTO that has a gate circuit outside the device. This relationship is as shown in FIG. 2, and a small diG/dt can be obtained with a GTO thyristor, but this is not possible with an MCT.

[0006] As described above, in MCT, the characteristic that the control range of diG/dt is small is an obstacle to maximizing the performance of the device. Specifically, if there are variations in the threshold values of turn-off channels on the device pellet, current concentration easily occurs, leading to device destruction. In order to suppress this current concentration and reduce turn-off loss, it is effective to make the unit element on the pellet smaller, that is, to make the cathode pattern finer. However, in this case, although the turn-off ability is improved, the injection efficiency of the cathode/emitter is lowered, and the turn-on characteristics are deteriorated.

[0007]

[Problem to be solved by the invention] As mentioned above, MCT
However, there was a problem in that the turn-off ability was low, and in particular, the turn-off ability was greatly reduced due to manufacturing variations in the threshold voltage of various parts on the pellet, and any attempt to improve this would result in a lower turn-on ability. Similar problems exist not only in MCTs but also in other power semiconductor devices having an insulated gate structure.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a power semiconductor device with an insulated gate that has improved turn-off ability without reducing turn-on ability.

[Configuration of the invention]

0010

[Means for Solving the Problems] The present invention provides, firstly, a power semiconductor device in which at least one gate portion for turn-on or turn-off has an insulated gate structure and is distributed over a semiconductor device pellet. It is characterized in that at least one of the gate parts for turn-on and turn-off is distributed with two or more different threshold voltages at each part on the pellet.

Second, the present invention provides a power semiconductor device in which at least one gate portion for turn-off or turn-on has an insulated gate structure and is arranged dispersedly on a semiconductor device pellet. One of the gates has a buried gate structure with a striped pattern, and a region adjacent to one side of this buried gate where a carrier discharge channel is formed and an emitter region adjacent to the other side are arranged alternately with minute intervals. It is a feature.

Thirdly, the present invention provides a power semiconductor device in which at least one gate portion for turn-off or turn-on has an insulated gate structure and is arranged dispersedly on a semiconductor device pellet. The emitter layer, which injects carriers at times, and the base layer, which discharges carriers at turn-off, are arranged alternately with minute intervals, and an insulating film is embedded between these emitter layers and the base layer. There is.

Fourthly, the present invention provides a power semiconductor device in which at least one of the gate portions for turn-off and turn-on has an insulated gate structure and is arranged dispersedly on a semiconductor device pellet. The buried gate structure is arranged as a buried gate structure having a plurality of striped patterns, and the base region adjacent to one side of each buried gate and the emitter region adjacent to the other side are arranged alternately, and the impurity concentration of the base layer between the buried gates is and the width thereof are set so that the carrier extraction resistance is substantially controlled by applying a gate voltage.

[0014]

[Operation] According to the first invention, by intentionally designing and distributing the threshold voltage of the turn-off channel in each part on the pellet to two or more different values, and by selecting the gate voltage waveform, a large number of The turn-off channels can be turned on at different times. This makes it possible to equivalently widen the control range of the change diG /dt in the off-gate current flowing through the entire turn-off channel of the entire pellet. The same applies when the turn-on channel has two or more threshold values. In this case, at turn-off, the turn-off channel is first turned off, and then the turn-on channels having different threshold voltages are sequentially turned off. Thereby, current concentration can be effectively suppressed. In addition, by intentionally varying the threshold voltage within the pellet, it is possible to relatively reduce the influence of variations in threshold voltage during manufacturing. With the above, it is possible to effectively suppress current concentration at turn-off while keeping the maximum turn-off current sufficiently large.
The turn-off ability of MCT etc. can be improved without reducing the turn-on ability.

According to the second invention, by employing a buried gate structure and arranging a large number of fine emitters at minute intervals within the pellet, emitter injection efficiency can be kept high and turn-off ability can be achieved without reducing turn-on ability. can be obtained. According to the third invention, in an emitter short-circuit structure in which p-type layers and n-type layers are alternately arranged at minute intervals in contact with an emitter electrode, the emitter injection efficiency is improved by embedding an insulating film in the pn junction. It is possible to quickly discharge carriers at turn-off while maintaining a high value. Therefore, the turn-off ability can be improved without impairing the turn-on ability.

According to the fourth invention, by designing the buried gate interval and the base layer impurity concentration, the effective width of the base layer of the emitter short-circuit portion is narrowed (that is, the resistance is substantially increased) at turn-on, High emitter injection efficiency can be ensured. On the other hand, during turn-off, the resistance of the base layer at the emitter short-circuit portion decreases due to carrier accumulation, and a sufficient carrier discharge effect can be obtained.

[0017]

[Examples] Examples of the present invention will be described below.

FIG. 1(a)(b), MCT of one embodiment
2 is a schematic layout and its AA' cross-sectional view, and FIG. 2 is a diffusion layer layout of one element. As shown in FIG. 1(a), in the MCT of this example, a plurality of elements surrounded by turn-on channels are arranged on the pellet, and two types of elements A in the figure are formed.
, B have threshold voltages of turn-off channels set to different values. That is, element A has a turn-off channel with a threshold voltage of Vth1, and element B has a turn-off channel with a threshold voltage of Vth2.
are arranged alternately.

A specific cross-sectional structure of the element is shown in FIG. 1(b). In this embodiment, one p-type base layer 2 and one n-type emitter layer 3 are formed on one surface of the n-type base layer 1, corresponding to one element. In the n-type emitter layer 3, there is a turn-off MOSF
A p+ type diffusion layer 4 serving as a source of ET is formed, and a cathode electrode 5 is disposed in contact with the n type emitter layer and this p+ type diffusion layer 4 at the same time. The outer periphery of the n-type emitter layer 3 forms a turn-off channel region 8 (81, 82).
), the outer periphery of the p-type base layer 2 sandwiched between the n-type emitter layer 3 and the n-type base layer 1 is a turn-on channel region 9, and a gate insulating film 6 is commonly formed in these regions.
A gate electrode 7 is provided via the gate electrode 7.

Turn-off channel region 8 of element A
1 is set to Vth1, and the threshold of the turn-off channel region 82 of element B is set to Vth2, which is different from Vth1. The turn-on channel region 9 is formed surrounding all the elements A and B and is set to a constant threshold value.

A p-type emitter layer 11 is formed on the other surface of the n-type base layer 1 via an n-type buffer layer 10, and an anode electrode 12 is formed on this p-type emitter layer 11.

Although the figure shows a case where there is one n-type emitter layer in one element to simplify the explanation, in actual high-power elements, there are multiple n-type emitter layers in one element. An emitter layer is formed, thus forming multiple turn-off channel regions within one element.

According to this embodiment, the threshold values of the turn-off channels of each part on the MCT pellet are set to two types, and the turn-off channels with different threshold values are distributed, so that as a result, the diG/dt is The control range becomes larger. This situation is shown in FIG. 3 by the broken line. In this way, at turn-off,
By making diG /dt smaller than in the past, current concentration can be suppressed and high turn-off capability can be obtained. In addition, intentionally providing two types of threshold voltages relatively reduces the influence of variations in threshold voltages during manufacturing. This also leads to the effect of suppressing current concentration at turn-off. As a result of the above, according to this embodiment, an MCT having high turn-off ability while maintaining high turn-on ability can be obtained.

FIGS. 4 and 5 show variations of the arrangement of elements A and B on a pellet with turn-off channels of different threshold voltages. By arranging these elements, the same effects as in the previous embodiment can be expected.

FIGS. 6-8 show the structure of one element of the MCT of another embodiment. (a) is a layout, (b) is a sectional view taken along line AA', and (c) is a sectional view taken along line BB'. Components corresponding to those in FIG. 1 are given the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted. In the previous embodiments, the threshold voltage of the turn-off channel region was constant within one element, but in these embodiments, the turn-off channel region may have two or more threshold voltages within one element. is set to .

For example, in the embodiment shown in FIG. 6, among the turn-off channel regions 8 forming a closed circuit, the threshold value of the channel region 81 running in the vertical direction on the layout of (a) is Vt.
h1, and the threshold value of the channel region 82 running in the lateral direction is set to Vth2, which is different from Vth1. In the embodiment of FIG. 7, the channel regions having different threshold voltages are further divided. In the embodiment of FIG. 8, the turn-off channel region 8 has three types of threshold values. That is, in the channel region 81, Vth1
, Vth2 in channel region 82 , channel region 8
3, the threshold voltage is set to Vth3.

The embodiments shown in FIGS. 6 to 8 also provide the same effects as the previous embodiments.

FIGS. 9(a), (b), and (c) show the layout of one element of MCT of another embodiment and its A.
-A' and BB' sectional views. Unlike the previous embodiments, in this embodiment the turn-on channel region 9 surrounding one element does not have a constant threshold;
It is composed of a channel region 91 having a threshold value Vth3 and a channel region 92 having a different threshold value Vth4. Regarding the turn-off channel region 8,
As in the previous embodiments, it is preferable to set two or more types of threshold values, but the threshold values may be constant.

This embodiment also provides the same effects as the previous embodiment. In other words, when turning off the turn-on channel, first turn off the turn-off channel, and then
This is because current concentration at turn-off can be suppressed by setting the gate voltage waveform so that regions with different threshold voltages of the turn-on channel are turned off with a time lag. The specific voltage waveform will be explained later.

FIGS. 10(a), 10(b), and 10(c) are layouts of two adjacent element portions of an MCT according to yet another embodiment, and sectional views taken along line AA' and line BB'. In this embodiment, unlike the embodiment of FIG. 9, the threshold of the turn-on channel is uniform within one element, but the turn-on channel region 91 of one of the two adjacent elements is set to the threshold Vth3. , the other turn-on channel region 92 is set to a threshold value Vth4 different from Vth3. By distributing elements having turn-on channels with different threshold values on the pellet, the same effects as in each of the above embodiments can be obtained.

FIG. 11 shows an embodiment in which an insulated gate structure is also introduced on the anode side. A p-type emitter layer 11 is selectively formed, an n+-type layer 13 is diffused therein, and an anode electrode 12 is formed at the same time as the p-type emitter layer 11.
It is also in contact with the mold layer 13. The outer peripheral portion of the p-type emitter layer 11 is used as a channel region 16, and a gate electrode 15 is formed on this region with a gate insulating film 14 interposed therebetween. In the element with this structure, each channel region 8 is separated between or within the elements as in the previous embodiments.
, 9, and 16, the same effects as in the previous embodiments can be obtained.

In the above embodiment, the impurity concentration NB (/cm3) and the thickness W (cm) of the n- type base layer 1 are
is set in the range of 1.5×1014<NB/W<2.5×1014 from the viewpoint of improving turn-off characteristics, and NB/W>2.5× from the viewpoint of improving turn-on characteristics. It is preferable to set it in the range of 1014.

FIGS. 12 to 15 show specific examples of device structures in which performance is expected to be improved by applying the present invention.

FIG. 12 shows a structure in which elements are formed in a striped pattern using a thick p-type base, with the upper surface serving as an anode and the lower surface serving as a cathode. CH1 is a turn-on channel, and CH2 and CH3 are turn-off channels.

In FIG. 13, a first gate electrode 71 that controls the turn-on channel region and a second gate electrode 72 that controls the turn-off channel region 8 are formed separately. The first gate electrode 71 has a normal planar insulated gate structure. The second gate electrode 72 is embedded in a trench formed deep enough to penetrate the n-type emitter layer 3. A p+ type diffusion layer 4 is formed along and above these grooves, and a turn-off channel region 8 is formed.
is formed vertically on the side wall of the groove.

FIG. 14 shows an embodiment that is a modification of FIG. 13. Similar to FIG. 13, a groove is formed penetrating through the n-type emitter layer 3, and a second gate electrode 72 is embedded therein in a striped pattern. In the region surrounded by the second gate electrode 72, portions serving as n-type emitter layers and portions where p-type diffusion layer 4 is formed and channel region 8 is formed are arranged alternately. That is, p-type diffusion layer 4
A vertical turn-off channel region 8 is formed in the region surrounded by the second gate electrode 7.

The structure shown in FIG. 13 employs a buried gate, but is different in that the region where the n-type emitter layer 3 and the turn-off channel region 8 for short-circuiting it with the p-type base are formed in the same region. No different from the conventional structure. This figure 14
In this embodiment, an n-type emitter layer 3 connected to a cathode electrode 5 for carrier injection, and a p-type emitter layer 4
a turn-off channel region 8 that short-circuits the p-type base layer 2 with the p-type base layer 2;
The regions where the gate electrodes are formed have a structure in which they are separated from each other by the buried gate electrodes 7 and arranged alternately. This is a preferred structure for effectively suppressing current concentration while maintaining high injection efficiency by distributing finely structured n-type emitters at minute intervals of, for example, 10 μm.

In the embodiment shown in FIG. 14, a buried third gate electrode is also formed on the anode side. That is, a stripe pattern groove is formed passing through the p-type emitter layer 11, and the third gate electrode 15 is embedded in this groove with the gate insulating film 14 interposed therebetween. In the region sandwiched between the third gate electrodes 15, similar to the cathode side, portions where the p-type emitter layer 11 is exposed and portions where the n-type diffusion layer 13 is formed are arranged alternately. A turn-off channel region 16 is formed on the trench sidewall in the region where the n-type diffusion layer 13 is formed.

FIG. 15 shows a first gate electrode 71 for turn-on formed on the cathode side and a second gate electrode 71 for turn-off formed on the cathode side.
This embodiment has a buried structure similar to the gate electrode 72 shown in FIG. With this structure, an MCT element for high power can be formed in a small area.

In the device structures of FIGS. 12 to 15 exemplified above, by giving each channel region the threshold distribution as explained in each of the previous embodiments, the same effects as in each of the previous embodiments can be obtained. can get. Note that the buried gate structures shown in FIGS. 14 and 15 can obtain the same effect of improving turn-off ability without impairing turn-on ability without distributing channel regions with different threshold voltages. This is done by forming channels vertically and dividing the fine emitters into many parts within the pellet, e.g.
This is because they can be arranged at microscopic intervals of μm, thereby making it possible to sufficiently suppress current concentration during turn-off while maintaining high emitter injection efficiency.

FIG. 16 shows the MCT of the above embodiment,
Two threshold voltages VthA, V on the turn-off channel
This is an example of the gate voltage waveform applied to the turn-off gate and the corresponding gate current waveform when thB is applied. As shown in the figure, the gate voltage is set to the threshold voltage VthA, V
The turn-off channel within the pellet is turned on with a temporal shift by increasing the amount in two steps in relation to thB. As a result, compared to the case where the turn-off channels are turned on all over the pellet at once, it is possible to reduce the sharp change and concentration of the gate current, and as described above, the current concentration is suppressed.

FIG. 17 shows that two threshold voltages VthA and VthA are applied to the turn-on channel as in the embodiments shown in FIGS.
This is an example of a gate voltage waveform at turn-off when VthB is applied. As shown in the figure, when the turn-on channel is open, the off-gate voltage VG is applied to the turn-off gate electrode.
(OFF) so that the main current flows intensively to the on-channel, and then the gate voltage VG(ON) of the turn-on channel, which has two types of threshold voltages, is lowered stepwise to increase the threshold voltage. Different turn-on channels can be turned off in a staggered manner. This makes it possible to suppress current concentration during turn-off.

Although the method for setting the threshold value of each channel region to two or more different values has not been specifically explained above, this method can be done by using a method well known in ordinary MOS technology. I can do it. For example, in Figure 18,
A method is shown in which the threshold values of channel regions 81 and 82 are made different by forming one n-type emitter layer 3 by overlapping two diffusion layers 31 and 32 having different impurity concentrations. In addition, the threshold value can be made to have a distribution by a method of partially irradiating radiation, a method of changing the thickness of the gate insulating film, or the like.

FIG. 19 shows a comparison of the turn-off loss of the MCT of the present invention with that of a conventional element, and FIG. 20 shows a comparison of the maximum turn-off current density.

FIG. 21 shows the gate driving section 2 using an optical trigger.
This is an example in which 0 is integrally formed on a pellet. As shown in the figure, the present invention can also be effectively applied to an element in which a gate signal for controlling the main current is formed and supplied by an external optical signal.

FIG. 22 shows an MC of an embodiment in which the structure of FIG. 14 is adopted on the card side and the structure of FIG. 13 is adopted on the anode side.
It is T.

FIG. 23 shows an embodiment in which the buried gate structure shown in FIG. 14 is applied to an IGBT. n-type base layer 1
A groove is formed in a striped pattern so as to penetrate through the p-type base layer 2 formed on the surface of the p-type base layer 2, and a gate electrode 7 is buried in this groove with a gate insulating film 6 interposed therebetween. The region sandwiched between the buried gate electrodes 7 is
A region of only the p-type base layer 2 and a region of the n-type emitter layer 3 are formed alternately. The groove side of the p-type base layer 2 in the region where the n-type emitter layer (source layer) 3 is formed serves as a channel region 21 that is controlled by the gate electrode 7 to turn on and turn off the device. A cathode electrode (source electrode) 5 has a p-type base layer 2 and an n-type base layer 2.
They are arranged so as to contact the mold emitter layer 3 at the same time.

In the IGBT of this embodiment as well, FIG.
Similarly to the MCT shown in FIG. 1 and FIG. 15, a large number of finely structured emitters can be arranged at minute intervals, thereby making it possible to improve the turn-off ability while maintaining a high turn-on ability. Further, as in FIGS. 14 and 15, by giving a distribution to the threshold values of the channel region 21, the turn-off ability can be further improved.

FIG. 24 shows an IGBT of an embodiment in which, contrary to FIG. 23, a buried gate structure similar to that on the cathode side (source side) in FIG. 21 is adopted on the anode side (drain side). That is, an n-type base layer 1 is formed on the surface of a p-type base layer 2, striped grooves are formed at minute intervals so as to penetrate this n-type base layer 1, and a gate insulating film 6 is formed in the grooves. A gate electrode 7 is buried therebetween. n alternately across the region where the gate electrode 7 is buried.
Region with only type base layer and p-type emitter layer (drain layer)
11 are arranged. p-type emitter layer 11
The side surface of the n-type base layer 1 in the region where is formed becomes the channel region 22. The anode electrode (drain electrode) 12 is n
It is arranged so as to contact the type base layer 1 and the p-type emitter layer 11 at the same time.

It is clear that this embodiment also provides the same effects as the previous embodiment.

FIG. 25 shows an IGBT in which the structure of the cathode-emitter junction termination is improved. An n-type emitter layer 3 is formed in the p-type base layer 2, and a gate insulating film is formed on the surface portion of the p-type base layer 2 sandwiched between the n-type emitter layer 3 and the n-type base layer 1 as a channel region 21. A gate electrode 7 is formed through the gate electrode 6 . Cathode electrode 5
is disposed in contact with the p-type base layer 2 and the n-type emitter layer 3 at the same time. This basic structure is the conventional IGBT
is the same as In this embodiment, the n-type emitter layer 3 and the p-type
In the pn junction between the type base layers 2, the channel region 21
A groove is formed in a portion other than a portion connected to the groove, and an insulating film 23 is embedded therein. That is, the buried insulating film 23 is formed to surround the n-type emitter layer 3.

A large number of unit elements having such a structure of fine cathode emitters are formed in array on the pellet. Preferably, the channel region 21 is distributed as regions having two or more different threshold values, as in the embodiment described above. As a result, an IGBT with low leakage between the n-type emitter layer and the p-type base layer and high turn-off ability and high turn-on ability can be obtained.

A similar structure is a thyristor or MOSFET.
It can also be applied to FIG. 26 shows an example in which a structure similar to that of FIG. 23 is applied to a thyristor. During turn-off, the n-type emitter layer 3 and p
A p+ type diffusion layer 24 is formed to short-circuit the type base layer 2, and a buried insulating film 23 is formed around this p+ type diffusion layer 24.

FIG. 27 shows an embodiment similarly applied to a MOSFET. In FIG. 27, for convenience, the same reference numerals are given to the element regions corresponding to those in FIG. 5. The anode electrode 12 is a source electrode and a drain electrode, respectively. These embodiments also provide the same effects as the embodiment of FIG. 25.

FIG. 28 shows an embodiment in which the buried gate electrode 15 on the anode side in the structure shown in FIG. 14 is made into a buried insulating film 23. Thereby, an emitter short-circuit structure can be obtained without reducing the emitter injection efficiency on the anode side.

Next, striped embedded gate electrodes are arranged at minute intervals, and the interval is optimized by optimal design of the base layer impurity concentration of the emitter layer and base layer, which are alternately arranged with the gate electrode in between. , an embodiment that achieves high turn-on ability and high turn-off ability will be described. In the following embodiments as well, it is effective to set the threshold voltage of the buried insulated gate electrode portion to a plurality of different values within the pellet as described in the previous embodiment.

FIG. 29 shows an MCT of such an embodiment. Striped buried gate electrodes 7 for turn-off are formed on the p-type base layer 2 with minute intervals, and the n-type emitter layer 3 adjacent to one side of the buried gate electrode 7 and the p-type base layer 2 adjacent to the other side are alternately formed. Arranged. The cathode electrode 5 includes a p-type base layer 2 and an n-type emitter layer 3.
are placed in simultaneous contact with the In the figure, the turn-on gate electrode is not shown.

Here, the interval between the buried gate electrodes 7 is 10
It should be less than μm. The impurity concentration of the p-type base layer 2 is, for example, 1017/cm3 except for the contact portion with the electrode.
The following shall apply. The depth of the embedded groove is preferably greater than the groove interval.

According to this embodiment, the buried gate electrode 7
The resistance of the p-type base layer 2 in the region sandwiched between the buried gate electrodes 7 can be substantially controlled by the voltage applied to the p-type base layer 2, and as a result, excellent turn-off ability and turn-on ability can be obtained. . This can be seen in Figure 3.
This will be explained more specifically using FIG. 0 and FIG. 31.

FIG. 30 shows the turn-on state when a positive gate voltage is applied to the buried gate electrode 7. At this time,
An inversion layer is formed on the side wall of the buried gate electrode 7 of the p-type base layer 2, and electrons are collected as shown in the figure. As a result, the narrow p-type base layer 2 sandwiched between the buried gate electrodes 7 effectively becomes high in resistance, and the p-type emitter layer 11
It becomes difficult for holes injected from the p-type base layer 2 to reach the cathode electrode 5. As a result, the effect of the emitter short-circuit structure is halved, and the electron injection efficiency from the n-type emitter layer 3 becomes high.

On the other hand, at turn-off, the buried gate electrode 7
When a negative voltage is applied to , a hole accumulation layer is formed around the buried gate electrode 7, as shown in FIG. This lowers the resistance of the region of the p-type base layer 2 sandwiched between the buried gate electrodes 7. Then, the holes in the n-type base layer 1 are quickly discharged to the cathode electrode 5 through the p-type base layer 2. Further, in the region where the n-type emitter layer 3 is formed, since a hole accumulation layer is formed on the side wall of the groove of the p-type base layer 2, electron injection from the n-type emitter layer 3 is suppressed. As described above, a high-speed turn-off operation is performed.

FIG. 32 shows an embodiment in which the embodiment of FIG. 31 is modified to provide a similar buried insulated gate structure on the anode side. An n-type buffer layer 10 is formed on the anode side of the n--type base layer 1, in which a plurality of striped grooves are formed at minute intervals, and a gate electrode 15 is embedded therein. Between the buried insulated gate electrodes 15, regions where p-type emitter layers 11 are formed alternately and regions where n-type emitter layers 11 are formed are arranged alternately.
Areas where the mold buffer layer 10 is exposed are arranged.

According to this embodiment, high carrier injection efficiency at turn-on and effective emitter shorting at turn-off can be realized not only on the cathode side but also on the anode side.

FIG. 33 shows an embodiment in which, in addition to the structure of FIG. 32, a gate electrode for turn-on is formed with a buried structure. Buried gate electrode 72 for turn-off
, 152 are the same as in FIG. On the cathode side, apart from the buried insulated gate electrode 72 for turn-off, a groove is formed deep enough to penetrate through the p-type base layer 2, and an insulated gate electrode 71 for turn-on is embedded therein. An n-type source layer 30 is formed on the surface of the p-type base layer 2 on the sidewall portion of the gate electrode 71 which becomes a turn-on channel. On the anode side as well, a groove penetrating the n-type buffer layer 10 is formed, and an insulated gate electrode 151 for turn-on is embedded therein. A p-type source layer 35 is formed on the surface of the n-type buffer layer 10 on the sidewall portion of the gate electrode 151 which becomes a turn-on channel.

FIG. 34 shows an embodiment based on the structure of FIG. 29, in which an insulated turn-on gate electrode of a planar structure is provided. An n-type source layer 30 short-circuited with the n-type emitter layer 3 is formed in the peripheral part of the p-type base layer 2.
An insulated gate electrode 71 for turn-on is formed so as to cover the surface of the p-type base layer 2 in the region sandwiched between the type source layer 30 and the n-type base layer 1.

FIG. 35 shows an embodiment that is a modification of the embodiment shown in FIG. A high-resistance p-type channel layer 31 is formed in a region sandwiched between the buried insulated gate electrodes 7 of the p-type base layer 2, and an n-type emitter layer 3 and a high concentration p-type layer 32 are alternately arranged on the surface thereof. has been done. The impurity concentration of the p- type channel layer 31 is set to, for example, 1015/cm3 or less.

According to this embodiment, compared to FIG. 29, the insulated gate drive suppresses the outflow of holes from the p-type base layer to the cathode electrode during turn-on, improves the electron injection efficiency from the n-type emitter, and improves turn-off. This effectively improves hole ejection efficiency and suppresses electron injection from the n-type emitter layer.

FIG. 36 shows an example in which high-resistance channel layers are provided on both the cathode side and the anode side in the example of FIG. 32. The structure on the cathode side is the same as that in FIG. 35. On the anode side, a high-resistance n-type channel layer 33 is formed between the buried gate electrodes 15, and a p-type channel layer 33 is formed on its surface.
Type emitter layers 11 and high concentration n-type layers 34 are alternately arranged.

This embodiment makes it possible to achieve even better turn-off and turn-on capabilities.

FIG. 37 shows the structure of the embodiment shown in FIG.
This is an example to which a structure similar to that of the example is applied.

FIG. 38 shows n- in the embodiment of FIG.
The portion of the p-type base layer 1 is replaced with a p- type base layer 37, and the portion of the p-type emitter layer 11 is replaced with an n+-type drain layer 38.
This is an example in which a transistor is configured instead of . Even if the n- type base layer 1 is used as it is, the transistor operates.

FIG. 39 shows the buried insulated gate electrode 7
N+ type emitter layers 3 and p+ type emitter layers are formed to a depth reaching the type base layer 1 and alternately formed between the buried insulated gate electrodes 7.
This is an example in which a mold base layer 2 is formed to configure an SI thyristor.

FIG. 40 shows an embodiment in which the embodiment shown in FIG. 39 is modified to form a buried insulated gate electrode 15 with a depth reaching the n- type base layer 1 on the anode side as well.

FIG. 41 shows a structure in which a buried insulated gate electrode 7 is formed to penetrate through a p-type base layer 2, and an n-type emitter layer 3 and a p+-type base layer 32 are formed in a region sandwiched between the buried gate electrodes 7. FIG. 3 is a diagram illustrating a three-dimensionally developed example.

The embodiments shown in FIGS. 37 to 41 also provide high turn-off ability while maintaining excellent turn-on ability.

FIGS. 42 to 46 show the detailed layout and cross-sectional structure of an MCT in which turn-on buried insulated gate electrodes are arranged at both ends of a turn-off buried insulated gate electrode array. FIG. 42 shows the cathode side layout, and FIGS. 43, 44, 45, and 46 respectively show AA′, BB′, and
They are CC' and DD' sectional views.

The buried insulated gate electrodes are arranged in a striped pattern with fine intervals as shown in FIG. The insulated gate electrode 72 for turn-off is shown in FIG.
As shown in FIG. 2, the p-type channel layer 31 is formed at a depth within the p-type base layer 2, and the n-type emitter layer is alternately formed on the surface of the p-type channel layer 31. 3 and a p+ type base layer 32 are formed. A turn-on buried insulated gate electrode 71 having a depth reaching the n- type base layer 1 is formed at both ends of such an array of turn-off buried insulated gate electrodes 72 . These insulated gate electrodes 71 and 72 are actually drawn out in common to the element surface at the ends of the striped gate electrodes, as shown in FIG. The cathode electrode 5 is provided over the entire surface of the device so as to be in contact with the n-type emitter layer 3 between such buried insulated gate electrodes 7 (FIG. 44), and also in contact with the p+-type base layer 32.

[0078]

As explained above, according to the present invention, the threshold voltage distribution of the insulated gate portion, the array of buried insulated gate electrodes with minute intervals, and the emitters arranged alternately in striped minute dimensions can be improved. By embedding an insulating film between the layer and the base layer, it is possible to obtain a power semiconductor element with an insulated gate that has both high turn-on ability and high turn-off ability.

[Brief explanation of the drawing]

FIG. 1 is a layout and cross-sectional view showing an MCT according to an embodiment of the present invention in which a threshold distribution is given to a turn-off channel.

FIG. 2 is a layout diagram of one element of the same embodiment.

FIG. 3 is a diagram showing gate current waveforms during turn-off of current-driven GTO and MCT.

FIG. 4 is a diagram showing a layout of an MCT of another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 5 is a diagram showing a layout of an MCT of still another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 6 is a diagram showing the main structure of an MCT of another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 7 is a diagram showing the main structure of an MCT according to another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 8 is a diagram showing the main structure of an MCT of another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 9 is a diagram showing the main structure of an MCT of another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 10 is a diagram showing the main structure of an MCT of another embodiment in which a threshold distribution is given to a turn-off channel.

FIG. 11 is a diagram showing the main structure of an MCT in an example in which an insulated gate structure is introduced on the anode side.

FIG. 12 is a diagram showing an example of an element structure suitable for applying the present invention.

FIG. 13 is a diagram showing an example MCT in which the turn-off gate has a buried structure.

FIG. 14 is a diagram showing an MCT of an embodiment employing a further improved buried gate structure.

FIG. 15 is a diagram showing an MCT of an embodiment employing a further improved buried gate structure.

16 is a diagram showing an example of a turn-off gate voltage waveform and gate current waveform in the MCT of the embodiment of FIG. 1. FIG.

17 is a diagram showing an example of a turn-off gate voltage waveform in the MCT of the embodiment shown in FIG. 9; FIG.

FIG. 18 is a diagram for explaining one method of providing a threshold voltage distribution.

FIG. 19 is a diagram showing turn-off loss according to the present invention in comparison with a conventional example.

FIG. 20 is a diagram showing a comparison of the maximum turn-off current density with a conventional example.

FIG. 21 is a diagram showing an MCT of an embodiment in which a gate driving section using an optical trigger is integrated.

FIG. 22 is a diagram showing an MCT of an example modified from FIG. 14;

FIG. 23 is a diagram showing an IGBT according to an embodiment in which a buried insulated gate structure is adopted on the cathode side.

FIG. 24 is a diagram showing an IGBT according to an embodiment in which a buried insulated gate structure is adopted on the anode side.

FIG. 25 is a diagram showing an IGBT according to an embodiment using a buried insulating film structure at the emitter junction termination portion.

FIG. 26 is a diagram showing a thyristor according to an embodiment employing a similar buried insulating film structure.

FIG. 27 is a diagram showing an example MOSFET employing a similar buried insulating film structure.

FIG. 28 is a diagram showing an example of an emitter short-circuit structure that does not reduce emitter injection efficiency.

FIG. 29 is a diagram showing an example of an emitter short-circuit structure that also does not reduce emitter injection efficiency.

30 is a diagram showing the state of carriers when the element in FIG. 29 is turned on; FIG.

FIG. 31 is a diagram showing the state of carriers when the device of FIG. 29 is turned off;

[Figure 32] Example M with double-sided buried insulated gate structure
A diagram showing CT.

33 is a diagram showing an MCT of an embodiment in which a buried insulated gate for turn-on is provided in addition to FIG. 32; FIG.

FIG. 34 is a diagram showing an example MCT in which the turn-on insulated gate electrode has a planar structure.

35 is a diagram showing an MCT of an example in which a low concentration channel layer is provided in the example of FIG. 29; FIG.

FIG. 36 is a diagram showing an MCT having a double-sided buried insulated gate structure and a low concentration channel layer.

FIG. 37 is a diagram showing an embodiment in which a turn-on buried insulated gate is provided in FIG. 36;

FIG. 38 is a diagram illustrating an embodiment of a transistor with a buried insulated gate structure.

FIG. 39 is a diagram showing an example of an SI thyristor with a buried insulated gate structure.

FIG. 40 is a diagram showing an example of an SI thyristor having a double-sided buried insulated gate structure.

FIG. 41: Example 3 of MCT with buried insulated gate structure
Diagram showing dimensional structure.

FIG. 42 is a diagram showing a more specific layout of an embodiment of an MCT with a buried insulated gate structure.

FIG. 43 is a sectional view taken along line AA' in FIG. 42;

FIG. 44 is a sectional view taken along line BB' in FIG. 42;

FIG. 45 is a sectional view taken along line CC' in FIG. 42;

FIG. 46 is a sectional view taken along line DD' in FIG. 42;

[Explanation of symbols]

1...n-type base layer, 2...p-type base layer, 3...n-type emitter layer, 4...p+ type source layer, 5...Cathode electrode, 6...gate insulating film, 7...Gate electrode, 8... Channel area for turn-off, 9... Channel region for turn-on, 10...n-type buffer layer, 11...p-type emitter layer, 12...Anode electrode, 13...n+ type source layer, 14...gate insulating film, 15...gate electrode, 16... Channel region for turn-off, 20... Optical trigger drive unit, 21, 22...channel region, 23...Embedded insulating film. 30...n-type source layer, 31...p-type channel layer, 32...p+ type layer, 33...n-type channel layer, 34...n+ type layer, 35...p-type source layer, 37...p-type base layer, 38...n+ type drain layer.

Claims (4)

[Claims] 1. A power semiconductor device in which at least one gate portion for turn-off or turn-on has an insulated gate structure and is arranged dispersedly on a semiconductor device pellet, wherein at least one gate portion for turn-on or turn-off has an insulated gate structure. A power semiconductor device with an insulated gate, characterized in that two or more different threshold voltages are distributed in different parts on a pellet. 2. A power semiconductor device in which at least one gate portion for turn-off or turn-on has an insulated gate structure and is distributed over a semiconductor device pellet, wherein at least one gate portion for turn-on or turn-off is arranged in stripes. A buried insulated gate structure having a shaped pattern is characterized in that a region where a carrier discharge channel is formed adjacent to one side of the buried insulated gate and an emitter region adjacent to the other side of the buried insulated gate are alternately arranged with minute intervals. Power semiconductor device with gate. 3. In a power semiconductor device in which at least one gate portion for turn-off or turn-on has an insulated gate structure and is distributed over a semiconductor device pellet, an emitter that is in contact with an emitter electrode side and injects carriers when turned on. A power supply device with an insulated gate, characterized in that layers and a base layer for discharging carriers at turn-off are arranged alternately with minute intervals, and an insulating film is embedded between the emitter layer and the base layer. semiconductor element. 4. A power semiconductor device in which at least one of the turn-off and turn-on gate portions has an insulated gate structure and is distributed over a semiconductor device pellet, wherein at least the turn-off gate portion has a plurality of stripe-like patterns. The base region adjacent to one side of each buried insulated gate and the emitter region adjacent to the other side of each buried insulated gate are arranged alternately, and the impurity concentration and width of the base layer between the buried insulated gates are 1. A power semiconductor device with an insulated gate, characterized in that carrier extraction resistance is set to be substantially controlled by gate voltage application.