JPH04226097A - Manufacture of multilayer wiring board - Google Patents
Manufacture of multilayer wiring boardInfo
- Publication number
- JPH04226097A JPH04226097A JP10553391A JP10553391A JPH04226097A JP H04226097 A JPH04226097 A JP H04226097A JP 10553391 A JP10553391 A JP 10553391A JP 10553391 A JP10553391 A JP 10553391A JP H04226097 A JPH04226097 A JP H04226097A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- film
- thick
- board section
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims abstract description 51
- 239000010409 thin film Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 30
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 238000005245 sintering Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 238000005530 etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000003746 surface roughness Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、多層配線に用いる配線
基板の製造方法に係るもので特に薄膜・厚膜混成方式の
配線基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wiring board used for multilayer wiring, and more particularly to a method of manufacturing a wiring board of a thin film/thick film hybrid type.
【０００２】0002
【従来の技術】電子計算機等に用いる大容量の混成集積
回路用多層配線基板として、一般に配線を厚膜印刷焼結
方式で形成し、基板および層間絶縁物としてアルミナセ
ラミックを用いた基板が用いられている。ところが近年
、電子計算機において高機能，高速化の要請が強く、こ
の結果大配線容量の混成集積回路用基板が要求されるよ
うになった。厚膜アルミナセラミック基板では、配線密
度が印刷工程の精度で限定され（最小可能配線ピッチ１
５０μｍ）るため、配線層５〜１０層、絶縁層５〜１０
層の多層で基板寸法１００ｍｍ の基板が出現してい
る。層数の増大は各層間の接続点数を大幅に増すため、
基板製造歩留の大幅低下をもたらすという欠点がある。
また基板の大型化は、信号伝送路の増大をきたすため高
速化が図れない。[Prior Art] As a multilayer wiring board for large-capacity hybrid integrated circuits used in electronic computers, etc., a board is generally used in which wiring is formed by a thick film printing and sintering method, and alumina ceramic is used as the board and interlayer insulator. ing. However, in recent years, there has been a strong demand for higher functionality and higher speed in electronic computers, and as a result, a substrate for hybrid integrated circuits with a large wiring capacity has become required. For thick-film alumina ceramic substrates, the wiring density is limited by the precision of the printing process (minimum possible wiring pitch 1
50 μm), 5 to 10 wiring layers, 5 to 10 insulating layers
Multilayer substrates with a substrate size of 100 mm have appeared. Increasing the number of layers greatly increases the number of connection points between each layer, so
This method has the drawback of significantly lowering the substrate manufacturing yield. Furthermore, increasing the size of the board increases the number of signal transmission paths, making it impossible to increase the speed.
【０００３】そこで、配線形成を半導体工業のプロセス
である薄膜ホトプロセスを用いることが試みられている
。薄膜プロセスを用いて多層化した基板では、電子計算
機用混成集積回路基板として必要なコネクタの着脱に耐
える数百本の端子をとりだすことは一般に困難である。
この端子に関しては基板裏面全域に焼結タングステンに
Ｎｉメッキしたピン接続部を配列し、この接続部に銀ろ
うあるいははんだろうでリードピンを接続している従来
の厚膜多層配線基板が適している。ところで高密度，高
速化を要する回路領域は論理信号回路である。電源回路
グランド層は、従来の厚膜多層配線の配線密度で十分余
裕がある。したがって、論理信号層を薄膜基板部として
形成し、電源グランド層やリードピン端子部を厚膜基板
部として形成した薄膜−厚膜混成方式で高密度，高速基
板を達成できる。[0003] Therefore, attempts have been made to use thin film photoprocessing, which is a process used in the semiconductor industry, to form interconnections. In a multilayered board using a thin film process, it is generally difficult to extract several hundred terminals that can withstand the attachment and detachment of connectors required for a hybrid integrated circuit board for an electronic computer. For this terminal, a conventional thick film multilayer wiring board is suitable, in which pin connection parts made of sintered tungsten plated with Ni are arranged over the entire back surface of the board, and lead pins are connected to these connection parts with silver solder or solder. By the way, a circuit area that requires high density and high speed is logic signal circuits. The power supply circuit ground layer has sufficient margin with the wiring density of conventional thick-film multilayer wiring. Therefore, a high-density, high-speed substrate can be achieved by a thin film/thick film hybrid method in which the logic signal layer is formed as a thin film substrate part and the power ground layer and lead pin terminal part are formed as a thick film substrate part.
【０００４】薄膜−厚膜混成方式の多層配線基板の製造
は、第１図に示す工程でできる。焼結タングステンから
なる電源・グランド層２リードピン端子部３を含む厚膜
基板部１０を通常の厚膜多層基板の製法であるグリンシ
ード法で形成する。薄膜基板部の配線と接続する厚膜配
線端子４をアルミナ絶縁層５のスルホールに穴うめして
形成しておく。この厚膜基板部１０の上面に薄膜基板部
の配線部となる配線膜６を通常の薄膜プロセスである抵
抗加熱蒸着あるいはスパックにてＡｌあるいはＣｒ／Ｃ
ｕ／Ｃｒで形成し、ネガ型レジストを用いるホトリゾエ
ッチングで配線膜６をパターン化する。このとき配線端
子４と配線パターン６を必ず重ね合せる。厚膜基板部１
０は製造時の焼結収縮にばらつきがあり端子４の位置ば
らつきは基板中心からみてその位置の中心からの距離の
０．６〜１．０％となる。このため、両基板部の接続を
基板全域で図るためには、位置ばらつきの幅を厚膜配線
端子４あるいは配線パターン６の接続部に与えなければ
ならない。このため、配線パターン６は高密度配線化が
図れるホトリゾエッチング工程を用いながら、厚膜配線
基板部の配線密度と同じにしなけれはばならない。この
上に、通常の薄膜プロセスで形成するＳｉＯ２やポリイ
ミド膜を絶縁層７とし、そのスルホール８をホトリゾエ
ッチングで形成する。こののち絶縁層７の上面に配線パ
ターン６１を配線パターン６と同様に形成し更に絶縁層
７１、スルホール８１を絶縁層７、スルホール８と同様
に形成する。これらの工程を繰返して薄膜基板部１１を
形成し、高密度，高速用の多層配線基板となる。A thin film/thick film hybrid type multilayer wiring board can be manufactured by the steps shown in FIG. A thick film substrate section 10 including a power supply/ground layer 2 and a lead pin terminal section 3 made of sintered tungsten is formed by the Grinseed method, which is a conventional thick film multilayer substrate manufacturing method. Thick film wiring terminals 4 to be connected to wiring on the thin film substrate portion are formed by filling through holes in the alumina insulating layer 5. A wiring film 6, which will become the wiring part of the thin film substrate part, is formed on the upper surface of the thick film substrate part 10 using a conventional thin film process such as resistance heating vapor deposition or spacing.
The wiring film 6 is formed of u/Cr and patterned by photolithography using a negative resist. At this time, the wiring terminal 4 and the wiring pattern 6 must be overlapped. Thick film substrate part 1
0 has variations in sintering shrinkage during manufacturing, and variations in the position of the terminals 4 are 0.6 to 1.0% of the distance from the center of the position when viewed from the center of the substrate. Therefore, in order to connect both substrate parts over the entire substrate area, it is necessary to provide a width of positional variation to the connection part of the thick film wiring terminal 4 or the wiring pattern 6. For this reason, the wiring pattern 6 must be made to have the same wiring density as that of the thick film wiring board portion, while using a photolithography etching process that allows high-density wiring. On top of this, an insulating layer 7 is made of SiO2 or polyimide film formed by a normal thin film process, and through holes 8 are formed by photolithography. Thereafter, a wiring pattern 61 is formed on the upper surface of the insulating layer 7 in the same manner as the wiring pattern 6, and an insulating layer 71 and through holes 81 are further formed in the same manner as the insulating layer 7 and the through holes 8. These steps are repeated to form the thin film substrate portion 11, resulting in a high density, high speed multilayer wiring board.
【０００５】[0005]
【発明が解決しようとする課題】この多層配線基板では
高密度化になんら寄与しない厚膜−薄膜接続の適合のた
めの層がパターン６層および絶縁層７と２層要しており
、このため工程が冗長され、歩便り低下の原因だけとな
っている。[Problems to be Solved by the Invention] This multilayer wiring board requires two layers, 6 pattern layers and an insulating layer 7, for adapting thick film-thin film connections, which do not contribute to high density. The process is redundant, which only causes a decrease in walking time.
【０００６】また、第１図の配線端子４には、パターン
６で覆われない個所が必ず発生する。これはパターン６
のパターン化時のエッチング液が配線端子４に触れるた
め、パターン６のエッチングへの悪影響や、また配線端
子４を酸化させ、信頼性を落す原因となる。また厚膜基
板部１０の表面粗さは通常３〜４μｍあるため、ホトリ
ゾエッチングのパターン６のパターン化が困難であり、
表面粗さ３〜４μｍ上のパターン６の配線抵抗の安定性
が悪いことがわかっている。Furthermore, in the wiring terminal 4 shown in FIG. 1, there will always be a portion that is not covered with the pattern 6. This is pattern 6
Since the etching solution during patterning comes into contact with the wiring terminals 4, this has an adverse effect on the etching of the pattern 6, and also causes the wiring terminals 4 to be oxidized, reducing reliability. In addition, since the surface roughness of the thick film substrate portion 10 is usually 3 to 4 μm, it is difficult to pattern the pattern 6 by photoliso etching.
It is known that the stability of the wiring resistance of the pattern 6 with a surface roughness of 3 to 4 μm is poor.
【０００７】本発明の目的は、以上の製造上の欠点を除
き、薄膜・厚膜混成方式の高密度，高速用の多層配線基
板の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a multilayer wiring board of a thin film/thick film hybrid type for high density and high speed use, eliminating the above-mentioned manufacturing disadvantages.
【０００８】[0008]
【課題を解決するための手段】上記目的は、厚膜配線基
板部と薄膜配線基板部とからなる混成構成の多層配線基
板の製造方法において、内部にスルーホール導体配線を
有する厚膜配線基板部の表面に絶縁膜と薄膜導体配線か
らなる薄膜配線基板部を形成した後、前記厚膜配線基板
部り他の表面にリードピンを付けることにより達成され
る。[Means for Solving the Problems] The above object is to provide a method for manufacturing a multilayer wiring board having a hybrid structure consisting of a thick film wiring board part and a thin film wiring board part, in which a thick film wiring board part has through-hole conductor wiring inside. This is achieved by forming a thin film wiring board section consisting of an insulating film and thin film conductor wiring on the surface of the thick film wiring board section, and then attaching lead pins to the other surface of the thick film wiring board section.
【０００９】[0009]
【作用】多層配線基板において、厚膜配線基板部に一方
の面に薄膜配線基板部を形成した後に他方の面にリード
ピンを付けるため、薄膜配線基板部の形成時には厚膜配
線基板部の薄膜配線基板部を形成しない他方の面はフラ
ットになるため高精度・高密度の薄膜配線基板部を形成
できる。[Operation] In a multilayer wiring board, after forming a thin film wiring board part on one side of the thick film wiring board part, lead pins are attached to the other side, so when forming the thin film wiring board part, the thin film wiring board part of the thick film wiring board part is attached. Since the other surface on which the substrate portion is not formed is flat, a thin film wiring substrate portion with high precision and high density can be formed.
【００１０】0010
【実施例】以下第２図に示す実施例により、本発明を具
体的に説明する。同図（ａ）は厚膜配線基板部を作る方
法を説明する図、同図（ｂ）は厚膜配線基板部に薄膜配
線基板部を形成する方法を説明する図である。[Example] The present invention will be specifically explained below with reference to an example shown in FIG. 3A is a diagram illustrating a method for forming a thick film wiring board section, and FIG. 2B is a diagram illustrating a method for forming a thin film wiring board section on a thick film wiring board section.
【００１１】図に示す１０は、タングステンの焼結体か
らなる電源配線層やグランド層２を含む、グリンシート
法で製造したアルミナ厚膜多層配線基板部１０である。
配線端子４はアルミナ絶縁層５のスルホールにタングス
テンペースドを穴うめ焼結して形成されている。配線端
子４の径は、接続する薄膜のスルホール径に（グリンシ
ート法での焼結収縮ばらつき０．６〜１．０％Ｘ基板の
長辺寸法×１／２）を加えた径とする。基板寸法を５０
ｃｍ 、薄膜スルホール径を５０μｍとすると、端子
の径は２５０μｍ前後とする。基板部１０の裏面には焼
結タングステンパッドに銀ろうで接続されたリードピン
９がついている。配線端子４はアルミナ絶縁層５の上面
と同一平面もしくは１０μｍ以下で突出するように形成
されている。この基板部１０にポリイミド樹脂をスピン
コーティング方式で塗布し、熱硬化して絶縁層７を形成
する。この絶縁層７にネガ型レジスト（例えば東京応化
製のＯＭＲ８３）をコーティングし、レジストを紫外線
露光でパターン化し、湿式エッチングで配線端子４の上
部の絶縁層７にスルホール８を形成する。スルホール８
の形成にネガ型レジストを用いるのは、厚膜基板部１が
硬く、そり，うねりがあるため、もろいポジ型レジスト
では露光時にマスクとの接触でレジストがはく離し、絶
縁層７にピンホールが発生するのを避けることにある。
そして配線端子４の上面をアルミナ絶縁層の上面より沈
めないのは、ネガ型レジストを用いるので、露光時にマ
スクと間隙があくと紫外光のまわりこみでスルホール８
が形成できなくなるのを避けるためである。スルホール
８形成後、抵抗加熱あるいはエレクトロンビーム蒸着ス
パッタなどでアルミあるいはチタン＋銅＋チタン膜６を
形成し通常のホトリゾ工程でパターン化する。この配線
６は絶縁層７の上でのパターン化のため表面粗さの大き
い厚膜多層配線基板部１０（表面粗さ４〜６μｍ）上と
異なり、２０〜４０μｍピッチでの配線化ができ、厚膜
基板部１０の影響を受けない。そして配線パターン６の
パターン化の際にそのエッチング液が配線端子４に触れ
ることはない。以降、この上部にポリイミド樹脂層７１
と配線層６１を繰返し形成し、薄膜多層配線基板部１１
を形成する。したがって、厚膜・薄膜の適合層７一層と
なる。これにより高密度配線の多層配線基板が形成され
る。なお、リードピン９は、薄膜配線基板部１１を形成
したあとに付けてもよい。Reference numeral 10 shown in the figure is an alumina thick film multilayer wiring board section 10 manufactured by the green sheet method, including a power supply wiring layer and a ground layer 2 made of sintered tungsten. The wiring terminals 4 are formed by filling through holes in the alumina insulating layer 5 with tungsten paste and sintering them. The diameter of the wiring terminal 4 is the diameter of the through hole of the thin film to be connected plus (0.6 to 1.0% sintering shrinkage variation in the green sheet method x long side dimension of the substrate x 1/2). The board size is 50
cm, and the diameter of the thin film through hole is 50 μm, the diameter of the terminal is approximately 250 μm. A lead pin 9 connected to a sintered tungsten pad with silver solder is attached to the back surface of the substrate part 10. The wiring terminal 4 is formed to be flush with the upper surface of the alumina insulating layer 5 or to protrude by 10 μm or less. A polyimide resin is applied to this substrate portion 10 by a spin coating method and thermally cured to form an insulating layer 7. This insulating layer 7 is coated with a negative resist (for example, OMR83 manufactured by Tokyo Ohka Co., Ltd.), the resist is patterned by UV exposure, and through holes 8 are formed in the insulating layer 7 above the wiring terminals 4 by wet etching. Through hole 8
The reason why a negative resist is used for forming the thick film substrate 1 is that the thick film substrate portion 1 is hard and has warps and undulations, whereas a brittle positive resist will peel off when it comes into contact with the mask during exposure, causing pinholes to form in the insulating layer 7. The goal is to prevent it from happening. The reason why the top surface of the wiring terminal 4 is not sunk below the top surface of the alumina insulating layer is because a negative resist is used, so if there is a gap between the mask and the mask during exposure, ultraviolet light will enter the through hole 8.
This is to avoid the inability to form. After forming the through holes 8, an aluminum or titanium+copper+titanium film 6 is formed by resistance heating or electron beam evaporation sputtering, and patterned by a normal photolithography process. Since this wiring 6 is patterned on the insulating layer 7, it can be patterned at a pitch of 20 to 40 μm, unlike on the thick film multilayer wiring board part 10 (surface roughness of 4 to 6 μm), which has a large surface roughness. It is not affected by the thick film substrate section 10. When patterning the wiring pattern 6, the etching solution does not come into contact with the wiring terminals 4. Thereafter, a polyimide resin layer 71 is formed on top of this.
and the wiring layer 61 are repeatedly formed to form the thin film multilayer wiring board section 11.
form. Therefore, there is only one compatible layer 7 of thick and thin films. As a result, a multilayer wiring board with high-density wiring is formed. Note that the lead pins 9 may be attached after the thin film wiring board section 11 is formed.
【００１２】0012
【発明の効果】以上のように、本発明によれば、従来の
厚膜多層配線基板より２〜３倍の高密度化が図れる。従
って配線層数，スルホール接続数が低減でき、製品歩留
りが向上し、更にコネクタ着脱に耐える多端子のとりだ
しが容易に図れる。As described above, according to the present invention, the density can be increased two to three times as much as that of the conventional thick film multilayer wiring board. Therefore, the number of wiring layers and through-hole connections can be reduced, product yield is improved, and multiple terminals that can withstand connector attachment and detachment can be easily taken out.
【図１】薄膜混成多層基板の従来製造方法を説明する図
、FIG. 1 is a diagram illustrating a conventional manufacturing method of a thin film hybrid multilayer substrate,
【図２】本発明の実施例を説明する図。FIG. 2 is a diagram illustrating an embodiment of the present invention.
１０…厚膜多層配線基板部、１１…薄膜多層配線基板部
、４…厚膜基板部の配線端子、５…厚膜基板部の絶縁層
、７，７１…薄膜基板部の絶縁層、６，６１…薄膜基板
部の配線、９…リードピン。DESCRIPTION OF SYMBOLS 10... Thick film multilayer wiring board part, 11... Thin film multilayer wiring board part, 4... Wiring terminal of thick film board part, 5... Insulating layer of thick film board part, 7, 71... Insulating layer of thin film board part, 6, 61... Wiring of thin film substrate section, 9... Lead pin.
Claims (1)
成の多層配線基板の製造方法において、内部にスルーホ
ール導体配線を有する厚膜配線基板部の表面に絶縁膜と
薄膜導体配線からなる薄膜配線基板部を形成した後、前
記厚膜配線基板部の他の表面にリードピンを付けること
を特徴とする多層配線基板の製造方法。1. In a method for manufacturing a multilayer wiring board having a hybrid configuration consisting of a thick film wiring board part and a thin film wiring board part, a thin film wiring made of an insulating film and a thin film conductor wiring is formed on the surface of the thick film wiring board part having through-hole conductor wiring inside. A method for manufacturing a multilayer wiring board, characterized in that after forming the substrate part, lead pins are attached to the other surface of the thick film wiring board part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3105533A JPH0810792B2 (en) | 1991-05-10 | 1991-05-10 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3105533A JPH0810792B2 (en) | 1991-05-10 | 1991-05-10 | Method for manufacturing multilayer wiring board |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17141281A Division JPS5873193A (en) | 1981-10-28 | 1981-10-28 | Method of producing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04226097A true JPH04226097A (en) | 1992-08-14 |
| JPH0810792B2 JPH0810792B2 (en) | 1996-01-31 |
Family
ID=14410230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3105533A Expired - Lifetime JPH0810792B2 (en) | 1991-05-10 | 1991-05-10 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810792B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753595B1 (en) * | 2003-01-14 | 2004-06-22 | Silicon Integrated Systems Corp | Substrates for semiconductor devices with shielding for NC contacts |
| JP2015162607A (en) * | 2014-02-27 | 2015-09-07 | 新光電気工業株式会社 | Wiring board, semiconductor device and wiring board manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5028655A (en) * | 1973-07-17 | 1975-03-24 | ||
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
| JPS5642399A (en) * | 1979-09-13 | 1981-04-20 | Fujitsu Ltd | System for producing multilayer wiring board |
-
1991
- 1991-05-10 JP JP3105533A patent/JPH0810792B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5028655A (en) * | 1973-07-17 | 1975-03-24 | ||
| JPS5328266A (en) * | 1976-08-13 | 1978-03-16 | Fujitsu Ltd | Method of producing multilayer ceramic substrate |
| JPS5642399A (en) * | 1979-09-13 | 1981-04-20 | Fujitsu Ltd | System for producing multilayer wiring board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753595B1 (en) * | 2003-01-14 | 2004-06-22 | Silicon Integrated Systems Corp | Substrates for semiconductor devices with shielding for NC contacts |
| JP2015162607A (en) * | 2014-02-27 | 2015-09-07 | 新光電気工業株式会社 | Wiring board, semiconductor device and wiring board manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810792B2 (en) | 1996-01-31 |
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