JPH04225556A - Production of capacitive element - Google Patents

Abstract

PURPOSE:To form an capacitive element which is not influenced by the transistor characteristic of a memory cell which constitutes a large capacity DRAM. CONSTITUTION:The method consists of a process of forming a first insulating film 26 on a semiconductor substrate 21, a process of forming a contact window 27 on the prescribed area of the first insulating film 26, a process of forming a second insulating film 28 on the first insulating film 26, a process of anisotropically etching the second insulating film 28 and leaving the second insulating film 28 on the side wall of the contact window 27, a process of forming a bottom electrode 29 on the left insulating film 28, a process of forming a dielectric film 30 on the electrode 29 and a process of forming a top electrode 31 on the film 30.

Description

[Detailed description of the invention]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitive element. [0002] In a large-capacity dynamic random access memory (hereinafter referred to as dynamic memory) with a storage capacity in the megabit class, as the number of elements becomes larger, the storage capacity per semiconductor memory element (hereinafter referred to as memory) increases. area has become smaller. As a result, in order to secure the capacity of the memory cell, instead of the conventional planar capacitor (planar capacitance element) formed on the surface of the substrate, polycrystalline silicon was used as one electrode by using a large step on the semiconductor substrate.
Stacked capacitors in which a capacitive insulating film is formed on this polycrystalline silicon are being used. [0003] An example of a conventional method for manufacturing a capacitive element used in semiconductor memory devices and the like will be described below with reference to FIGS. First, as shown in FIG. 2(a), P-type (1
00) on a silicon substrate 1 with a film thickness of 5 by a well-known method.
A selective oxide film (LOCOS film) 2 with a thickness of about 00 nm is formed. Next, the surface of the silicon substrate 1 is thermally oxidized to have a film thickness of 18
A gate oxide film 3 having a thickness of 200 nm is formed, and then a polycrystalline silicon film having a thickness of 200 nm, for example, which will become the gate electrode 4 is formed by vapor phase growth. This polycrystalline silicon film is doped with impurities to lower its resistance. Doping methods include ion-implanting impurities after forming a non-doped polycrystalline silicon film, or diffusing impurities from the phase using an impurity gas, or using a gas when growing a polycrystalline silicon film using a CVD device. A method is used in which a gas containing impurity elements is mixed and a polycrystalline silicon film containing impurities is formed simultaneously with growth. Thereafter, the polycrystalline silicon film is etched using normal photolithography using a photoresist with windows opened in a predetermined area as a mask to form a gate electrode 4 of polycrystalline silicon. After that, ions are implanted into the entire surface of the silicon substrate 1 to form a diffusion layer (diffusion layer wiring).
form 5. At this time, the polycrystalline silicon gate electrode 4
Ions are not implanted into the silicon substrate 1 directly under the selective oxide film 2. Furthermore, a film thickness of 150n was obtained using the vapor phase growth method.
After forming a CVD oxide film 6 of m thickness, reactive ion etching is performed on the CVD oxide film 6 using a mixed gas of CHF3, O2, and Ar using a photoresist with windows opened in a predetermined area using photolithography as a mask, and diffusion is performed. Contact windows 7 are formed at predetermined locations on layer 5 . Next, a polycrystalline silicon film 8 is formed by a vapor phase growth method, and conductivity is increased by diffusing impurities such as phosphorus into this polycrystalline silicon film 8, and then reactive ion etching technology is applied using a photoresist as a mask. It is processed into a predetermined shape and used as a lower electrode of a capacitive element. Next, as shown in FIG. 2B, a capacitive insulating film 9 such as a silicon nitride film is formed on the surface of this polycrystalline silicon film 8 by vapor phase growth. A polycrystalline silicon film 10 is formed thereon by a vapor phase growth method, and an impurity such as phosphorus is diffused into this polycrystalline silicon film 10 to increase its conductivity and serve as the upper electrode of the capacitive element. Thereafter, an interlayer insulating film 11, a contact hole 12, and an aluminum wiring 13 are formed to form a capacitive element. [0006] However, in the above-mentioned conventional configuration, if misalignment occurs in photolithography when forming the contact window 7, the contact window 7 approaches the gate electrode 4 of the polycrystalline silicon film. contact window 7
There is a problem in that impurities such as phosphorus from the polycrystalline silicon film 8 diffuse into the transistor region through the process, causing variations in the characteristics of the formed transistor. The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a method for manufacturing a capacitive element in which transistor characteristics are stabilized by forming fine contact windows. Means for Solving the Problems In order to achieve this object, the method for manufacturing a capacitive element of the present invention includes a step of forming a first insulating film on a semiconductor substrate, and a step of forming a first insulating film on a semiconductor substrate. forming a contact window in a predetermined region of the film; forming a second insulating film on the first insulating film; and etching the second insulating film anisotropically to form the contact window. leaving the second insulating film on the sidewalls of the first and second insulating films;
forming a lower electrode on the insulating film; forming a third insulating film on the surface of the lower electrode; and forming an upper electrode on the third insulating film. ing. [0009] With this configuration, a capacitive element having a fine contact window can be formed. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process cross-sectional view of a method for manufacturing a capacitive element according to an embodiment of the present invention. First, as shown in FIG. 1A, a selective oxide film (LOCOS film) 22 with a thickness of about 500 nm is formed on one main surface of a P-type (100) silicon substrate 21 by a well-known method. Next, the surface of the silicon substrate 21 is thermally oxidized to form a gate oxide film 2 with a thickness of 18 nm.
3 is formed, and a film thickness of 20 mm is formed thereon by vapor phase growth.
A polycrystalline silicon film of nm thickness is formed. This polycrystalline silicon film is doped with impurities to lower its resistance. Thereafter, the polycrystalline silicon film is etched using ordinary photolithography using a photoresist with windows opened in a predetermined region as a mask to form a gate electrode 24 of polycrystalline silicon. After that, ions are implanted into the entire surface and the diffusion layer (
A diffusion layer wiring) 25 is formed. At this time, the gate electrode 24
Ions are not implanted into the silicon substrate 21 directly under the selective oxide film 22. Furthermore, after forming a CVD oxide film 26 to a thickness of 250 nm at a growth temperature of approximately 710° C. using a mixed gas of TEOS (tetraethoxysilane) and oxygen, for example, the CVD oxide film 26 is coated with, for example, CHF3 using a photoresist as a mask.
Reactive ion etching is performed using a mixed gas of O2 and Ar, and a diameter of 0.85
A contact window 27 of μm is formed. Next, a CVD oxide film 28 is formed at a thickness of 270 mm under the same conditions as for the formation of the CVD oxide film 26.
nm is formed. This CVD oxide film 28 is coated with CHF3 and O2.
Reactive ion etching is performed to a film thickness of 300 nm using a mixed gas of and Ar. Since this etching is anisotropic etching, the CVD oxide film 28 is etched away, but the inner wall of the contact window 27 has a thickness of 0.15 μm.
An oxide film 28 remains. That is, a contact window with a diameter of 0.55 μm is formed. Next, as shown in FIG. 1(b), a polycrystalline silicon film 29 is formed by vapor phase growth, and conductivity is increased by diffusing impurities such as phosphorus into this polycrystalline silicon film 29. Thereafter, using a photoresist as a mask, it is processed into a predetermined shape by reactive ion etching technology to form a lower electrode (indicated by 29) of the capacitive element. Next, as shown in FIG. 1C, a capacitive insulating film 30 such as a silicon nitride film is formed on the surface of this polycrystalline silicon film 29 by vapor phase growth. A polycrystalline silicon film 31 is formed thereon by a vapor phase growth method, and conductivity is increased by diffusing impurities such as phosphorus into this polycrystalline silicon film 31 to form an upper electrode (indicated by 31) of a capacitive element.
shall be. After that, the interlayer insulating film 32, the contact window 33,
A capacitive element is formed by forming an aluminum wiring 34. Note that the CVD oxide film 26 has a thickness of 200 nm.
If the thickness is less than m, the CVD oxide film 28 will be overetched when it is etched back, so that the CVD oxide film 26 will also be partially etched and become thinner, with the final film thickness becoming 150 nm or less. This causes problems such as insufficient breakdown voltage between the two layers of polycrystalline silicon films. Furthermore, if the thickness of the CVD oxide film 26 exceeds 300 nm, the step difference on the substrate becomes large, making it difficult to form aluminum wiring. Also C
If the thickness of the VD oxide film 28 is less than 200 nm, a sufficient sidewall film will not be formed on the inner wall of the contact window 27, and if the thickness exceeds 300 nm, the CVD oxide film 2 will be etched back.
The film thickness of No. 8 is 350 nm or more. In this case, considering that the variation in the film thickness of the CVD oxide films 26 and 28 is about ±5%, and the variation in the etching rate of dry etching is about ±5%, the final carbon
The thickness of the VD oxide film becomes 150 nm or less, which causes problems such as insufficient breakdown voltage between the two layers of polycrystalline silicon films. Therefore, it is desirable that the thicknesses of both the CVD oxide films 26 and 28 be within the range of 200 to 300 nm. Furthermore, in this example, a polycrystalline silicon film was used as the upper or lower electrode of the capacitive element.
A laminated film of metal silicide or polycrystalline silicon and metal silicide may be used. As described above, according to the method for manufacturing a capacitive element of the present invention, a capacitive element is manufactured using, for example, the conventional technique, and the distance between the end of the gate and the contact window is 0.1 μm.
Even if the spacing is narrowed to a certain extent, a spacing of about 0.25 μm can be secured, so that there is no change in the characteristics of the transistor, and it is possible to manufacture a capacitive element with stable characteristics.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of a method for manufacturing a capacitive element in an embodiment of the present invention.

[Figure 2] Process cross-sectional diagram of a conventional capacitive element manufacturing method

[Explanation of symbols]

21 P-type silicon substrate (semiconductor substrate) 26 CV
D oxide film (first insulating film) 27 Contact window 28 CVD oxide film (second insulating film) 29 Polycrystalline silicon film (lower electrode) 30 Capacitive insulating film

Claims (4)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate, a step of forming a contact window in a predetermined region of the first insulating film, and a step of forming a first insulating film on the first insulating film. forming a second insulating film, etching the second insulating film anisotropically to leave the second insulating film on the side wall of the contact window, and removing the first and second insulating films. Manufacturing a capacitive element, comprising: forming a lower electrode on top; forming a third insulating film on the surface of the lower electrode; and forming an upper electrode on the third insulating film. Method. 2. The thickness of the first insulating film is 200 to 300 nm.
The method for manufacturing a capacitive element according to claim 1, characterized in that: 3. The thickness of the second insulating film is 200 to 300 nm.
The method for manufacturing a capacitive element according to claim 1, characterized in that: 4. The method of manufacturing a capacitive element according to claim 1, wherein the lower electrode or the upper electrode is made of polycrystalline silicon, metal silicide, or a laminated film of polycrystalline silicon and metal silicide.