JPH04225222A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04225222A JPH04225222A JP2407653A JP40765390A JPH04225222A JP H04225222 A JPH04225222 A JP H04225222A JP 2407653 A JP2407653 A JP 2407653A JP 40765390 A JP40765390 A JP 40765390A JP H04225222 A JPH04225222 A JP H04225222A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- disk
- electrons
- supplied
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 abstract description 9
- 235000012431 wafers Nutrition 0.000 description 35
- 238000010586 diagram Methods 0.000 description 6
- 238000010884 ion-beam technique Methods 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 241000478345 Afer Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Welding Or Cutting Using Electron Beams (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
係り,特にイオン注入工程におけるウエハのチャージア
ップ防止方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for preventing wafer charge-up during an ion implantation process.
【0002】MOS デバイスの微細化によるゲート絶
縁膜の薄膜化により, イオン注入によるウエハのチャ
ージアップでゲート絶縁膜の劣化が多発し,これがデバ
イスの信頼性の点で大問題となり対策が望まれている。As the gate insulating film becomes thinner due to the miniaturization of MOS devices, the gate insulating film frequently deteriorates due to the charge-up of the wafer due to ion implantation.This is a major problem in terms of device reliability, and countermeasures are desired. There is.
【0003】このために,イオン注入中に発生するウエ
ハ上の正電荷に対し電子を供給することで中和している
が, 逆に電子の過剰供給から負電荷のチャージアップ
がゲート絶縁膜の劣化を引き起こすこともあり,電子の
供給量は常に適正であるように制御する必要がある。For this reason, the positive charges generated on the wafer during ion implantation are neutralized by supplying electrons, but conversely, the oversupply of electrons causes negative charges to build up on the gate insulating film. This may cause deterioration, so the amount of electrons supplied must be controlled so that it is always appropriate.
【0004】本発明はこの必要性に対応した電子供給量
の制御方法として利用できる。The present invention can be used as a method for controlling the amount of electron supply that meets this need.
【0005】[0005]
【従来の技術】図3は従来例を説明する構成図である。
図において,1はウエハ,2はディスク,3はイオンビ
ーム,4はエレクトロンシャワーの電子供給用フィラメ
ント,5はディスク電流計である。2. Description of the Related Art FIG. 3 is a block diagram illustrating a conventional example. In the figure, 1 is a wafer, 2 is a disk, 3 is an ion beam, 4 is a filament for supplying electrons for an electron shower, and 5 is a disk ammeter.
【0006】従来のイオン注入装置においては,ウエハ
1を保持したディスク2にイオンビーム3が照射される
のでディスク2に正電荷が溜まり,ディスク2とGND
間に電流 Idiscが流れる。そのため, Idi
sc=0となるようにイオンビーム3と同時にフィラメ
ント4より電子をディスク2に供給することで,ディス
ク2全体の電荷が中和され,これにともないウエハ上の
電荷も中和されると考えられていた。In the conventional ion implantation apparatus, since the ion beam 3 is irradiated onto the disk 2 holding the wafer 1, positive charges are accumulated on the disk 2, and the disk 2 and GND are irradiated with the ion beam 3.
A current Idisc flows between them. Therefore, Idi
It is thought that by supplying electrons from the filament 4 to the disk 2 at the same time as the ion beam 3 so that sc = 0, the charge on the entire disk 2 is neutralized, and the charge on the wafer is also neutralized accordingly. was.
【0007】ところが,実際はディスク表面とウエハ表
面は絶縁性が異なり表面の電荷量に差ができることから
,ディスク全体を中和しても必ずしもウエハ上の電荷が
中和されるとは限らない。However, in reality, the disk surface and the wafer surface have different insulating properties, resulting in a difference in the amount of charge on the surface, so even if the entire disk is neutralized, the charge on the wafer is not necessarily neutralized.
【0008】[0008]
【発明が解決しようとする課題】従来例では,ディスク
全体の電荷のみを制御していたため,ディスクとウエハ
の表面状態によっては,ウエハ表面の電荷が完全に中和
されずに正や負に帯電し,ゲート絶縁膜の劣化を引き起
こしていた。[Problem to be solved by the invention] In the conventional example, only the charge on the entire disk was controlled, so depending on the surface conditions of the disk and wafer, the charge on the wafer surface could not be completely neutralized and could become positively or negatively charged. This caused deterioration of the gate insulating film.
【0009】本発明はイオン注入中にウエハ表面に帯電
した電荷を完全に中和することを目的とする。An object of the present invention is to completely neutralize the charges that are accumulated on the wafer surface during ion implantation.
【0010】0010
【課題を解決するための手段】上記課題の解決は,ディ
スクに保持されたウエハ上に電子を供給しながら該ウエ
ハにイオン注入を行う際に,該ウエハを該ディスクと電
気的に絶縁し,該ウエハと接地電位間の電流を測定し,
該電流値を電子供給手段に帰還して電子供給量を制御し
,該ウエハの帯電を防止する半導体装置の製造方法によ
り達成される。[Means for Solving the Problem] The above problem is solved by electrically insulating the wafer from the disk when ion implantation is performed on the wafer held by the disk while supplying electrons to the wafer. Measure the current between the wafer and ground potential,
This is achieved by a semiconductor device manufacturing method that controls the amount of electron supply by feeding back the current value to the electron supply means to prevent the wafer from being charged.
【0011】[0011]
【作用】本発明はウエハに注入したイオン量に対しての
み電子供給量を制御することでウエハ表面に帯電した電
荷を完全に中和するようにしたものである。[Operation] The present invention completely neutralizes the charges on the wafer surface by controlling the amount of electrons supplied only with respect to the amount of ions implanted into the wafer.
【0012】図1は本発明の原理説明図である。図にお
いて,5はディスク電流計,6はウエハ電流計である。
ディスク2とウエハ1は電気的に絶縁され,打ち込まれ
た正イオンに対し,ディスク2とGND 間に電流 I
discが流れ,また, ウエハ1とGND 間に電流
Iwafer が流れる。そこで,本発明では Iw
afer =0となるようにフィラメント4に供給する
電流に帰還をかけて電子の供給を制御することでウエハ
上の電荷を完全に中和する。FIG. 1 is a diagram explaining the principle of the present invention. In the figure, 5 is a disk ammeter and 6 is a wafer ammeter. The disk 2 and the wafer 1 are electrically insulated, and a current I is generated between the disk 2 and GND for the positive ions implanted.
disc flows, and a current Iwafer flows between the wafer 1 and GND. Therefore, in the present invention, Iw
By controlling the supply of electrons by applying feedback to the current supplied to the filament 4 so that afer =0, the charges on the wafer are completely neutralized.
【0013】[0013]
【実施例】図2は本発明の一実施例を説明する構成図で
ある。図にといて,1はウエハ,2はディスク,3はイ
オンビーム,4はフィラメント,5はディスク電流計,
6はウエハ電流計,7はウエハクランプ,8はフィラメ
ントの可変電源,9は電子の加速電源,10はファラデ
ーカップ, 11はバイアスリング, 12はビーム電
流計である。Embodiment FIG. 2 is a block diagram illustrating an embodiment of the present invention. In the figure, 1 is a wafer, 2 is a disk, 3 is an ion beam, 4 is a filament, 5 is a disk ammeter,
6 is a wafer ammeter, 7 is a wafer clamp, 8 is a filament variable power source, 9 is an electron acceleration power source, 10 is a Faraday cup, 11 is a bias ring, and 12 is a beam ammeter.
【0014】図はイオン注入装置のエンドステーション
部を示す。ウエハ1はディスク2表面の円周上に10枚
程度保持され, ディスク2を回転してウエハに順次イ
オンを注入している。The figure shows the end station portion of the ion implanter. Approximately ten wafers 1 are held on the circumference of the surface of a disk 2, and ions are sequentially implanted into the wafers by rotating the disk 2.
【0015】通常のイオン注入では, 正イオンはディ
スクおよびウエハの両者に供給される。このため,電子
供給がなければディスクおよびウエハからGND へ
IdiscおよびIwafer が流れる。これに対し
, 電子供給が行われると電子がディスクおよびウエハ
に供給され, Idiscおよび Iwafer の
値は供給された電子の量だけ小さくなり,あるいは場合
によっては負の値になる。In conventional ion implantation, positive ions are supplied to both the disk and the wafer. Therefore, if there is no electron supply, the disk and wafer will go to GND.
Idisc and Iwafer flow. On the other hand, when electrons are supplied, electrons are supplied to the disk and wafer, and the values of Idisc and Iwafer become smaller by the amount of supplied electrons, or in some cases become negative values.
【0016】実施例では, 予め設定した Iwafe
r の値(一般には0)に保持できるようにフィラメン
ト4の電源8に帰還をかけて電子の供給を制御すること
でウエハ上の電荷を完全に中和している。[0016] In the embodiment, the preset Iwafe
The electric charge on the wafer is completely neutralized by applying feedback to the power supply 8 of the filament 4 and controlling the supply of electrons so that the value of r (generally 0) can be maintained.
【0017】[0017]
【発明の効果】イオン注入中にウエハ表面に帯電した電
荷を完全に中和することができるようになった。[Effects of the Invention] It has become possible to completely neutralize the electric charge that is accumulated on the wafer surface during ion implantation.
【0018】この結果,帯電によるデバイスの劣化を抑
制でき,信頼性の向上に寄与することができた。As a result, deterioration of the device due to charging could be suppressed, contributing to improved reliability.
【図1】 本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention
【図2】 本発明の一実施例を説明する構成図[Figure 2] Block diagram illustrating one embodiment of the present invention
【図3
】 従来例を説明する構成図[Figure 3
] Configuration diagram explaining a conventional example
1 ウエハ 2 ディスク 3 イオンビーム 4 フィラメント 5 ディスク電流計 6 ウエハ電流計 7 ウエハクランプ 8 フィラメントの可変電源 9 電子の加速電源 10 ファラデーカップ 11 バイアスリング 12 ビーム電流計 1 Wafer 2 Disc 3 Ion beam 4 Filament 5 Disc ammeter 6 Wafer ammeter 7 Wafer clamp 8. Variable power supply for filament 9 Electron acceleration power source 10 Faraday Cup 11 Bias ring 12 Beam current meter
Claims (1)
を供給しながら該ウエハにイオン注入を行う際に,該ウ
エハを該ディスクと電気的に絶縁し,該ウエハと接地電
位間の電流を測定し,該電流値を電子供給手段に帰還し
て電子供給量を制御し,該ウエハの帯電を防止すること
を特徴とする半導体装置の製造方法。Claim 1: When ion implantation is performed on a wafer held by a disk while supplying electrons to the wafer, the wafer is electrically insulated from the disk and the current between the wafer and the ground potential is measured. A method for manufacturing a semiconductor device, characterized in that the current value is fed back to the electron supply means to control the amount of electron supply to prevent the wafer from being charged.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2407653A JPH04225222A (en) | 1990-12-27 | 1990-12-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2407653A JPH04225222A (en) | 1990-12-27 | 1990-12-27 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04225222A true JPH04225222A (en) | 1992-08-14 |
Family
ID=18517213
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2407653A Withdrawn JPH04225222A (en) | 1990-12-27 | 1990-12-27 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04225222A (en) |
-
1990
- 1990-12-27 JP JP2407653A patent/JPH04225222A/en not_active Withdrawn
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980312 |