JPH04221834A - Double hetero bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain high speed and a high current gain by a simple structure and contrive to achieve simultaneously a high yield and a high breakdown strength. CONSTITUTION:An undoped InGaAs layer 5 and an n<+> InGaAs layer 6 or a layer 6 doped into an n-type, which have a band gap identical with that of a P<+> InGaAs base layer 4, larger than that of the base layer 4 or smaller than that of an undoped InP collector layer 7 and have an i/n doping profile, are inserted in the interface between the layers 4 and 7 as second collector layers. Thereby, a quantum level which is generated by the discontinuity of the conduction band of the interface between the layers 4 and 7 is made to rise and the adverse effect of a triangular barrier can be effectively inhibited.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to an II system suitable for high-speed operation.
This invention relates to the structure of a double hetero bipolar transistor (hereinafter referred to as DHBT) using a group IV compound semiconductor.

0002

2. Description of the Related Art In an N-p-N type DHBT, there is a triangular barrier caused by conduction band discontinuity at the base/collector heterojunction. This triangular barrier prevents electrons from traveling from the base to the collector, reducing the current gain. Therefore, in order to produce a DHBT with good characteristics,
It is necessary to eliminate this triangular barrier or to reduce its influence.

[0003] In order to reduce the influence of the triangular barrier, the following methods have conventionally been used. One of them is, as shown in FIG.
-n-InxGa1-xA between the InP collector layers 7
There is a DHBT structure in which a grading layer (layer whose composition is gradually changed) 10 of syP1-y is inserted. The band diaphragm in this case is shown in FIG. 6, in which arrow 20 indicates the traveling direction of electrons (e). The dotted line in FIG. 6 shows the case without the grading layer 10, and a triangular barrier 21 is formed. On the other hand, as shown by the solid line in FIG. 6, the triangular barrier 21 can be eliminated by inserting the grading layer 10 and gradually changing the band gap. Regarding this, for example, see Document 1 (RN. Nottenburg, J.C.Bi
Schoff, M. B. Punish and H.
Tempkin: IEEE Electron D
evice Lett. EDL-8 282 (19
87)).

[0004] The other is as shown in FIG.
There is a method of forming a thin N-InP doping layer 11 with a thickness of about 300 nm at a concentration of about 1 x 1017 cm-3 on the triangular barrier 21 on the collector side at the interface between the InGaAs base layer 4 and the undoped InP collector layer 7. , this is described, for example, in document 2 (O. Sugiura, A.
．． G. Dentai, C. H. Joyner, S.
Chandrasekhar and J. C. Cam
pbell: IEEE Electron Dev
ice let. EDL-9 253 (1988
)) or Reference 3 (P. Speier, U. Ko
Erner, A. Nowitzki, F. Grot
Jahn, F. J. Tegude and K. Wu
nstel: J. Cryst. Growth 9
3 (1988) 885). FIG. 8 shows a band diagram in this case. Figure 8 shows n-In
This is a comparison between the case where the P doping layer 11 is inserted and the case where the P doping layer 11 is not inserted.As shown in FIG.
The triangular barrier 21 formed between the base layer 4 and the collector layer 7 is thinner than that in the case where the barrier layer 21 is not formed (see FIG. 4A). Therefore, the tunneling probability of electrons increases, so that electrons (e in the figure) can more easily travel from the base layer 4 to the collector layer 7.

However, this method does not completely eliminate the triangular barrier 21. As shown in Figure 9,
There is a quantum level 22 that occurs between the base layer 4 and the collector layer 7. Therefore, electrons accumulate in this quantum level, and due to the space charge effect of the electrons, the triangular barrier 21 becomes higher as the current increases. Regarding this, see, for example, document 4.
(H. Nakajima, T. Ishibashi
and M. Tomizawa: Extended
Abstracts of the 22nd Co.
nference on Solid State D
evices and Materials p. 63
(1990)). Therefore, in this structure,
It is not possible to flow a large amount of current, making it impossible to operate at high speed.

[0006]

As described above, in the conventional DHBT structure shown in FIG. 5, the composition is precisely changed in an extremely thin region in the grading layer 10, which requires advanced crystal growth technology. There is a drawback. Furthermore, when manufacturing a DHBT, selective etching is used in which a certain type of liquid or gas is used and the etching rate varies depending on the material. At this time, since the base layer 4 and the collector layer 7 are made of different semiconductor materials, selective etching can be used when the grading layer 10 is not present. However, when the grading layer 10 is present, the etching rate of the grading layer 10 takes a value between the etching rates of the material of the base layer 4 and the material of the collector layer 7, so that selectivity is lost. Therefore, there are disadvantages in that selective etching cannot be used, the DHBT manufacturing process becomes complicated, and the yield of DHBT decreases.

Furthermore, in the conventional structure shown in FIG. 7, since there is a quantum level generated between the base layer 4 and the collector layer 7, electrons accumulate in this quantum level and the space charge effect of the electrons is generated. The triangular barrier becomes higher with increasing current. Therefore, there is a drawback that a large amount of current cannot flow and high-speed operation cannot be performed. The present invention has been made in view of the above points, and its purpose is to provide a DHBT structure that achieves high speed, high current gain, high yield, and high breakdown voltage at the same time with a simple structure. It is.

[0008]

[Means for Solving the Problems] In order to achieve this object, the present invention provides a DHBT having an i/n doping profile with a bandgap that is the same as the p-type base layer or larger than the base layer and smaller than the collector layer. By inserting a layer or an n-doped layer as a second collector at the interface between the base layer and the collector layer,
The most important feature is to reduce the influence of the triangular barrier that occurs at the base/collector interface of the DHBT.

[0009]

[Operation] According to the DHBT of the present invention, by performing the necessary n-type doping to a part or all of the region of the second collector layer inserted between the base layer and the collector layer, the base and collector interface It is possible to increase the quantum level caused by the conduction band discontinuity in the structure and effectively suppress the negative effects of the triangular barrier.

0010

[Example] Hereinafter, as an example of the present invention, N-InP (emitter)/p-InGaAs (base)/undoped I
The nP (collector) DHBT will be explained. FIG. 1 shows an example of the structure of the present invention. In the same figure, 1 is n+-I
It is an nGaAs layer and serves as a cap layer for forming the emitter electrode 12. 2 is an N-InP emitter layer, 3 is an undoped InGaAs spacer layer that prevents the influence of impurity diffusion, 4 is a p+-InGaAs base layer with a thickness of 680 mm, and 5 and 6 are second collector layers, each made of undoped InGaAs. layer, n+-InGaAs layer. 7 is an undoped InP collector layer with a thickness of 4000 mm, and 8 is an n+-InGaA layer for forming the collector electrode 14.
The s-layer 9 is an InP substrate doped with Fe and having a (001) plane. Here, p+-InGaAs base layer 4 and I
The undoped InGaAs layer 5 and the n+-InGa which are the second collector layer inserted into the interface of the nP collector layer 7
The thickness of the As layer 6 is 50 and 20, respectively, and the doping concentration of the n+-InGaAs layer 6 is, for example, 2×10 19 cm −3 . Also, p+-InGa
The doping concentration of the As base layer 4 is 1×1019 cm−
It is 3. In the figure, 13 is a base electrode.

As shown in FIG. 2, n+-InGaAs
If the layer 6 is not formed or doped but at a low concentration, a triangular barrier 21 generated between the base layer 4 and the collector layer 7 forms a quantum level 22 at the interface. The energy E0 of this quantum level 22 depends on the internal electric field F of the undoped InGaAs region 5. To simplify the calculation, considering an infinite heterobarrier model, the relationship between E0 and F is as shown in the following equation.

0012

[Math 1]

##EQU1## where h is Planck's constant, m is the mass of the electron, and q is the elementary charge. In addition, undoped InGaAs
The electric field F applied to layer 5 is approximated by the following equation.

[0014]

[Math 2]

where N is the doping concentration of the n+-InGaAs layer 6, d is the thickness of the n+-InGaAs layer 6, and ε is the dielectric constant of InGaAs. From the above relationship, the relationship between E0 and F is calculated as shown in FIG. N・d≧2.
At 5×1012 cm-2, E0≧250 meV. The band discontinuity of InP and InGaAs is 250 me
Since it is about V, N・d≧2.5×1012cm−2
Under the condition, the quantum level 22 becomes sufficiently shallow. Therefore, in this case, as shown in FIG. 4, the potential for electrons becomes as shown by a solid line, and the band discontinuity between the base layer 4 and collector layer 7 no longer acts as a triangular barrier 21 for electrons. In FIG. 4, 23 indicates the potential for electrons, and 24 indicates the band diagram at the lower end of the conduction band.

The above calculations were performed assuming an infinite potential. In reality, the height of the potential is finite, so the N·d product that changes E0 must be slightly larger than the above value. This effect is about 50% at most, and N・d≧4×1012cm−2
If so, there is no problem. In the case of Figure 1, N・d≧4×101
It can be seen that the condition of 2 cm −2 is satisfied, and the quantum level 22 becomes sufficiently shallow. In this structure, the current gain does not decrease even if the current density is 4 × 104 A/cm2,
It is now possible to pass high currents. The value of this current density is the same as in the case of the DHBT in which the grading layer 10 as shown in FIG. 5 is formed. Furthermore, the current density is four times or more that of the structure shown in FIG. For this reason, the present invention enables high-speed operation with a simple DHBT structure.

[0017] In order to achieve high voltage resistance, p + -InGaAs
An undoped InGaAs second collector layer inserted at the interface between the base layer 4 and the undoped InP collector layer 7
The thickness of layer 5 and p+-InGaAs layer 6 is set to p+-I
The nGaAs layer 6 must be made thin enough to be completely depleted. When the doping concentration and thickness of the p+-InGaAs layer 6 are specified, undoped InGaAs
The potential change of the layer 5 is the undoped InGaAs layer 5.
If the thickness of
The bandgap of the As layer) is required. That is, regarding D

[0018]

[Math 3]

The following conditions are necessary. Here, D<12
5, and it can be seen that the structure of FIG. 1 satisfies this condition. In this case, the breakdown voltage is 5V or more,
There are no practical problems.

In the above, in order to simplify the calculation, the undoped InGaAs layer 5 and the p + -InGaAs layer, which is the second collector layer, are placed at the interface between the base layer 4 and the collector layer 7.
The case where layer 6 is inserted has been described. However, in order to make the quantum level 22 formed by the triangular barrier 21 formed between the base layer 4 and the collector layer 7 sufficiently shallow, it is essential to narrow the width of the quantum well. There's no particular need. In addition, here, a DHBT consisting of an N-InP emitter layer 2/p+-InGaAs base layer 4/undoped InP collector layer 7 is used.
However, it is clear that the present invention can be applied to DHBTs having other material configurations in which the triangular barrier 21 is formed at the interface between the base layer 4 and the collector layer 7 due to conduction band discontinuity.

[0021]

[Effects of the Invention] As explained above, the present invention provides DHBT
In this method, a double layer of an i-doped layer and an n-doped layer made of the same material as the p-type base layer, or a double layer made of the same material as the p-type base layer and doped n-type, is placed at the interface between the base layer and the collector layer. By inserting it, a DHBT with high breakdown voltage, high current gain, and high speed can be manufactured with a simple structure.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a DHBT structure according to an embodiment of the invention.

FIG. 2 is an energy band diagram between base and collector in the embodiment of FIG. 1;

FIG. 3 is a diagram showing calculation results of the relationship between quantum level energy E0 and internal electric field F according to the present example.

FIG. 4: n+ which is the second collector layer in this example.
- It is a band diagram when an InGaAs layer is heavily doped.

FIG. 5 is a partial cross-sectional view of a DHBT structure showing an example of the prior art.

FIG. 6 is an energy band diagram corresponding to the structure of FIG. 5;

FIG. 7 is a partial cross-sectional view of a DHBT structure showing another example of the prior art.

8 is a band diagram showing how the triangular barrier is thinned by N-type doping only in the thin region on the collector side at the interface between the base layer and the collector layer in the structure of FIG. 7;
FIG. 3 is a diagram comparing and showing cases in which an nP layer is inserted and cases in which an nP layer is not inserted.

9 is a diagram showing that quantum levels are formed at the base/collector interface in the conventional structure of FIG. 7. FIG.

[Explanation of symbols]

1 n+-InGaAs cap layer 2 InP emitter layer 3 InGaAs spacer layer 4 p+-InGaAs base layer 5 Undoped InGaAs that is the second collector layer
Layer 6 n+-InGaAs layer 7 which is the second collector layer InP collector layer 8 n+-InGaAs layer 9 for forming an electrode I
nP substrate

Claims (1)

[Claims] 1. A first collector layer of a first conductivity type on a semiconductor substrate, a base layer of a second conductivity type having a smaller band gap than the first collector layer, and an emitter having a larger band gap than the base layer. In a double hetero bipolar transistor configured of layers in this order, or in the order of the emitter layer, the base layer, and the collector layer, a second collector layer having a smaller band gap than the first collector layer is the base layer. provided between the first collector layer, a part or all of the second collector layer is doped with impurities of the first conductivity type at a predetermined concentration, and A double hetero bipolar transistor characterized by changing the quantum level of a potential well formed at the interface of a collector layer.