JPH04221452A - Pattern generator for servo control device use and servo control device of vtr - Google Patents

Abstract

PURPOSE:To offer a pattern generator, for servo control device use, which can easily generate a pattern whose jitter component is extremely small. CONSTITUTION:The following are provided: a RAM 40 which stores, in the same address, the time constant of a pattern to be generated and the data value of the pattern and a counter 45 which counts the period corresponding to the time constant of an address designated by the RAM 40. During the counting period of the counter 45, an output data at the address designated by the RAM 40 is output, and the address of the RAM 40 is changed whenever the counter 45 finishes a counting operation.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator used in a servo control device and a servo control device for a VTR (video tape recorder) using this pattern generator.

0002

[Prior Art] Servo motors for VTRs, namely DC (direct current) servo motors for driving rotating head drums, DC servo motors for driving capstans, and tape reel drives. As a device for controlling a DC servo motor for
624) exists.

[0003] In this servo control IC device, the VT
Various signals necessary for servo control of R are controlled and formed by microcomputer software. That is, by controlling the activation of the built-in pattern generator by software, various signals such as the head switching pulse HSW of the rotary head drum and the pseudo vertical synchronization signal FV are generated.

0004

[Problems to be Solved by the Invention] According to the conventional servo control device as described above, it is necessary to manage the mutual time relationships of the various signals to be formed by software, and it is necessary to manage the mutual time relationships of the various signals to be formed. In order to output the - signal, it is necessary to calculate the activation timing of each signal, etc.
Control becomes very complicated.

Moreover, if the activation of the pattern generator is controlled by software in this manner, there is a risk that a time delay may occur in the generated signal. That is, according to software control, (a) if a high-priority interrupt process occurs, the CPU (central processing unit) executes it first, and (b) during the instruction execution cycle, that instruction is Because it is not possible to move on to the next event until the processing of the event is completed, the generated signal contains a large jitter component.

Accordingly, the present invention provides a pattern generator for a servo control device that can easily generate patterns with extremely low jitter components.

A further object of the present invention is to provide a servo control device that can perform servo control of a VTR with high precision and extremely easily.

[0008]

[Means for Solving the Problems] According to the first invention of the present application, there is provided a memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address; a counting means for counting a period corresponding to a time constant of a designated address of the means; and means for outputting a data value at the designated address of the memory means as described above during the counting period of the counting means;
A pattern generator for a servo control device is provided, comprising means for changing the above-mentioned address each time the counting means completes counting.

According to the second invention of the present application, there is provided a memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address, and a designated address of the memory means. a counting means for counting a period corresponding to a time constant of , a means for outputting a data value at an address specified by the memory means as described above during the counting period of the counting means, and a means for outputting a data value at an address designated as described above in the memory means, each time the counting means finishes counting. A pattern generator for a servo control device is provided, comprising means for changing the above-mentioned address, and which uses at least one bit of the output data value as a head switching pulse for a rotating head drum of a VTR. be done.

According to the third invention of the present application, there is provided a memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address, and a designated address of the memory means. a counting means for counting a period corresponding to a time constant of , a means for outputting a data value at an address specified by the memory means as described above during the counting period of the counting means, and a means for outputting a data value at an address designated as described above in the memory means, each time the counting means finishes counting. means for changing said address to V
The rotation of the rotary head drum is controlled from a pulse generating means that generates a pulse corresponding to the actual rotational position of the rotary head drum of the TR, a head switching pulse consisting of at least one bit of the output data value, and the generated pulse. service
A servo control device for a VTR is provided.

[0011]

[Operation] A dedicated counting means counts a period corresponding to a time constant stored at a designated address of the memory means. The data value at this designated address is output during the counting period of the counting means. The address is changed every time the counting means finishes counting. Therefore, a pattern having an arbitrarily settable time constant can be generated without the intervention of software.

By setting at least one bit of this output pattern as a head switching pulse of the rotary head drum of the VTR, this pattern generator
The free running period of the motor is synchronized with this head switching pulse. In other words, the pattern output from this pattern generator is synchronized with all head switching pulses, resulting in a pattern with extremely low jitter components.
can be easily generated.

[0013] In the VTR servo control device, the VT
The rotation of the rotary head drum is servo-controlled based on the pulse corresponding to the actual rotational position of the R rotary head drum and the synchronized head switching pulse as described above.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram schematically showing the configuration of a servo control device for a VTR as an embodiment of the present invention.

In the figure, numeral 10 indicates a microcomputer for servo control. This microcomputer 10 includes a CPU 11, a ROM (read only memory) 12, a RAM (random access memory) 13, and a PPG (programmable pattern generator).
14. FRC (free run counter) capture circuit 1
5. Drive pulse generation circuit 16, SIO (serial interface unit) 17 for input/output conversion of serial data, timer/counter 18, A/D converter 19, and general-purpose input/output port 20 These are connected to each other via an internal bus 21.

This microcomputer 10 has a VT
The rotary head drum 22 of R, the CTL (control) head 23, the capstan drive motor 25 via the drive circuit 24, the rotary head drum drive motor 27 via the drive circuit 26, and the capstan. Frequency generator 28
, a frequency generator 29 of the rotary head drum 22, a pulse generator 30 of the rotary head drum 22, a crystal oscillator 31, etc. are connected.

The PPG 14 receives various signal patterns, such as a head switching pulse HSW of the rotating head drum 22, a control signal HAMP of a head amplifier (not shown),
Recording control signal REC-CT of CTL head 23
It generates patterns such as L, pseudo vertical synchronizing signal FV, and audio head switching pulse A-HSW. This P
The configuration and operation of the PG 14 will be explained in detail later.

The FRC capture circuit 15 is mainly composed of a free run counter, and receives a capstan frequency pulse C-FG applied from a frequency generator 28 of the capstan, a frequency generator of the rotating head drum 22 Drum frequency pulse D-FG applied from 29
, the drum pulse D-PG applied from the pulse generator 30 of the rotating head drum 22, the playback control signal PL-CTL applied from the CTL head 23, and the edge timing of the vertical synchronization signal VSYNC are detected. The contents of the free run counter at that time are latched. Therefore, the actual rotational position of each motor is represented as the measured value of this free run counter, and the latched measured value is applied to the CPU 11. The pulse generator 30 described above corresponds to the pulse generating means of the present invention.

[0020] The CPU 11 includes an FRC capture circuit 15
PPG14 using the measured value of the pulse edge given by
The control amount of the motor is calculated based on the difference between the edge of the pattern signal generated from the drive pulse generation circuit 16
Output to. For example, for driving a rotating head drum in which the difference between the measured value of the edge of the drum pulse D-PG from the FRC capture circuit 15 and the measured value of the edge of the head switching pulse HSW generated from the PPG 14 is a constant value or zero. The control amount of the motor 27 is output to the drive pulse generation circuit 16. The CPU 11 corresponds to the servo control means of the present invention.

The drive pulse generation circuit 16 is a duty control circuit, and controls the rotational speed and speed of the capstan drive motor 25 and the rotary head drum drive motor 27 according to the control amount given from the CPU 11. PWM to control the phase
A (pulse width modulation) signal is created and output to the drive circuit 24 and the drive circuit 26, respectively. As a result, the capstan drive motor 25 and the rotary head drum drive motor 27 are servo-controlled.

The A/D converter 19 receives adjustment data,
It is provided for inputting signals from the capstan sensor, signals from the mechanism sensor, etc.

The general-purpose input/output port 20 inputs signals from the reel sensor and outputs capstan control signals, mechanism control signals, and the like.

FIG. 1 is a block diagram showing the configuration of the PPG 14 in more detail.

In the figure, 40 is a 32-bit RAM.
It shows. This RAM 40 is
A part of the RAM 13 (see FIG. 2) built in the computer may be used, or a dedicated RAM 13 may be provided. RAM
40 has three regions 40a, 40b, and 40c
Each area is divided into 40a, 40b, and 4
0c is configured so that 16-bit time constant data, 8-bit output data, and 8-bit output port control data can be stored at the same address. These data may be written in the RAM 40 in advance, or may be written in accordance with an instruction from the CPU 11 each time the mode is initialized. RAM 40 corresponds to memory means of the present invention.

A register (DMPTR) 41 having an increment function is connected to the RAM 40, and the DMPTR 41 is configured to give an address of the RAM 40. This DMPTR41 has RAM40
A register (IDMPTR) 42 that gives the start address of
is connected. The IDMPTR 42 is connected to the CPU 11 (see FIG. 2) via an internal bus 43, and
RA from CPU 11 when initializing mode switching, etc.
The starting address of M40 is loaded. This DMPTR
41 corresponds to means for changing the address of the present invention.

A 16-bit register (PGTCMP) 44 having a match detection function is connected to the DMPTR 41, and the DMPTR 41 is incremented by a match signal given from the PGTCMP 44. P.G.
The TCMP 44 is connected to an area 40a of the RAM 40 and a time base counter (PGTM) 45, and compares the contents of the PGTM 45 with the time constant data addressed in the area 40a of the RAM 40, so that both Outputs a match signal when a match occurs.

The PGTM 45 is cleared by a signal applied via the selector 46, and the clock (CLOC)
K). This PGTM 45 corresponds to the counting means of the present invention.

Counter (DMCT) 47 is PGTCMP
PGTCMP44, and is incremented by a match signal given from this PGTCMP44. This D
MCT47 is a register (IDMC) with a match detection function.
NT) 48 is connected. IDMCNT48 is CP
It is connected to U11 (see Figure 2) via an internal bus 49, and when initializing the mode change, etc.
The set number of address changes in the RAM 40 is loaded from 1 to 1. IDMCNT48 is the content of DMCT47 and CP
It compares the set number of address changes in the RAM 40 loaded from U11, and outputs a match signal when the two match. This match signal is applied to DMCT 47 to clear this counter and is applied to DMPTR 41 to load this register with the starting address from IDMPTR 42. Furthermore, this match signal is applied to selector 46.

The selector 46 selects the above-mentioned coincidence signal from the IDMCNT 48, the coincidence signal from the PGTCMP 44, or an external trigger according to an instruction from the CPU 11. The external trigger is selected when it is desired to obtain a one-shot function, when there is a disturbance, and when it is particularly desired to control with an external trigger.

[0031] The register (PGOUT) 50 is
0 and an output port (PORT) 51 which is a general-purpose port register of the microcomputer. The PGOUT 50 receives 8-bit output data and 8-bit output port control data stored in the addressed areas 40b and 40c of the RAM 40, and outputs them to the PORT51. the result,
The bit of PORT51 specified as “1” by the output port control data becomes active and becomes “0”.
The bit designated as 2 becomes high impedance. The activated bit of the PORT 51, that is, the activated bit of the output terminal of the pattern generator, is controlled to be high (H) or low (L) depending on the output data. A head switching pulse HSW is outputted to one bit of this output terminal as shown in FIG. Other bits of the output terminal contain other patterns, such as the head amplifier control signal HAMP, the CTL head recording control signal REC-CTL, and the pseudo vertical synchronization signal FV.
, audio head switching pulse A-HSW, and other patterns are output. The above-mentioned PGOUT50 and PORT51 are the data of the present invention.
This corresponds to a means for outputting data values.

Next, the operation of this PPG 14 will be explained.

First, the time constant data stored in the RAM 40 at the address set by the DMPTR 41 is sent to the PGTCMP 44, and the output data and output port control data at the same address are sent to the PGOUT 50. As mentioned above, the time constant data is sent to PGTCMP44.
The contents of TM45 are applied. This PGTM45 is counted up by a clock. PGTM45
The pattern set by PGOUT50, that is, the pattern based on the output data of the same address and the output port control data, is output until the content of the data becomes equal to the time constant data. .

When the contents of PGTM 45 match the time constant data, DMPTR 41 is incremented, and the next address in RAM 40 is accessed to store the time constant data, output data, and output port control data. PGTCMP44 and PGOUT
50 respectively. At the same time, DMCT47 is incremented.

The above processing is repeated, and DMCT4
The contents of 7 are the contents set in IDMCNT48,
In other words, if the number of address changes in RAM 40 matches the set number, the contents of IDMPTR 42 are loaded to DMPTR 41.
The address of the RAM 40 returns to the starting address. This results in one cycle of a series of patterns being generated.

[0036] By operating the selector 46, select PGTCMP4.
If the PGTM45 is set to be reset by the match signal of 4 or the match signal of IDMCNT48, this P
PG14 will be self-propelled. If the PGTM 45 is set to be reset by the match signal of the PGTCMP 44, the time constant data counting start point will appear every time the address is changed. Also, IDMCN
If the PGTM 45 is set to be reset by the match signal of T48, the time constant data counting start point will appear every time the address change reaches the set number of times. Which coincidence signal to select depends on how to set the time constant of the pattern to be generated: whether to start counting from the start point of each cycle or from the end of the previous pattern. etc., as desired.

As described above, during the period corresponding to the time constant data stored in the RAM 40, the data value at the same address as the time constant data is output. That is, as shown in Figure 1, 16-bit time constant data is "00000000".
00000101”, PGTM45 is “
During the period of counting ``101'', the 8-bit output data ``0'' is counted.
0000001” and 8-bit output port control
The file data "11111111" is sent to PGOUT50. Since each bit of the output port control data is all "1", all bits of PORT51 become active, and the output data "00000001" is directly output from the output terminal to form a pattern. Ru. When the period corresponding to the time constant data ends, the address is incremented, and the next time constant data becomes "0000000000000011". All bits of output port control data are “1”
Therefore, the output data "10000001" is output during the period corresponding to the time constant data "11".

In this manner, since the pattern is output without the intervention of software, a pattern with extremely low jitter components can be easily generated. Moreover, if one bit of the pattern output in this way is the head switching pulse HSW of the VTR, all the patterns output from the other bits, such as the control signal HAMP of the head amplifier and the control signal HAMP of the CTL head, Patterns such as the recording control signal REC-CTL, pseudo vertical synchronization signal FV, audio head switching pulse A-HSW, etc. are generated reliably in synchronization with this head switching pulse HSW without any timing delay. . Therefore, VT
Servo control of R can be performed accurately and extremely easily.

Although one head switching pulse HSW is used in the above embodiment, a plurality of head switching pulses may be generated.

Furthermore, in the embodiment described above, the RAM 40 has three
Although it is a 2-bit RAM, a 16-bit or 8-bit RAM may be used, or a plurality of RAMs may be connected.

Furthermore, the memory means of the present invention may use ROM, registers, or other storage devices in addition to RAM.

[0042]

As described in detail above, according to the present invention, there is provided a memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address; a counting means for counting a period corresponding to a time constant of a designated address of the memory means, and means for outputting a data value at the designated address as described above in the memory means during the counting period of the counting means;
Since the counting means includes means for changing the above-mentioned address each time the counting is completed, a pattern having an arbitrarily settable time constant can be generated without the intervention of software.

By setting at least one bit of this output pattern to the head switching pulse of the rotary head drum of the VTR, this pattern generator
The free running period of the motor is synchronized with this head switching pulse. In other words, the pattern output from this pattern generator is synchronized with all head switching pulses, resulting in a pattern with extremely low jitter components.
can be easily generated.

In the VTR servo control device, the VT
Since the rotation of the rotary head drum is servo-controlled from the pulse corresponding to the actual rotational position of the R rotary head drum and the synchronized head switching pulse as described above,
Servo control of a VTR can be performed accurately and extremely easily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing in detail the configuration of a PPG in an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing the configuration of a servo control device for a VTR in the embodiment of FIG. 1;

[Explanation of symbols]

10 Microcomputer 11 CPU 12 ROM 13, 40 RAM 14 PPG 15 FRC capture circuit 16 Drive pulse generation circuit 17 SIO 18 Timer/counter 19 A/D converter 20 General-purpose input/output ports 21, 43, 49 Internal Bus 22 Rotating head drum 23 CTL head 23 24, 26 Drive circuit 25 Capstan driving motor 27 Rotating head drum driving motor 28, 29
Frequency generator 30 Pulse generators 40a, 40b, 40c Region 41 DMP
TR 42 IDMPTR 44 PGTCMP 45 PGTM 46 Selector 47 DMCT 48 IDMCNT 50 PGOUT 51 PORT

Claims (3)

[Claims] Claim 1: Memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address, and a period corresponding to the time constant of a specified address of the memory means. counting means for counting, means for outputting a data value at the designated address of the memory means during a counting period of the counting means, and changing the address each time the counting means finishes counting. 1. A pattern generator for a servo control device, comprising: means. 2. Memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address, and a period corresponding to the time constant of the designated address of the memory means. counting means for counting, means for outputting a data value at the designated address of the memory means during a counting period of the counting means, and changing the address each time the counting means finishes counting. 1. A pattern generator for a servo control device, characterized in that at least one bit of the output data value is used as a head switching pulse of a rotary head drum of a VTR. 3. Memory means for storing a time constant of a pattern to be generated and a data value of the pattern at the same address, and a period corresponding to the time constant of the specified address of the memory means. counting means for counting, means for outputting a data value at the designated address of the memory means during a counting period of the counting means, and changing the address each time the counting means finishes counting. pulse generating means for generating a pulse corresponding to the actual rotational position of a rotary head drum of the VTR; a head switching pulse comprising at least one bit of the output data value; 1. A servo control device for a VTR, comprising means for servo controlling the rotation of a rotary head drum.