JPH0421995A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To accelerate time for inverting a cell and for writing by setting a potential VB of a bit line to impressing voltages VC and VE of the memory cell to be VB<VE when writing a data to the memory cell, and reducing the differential voltage of VC-VE. CONSTITUTION:In order to accelerate access time when reading out information while switching a select word line, the amplitude of the voltage signal of the word line is lowered from 2.4V to 1.6V. Namely, a non-select level VWL of the word line is increased from -3.2V to -2.4V. Therefore, in the case of the VWL (-2.4V), it is necessary to increase the potential VE as well to the VWL (-2.4V) so that transistors MTL and MTR can not be turned on. Since a normal memory sets the potential VE and a potential VBL of the bit line in the case of writing to be VR<=VBL, the write time is delayed when increasing the VBL only for the increased component of the VE. In this case, the VBL is set to -3.0V and made lower than the VE (=2.4V) and the On resistance of the MPL or MPR in the case of writing is reduced. Then, the time is accelerated for inverting the memory cell and writing the data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and particularly to a semiconductor memory suitable for speeding up the write time of a memory whose memory cells are constructed of flip-flops including field effect transistors. Regarding circuit technology.

[Prior Art] Recently, in order to achieve both high integration and high speed of memory, many circuits using both field effect transistors and bipolar transistors have been proposed1. rccl+
"An" of oical Papers pp, 36-37
8ns BiCMO3IMb ECL SRAM
With a Configurable Memory
In a circuit like the one described in the paper entitled "YArray 5ize", the memory cells are constructed with insulated gate field effect transistors suitable for high integration, and the base is connected to the bit line with a differential amplifier that detects the potential of the bit line. In addition, the circuit that supplies charging current to the bit line is composed of a bipolar transistor whose emitter is connected to the bit line via a resistor.In other words, it is an insulated gate transistor suitable for high integration. A field effect transistor is used to reduce the memory cell area, and a bipolar transistor suitable for high speeds is used to shorten the bit line potential detection time and bit line charging time.However, the difference in detecting the bit line potential is Since the circuit that drives the differential amplifier to the active state and the circuit that supplies discharge current to the bit line are composed of insulated gate field effect transistors, the time it takes for the differential amplifier to switch to the active state and the discharge time of the bit line are shortened. There were limits to shortening.

[Problems to be Solved by the Invention] The above conventional example is shown in FIG. 2(a). FIG. 2(a) is a circuit diagram of a memory cell of a semiconductor memory and its peripheral circuit. In this figure, MCll-MC22 is a memory cell, Wl
, W2 is the word line, BLI.

+3RI, BL2. BR2 is the bit line, VYINI.

VYIN2 is a bit line selection signal, D, D', DI.

DI' is a read/write control signal. Memory cell MCI
When selecting I and reading information, transistor M'
Word line W1 is driven to a high potential to turn on L and MTR, and transistor URL.

Bit line selection signal VY to turn on MRR and MR.
Drive TNI to high potential, read/write control signal, D'
is driven to a low potential to turn off transistors MDL and MDR, and DI and DI' are driven to a high potential. Now cell M
When transistor MNL in CII is on, one cell current flows from transistor QYL to REL, M
Flows to VEE via TL and MNL. Therefore, QYL
The current flowing through Icell and MRL is the current I(
MRL), that is, Icell+1(MRL). (However, the base current of QRL is extremely small, so we ignored it here.) Therefore, the base current of QYL
The emitter voltage VBE (QYL) is as follows: VBE (QYL) = (nkT/q)・In[(1cell
l+[(MRL))/Io] where, k: Boltzmann constant = 1.38XIO=”J/Kq
:Electronic charge = 1.602XIO-'”Cn: Slope coefficient of junction voltage/current characteristics (e.g., n=1.05) T: Standard operating temperature (e.g., T=323.15K) IO
=Reverse saturation current of junction Also, resistance REL (7) voltage V(REL) is V(RE
L)=REL・(Icell+I(MRL)).

On the other hand, the current flowing through QYR is the current I flowing through MRR.
(MRR) (=I (MRL)) only. (However, the base current of QRR is extremely small, so it is ignored here.) Therefore, the base-emitter voltage VBE (QYR) of QYR is: VBIIQYR) = (nkT/q) HIn [1(
MRL) / Io] Also, the resistance RER(=REL)(
7) The voltage V (RER) is as follows: V (REI+) = REI, · I (MRL). Therefore, the potential difference ΔVB between the bit lines BLI and BRI is AVB=VBE(QYI,)+V(REL)−VBE(
QYR)-V(RER)=(nkT/q)・In((l
cell+I(MRL))/I(MRL)]+REL・
It becomes Icel I. Now, since VYINI is at a high potential and MR is on, the differential amplifier composed of QRL and QRR is in the active state, so this differential amplifier detects the potential difference ΔVB and connects the common data line. Output data to CDL and CDR.

On the other hand, unselected bit lines receive bit line selection signal VYIN2.
is at a low potential and MR in S2 is off, so the differential amplifier in S2 is not in an active state, and this differential amplifier does not output data to the common data lines CDL and CDR. . Therefore, the common data lines CDI, ,CD
Since only the data of cell MCII is output to R,
By detecting this data, the information of cell MC1,1 is
Can be read.

Next, when selecting the memory cell MC11 and loading information into it, the word line W1 is first driven to a high potential and the bit line selection signal VYINI is driven to a high potential, as in the case of reading. Next, depending on the write information, either one of the read/write control signals 1) and D' is set to a high potential, DI, DI'
Drive either one of them to the low 1 position. Now, when transistor MNL in cell MCII is on, if D' is driven to high potential and DI' is driven to low potential, bit line B
Since RI changes to a low potential and the gate voltage of MNL becomes low potential, MNL is switched from on to off, and the information in the cell is inverted.

However, this conventional example has two problems as described below.

First, let us discuss the first problem. This problem occurs when reading information by switching the selected bit line. That is, first, the information of the cell Mcz is read out, and then, in order to switch the selection pin 1 to line and read the information of the cell MC12, VYINI is driven to a low potential and VYIN2 is driven to a high potential. , at this time, the MR in Sl is switched from on to off, and the MR in S2 is switched from off to on.

Therefore, the differential amplifier in Sl becomes inactive, and S
The differential amplifier in cell MC12 becomes active, and the data of cell MC12 is output to common data lines CDL and CDR. However, since the switching time of an insulated gate field effect transistor is generally as slow as lns, it takes an extremely long time for the MR to switch from off to on and for the differential amplifier to switch to the active state.

Therefore, there is a problem in that the access time when reading information by switching the selected bit line becomes extremely slow.

Next, the second problem will be described. This problem occurs when writing information. That is, when selecting the memory cell MC11 and writing information, as described above, depending on the write information, either the bit line BL1 or the BRI is discharged to lower the potential of the pin I line. It is necessary to drive it to a potential. Therefore, when writing, the read/write control signal or I)' is set to a high potential and MDL or M I)' is switched from off to on, but the switching time of the insulated gate field effect transistor is
Since it is slow, on the order of nanoseconds, it takes an extremely long time to discharge the bit line and drive the potential of the bit line to a low potential.

Therefore, there is a problem that the writing time becomes extremely slow.

Therefore, the inventors proposed a method for speeding up the access time when reading information by switching the selected bit line and shortening the charging/discharging time of the bit line when writing information in Japanese Patent Application No. 1-210083-3. , proposed a method to speed up writing time.

FIG. 2(b) shows one of the semiconductor memories adopting the above proposal.
It is a figure which shows an example. FIG. 2(b) is a circuit diagram of a memory cell of a semiconductor memory and its peripheral circuit. In this diagram,
MCII to MG22 are memory cells, Wl, W2i;t,
'7-D line, BLI, BRI.

13+, 2. BR2 is the bit line, VYINI.

VYINI', VYIN2. VYIN2' is a bit line selection signal, and WE, DI, and DI' are read/write control signals. In addition, the numbers in the diagram are 1.
For example, -3, 0/-3, 4 of the bit line selection signal VYINI indicates that the selection level is -3,
OV, the non-selection level is -3°4■, and the read/write control signal WEQ) -0°8/-2,2 means that the read level is -0,8V and the write level is -2,2■. It shows. In this figure, when selecting memory cell MCII and reading information, transistors M T 1 .
, and drives word line W1 to a high potential to turn on MTR, and transistors QIR, QIBL.

Bit line selection signal VYIN to turn on QTBR
I is driven to a high potential, the read/write control signal WYl' is set to high 11, DI and D1'' are set to a high potential, and V 'l' T N 1 is set so that the potential of the bit line is determined from WE.
' Drive to low potential. If the transistor MNL in the cell MCII is currently on, the cell current Icell comes from the transistor QYL.

Flows to VE via RIEL, MTL, and MNL.

Therefore, the current flowing through QYL is Tcell and 113L.
The sum is Icell+IBL. Therefore,
The base-emitter voltage VBE (QYL) of QYL is VBE (QYL) = (nkT/q)4n[(Icell
+IBL)/to] Here, k: Bol'/Ma'/Constant = 1.38x+o-"J/K
q: Electron charge = 1.602
Io: Reverse saturation current of junction Also, resistance REL (7) voltage V(REL) is V(RE
L)=REL(Icell+IBL). On the other hand, Q
The current flowing through YR is only IBR (=IBL).

Therefore, the base-emitter voltage VBE (Q
Y・R) is VBE(QYR) ±(nkT/q) ・
in[IBL/Io] Also, resistance RER (=REL)
The voltage V (RER) is as follows: V (R1 SI) = 1 EL-IB+. Therefore, the potential difference ΔVB between bit lines BLI and BRI is AVB=VBE(QYL)+V(REL)−VBE(Q
YR)-V(RER)”(nkT/q)・In[(lc
ell+IBL)/IBL]+REL・1cell・・
・・・・・・・・・・・・・・・・・・・・・・・・
...(1). Now, since VYINI is at a high potential and QIR is on, the differential amplifier composed of QRL and QRR is in the active state, so this differential amplifier detects the potential difference ΔVB and connects the common data line. Output data to CDL and CDR.

On the other hand, the unselected bit line is connected to the bit line selection signal VYIN.
2 is at a low potential and the QIR in S2 is off, so S
The differential amplifier within common data line CDl7. Do not output data to CDR. Therefore, the common data lines CDL, C
Since only the data of cell MCII is output to DR, the information of cell MCII can be read by detecting this data.

Next, when selecting the memory cell MCII and writing information, first drive the word line Wl to a high potential as in the case of reading, drive the bit line selection signal VYINI to a high potential, and set the VYINI to a high potential.
Drive NI' low. Next, depending on the write information, one of the read/write control signals DI and DI' is driven to a low potential, and WE is driven to a low potential. Now cell MCI
When transistor MNL in I is on, DI'
When QIWR is driven to a low potential, QIWR is turned on and the bit line BRI changes to a low potential. Therefore, the gate voltage of the MNL becomes a low potential, so the MNL is switched from on to off, and the information of the cell is inverted.

Here, in this embodiment, there are two points to note.

The first point to note is when switching the selected bit line and reading out information. That is, first cell MCII
Next, to switch the selected bit line and read the information of cell MC12, drive VYINI to a low potential and VYINI' to a high potential, and drive VYINI to a low potential and VYINI' to a high potential.
2 to a high potential and VYIN2' to a low potential. At this time, the QIR in Sl turns from on to off, and the QIR in S2 changes from on to off.
IR switches from off to on. Therefore, the differential amplifier in Sl becomes inactive, the differential amplifier in S2 becomes active, and the common data lines CDL and CD
The data of cell MC12 is output to R. The point to note here is that the switching time of bipolar transistors is generally fast, about 0.5 ns, so it takes only a short time for the differential amplifier to switch to the active state, so the selected bit line can be switched. This means that the access time when reading information is faster.

Next, the second point of interest is when writing information.

That is, when selecting the memory cell MCII and writing information, as described above, either the bit line B L l or B'RI is discharged depending on the write information, and
It is necessary to drive the bit line potential to a low potential. Therefore, when writing, the read control signal DI or DI' is set to a low potential, and the read control signal DI or DI' is set to a low potential.
Switch from off to on. The point to note here is that the switching time of bipolar transistors is 0.
．． Since it is as fast as about 5 ns, it takes only a short time to discharge the bit line and drive the potential of the bit line to a low potential, which means that the writing time becomes faster.

However, in this example, although the access time and write time when reading information by switching the selected bit line become faster, the access time when reading information by switching the selected word line does not become faster.

In order to speed up the access time when switching the selected word line, it is effective to reduce the amplitude of the word line voltage signal. However, if the amplitude of the voltage signal of the word line is reduced, a problem arises in that the writing time, which has been made faster, becomes slower. This will be explained below.

The time for writing information into the memory cell is the sum of the bit line discharge time and the memory cell inversion time described above. In this example, since the discharge time of the bit line is fast, the boiling time can be made faster.

However, the inversion time of the cell itself, that is, the time during which the information in the cell is inverted after the transistor MNL switches from on to off in the above explanation, is determined by the on-resistance of MPL,
It is determined from the time constant with the parasitic time of the drain of MNL. M
The on-resistance of I) I increases as the gate voltage of M I) L increases. Therefore, if the amplitude of the word line voltage signal is lowered and the voltage of VE is increased accordingly, the inversion time of the memory cell increases and the write time becomes slower.

An object of the present invention is to speed up the inversion time of the cell itself when reducing the amplitude of the voltage signal on the word line, thereby speeding up the write time.

[Means for Solving the Problem] A semiconductor memory device of the present invention for achieving the above object, 4
A semiconductor having a configuration of a flip-flop made of a field effect transistor to which VC and VE (VC>VE) are applied, and a transfer gate that transfers data between the flip-flop and the bit line. In the memory, the potential V B of the bit line when writing data to the memory cell marked "-" is set to V T3 > V
C or V B < V l-, 4.1.

Alternatively, the semiconductor memory of the present invention for achieving the -1- memory characteristic has potentials VC and VI:, (VC>VIE
) is applied, and a transfer gate that transfers data between the flip-flop and the above-mentioned bit line. Potential of the well or semiconductor substrate where transistors constituting the flip-flop are formed V T3 B
and the potential VB of the bit line when writing data to the memory cell are VBB)VB)VC or VBB(VB(VE).

[Function] First, a case where the transfer gate is an NMOS will be explained.

By increasing the potential of VE as VB<VE and decreasing the voltage difference between VCl2 and VE to reduce the amplitude of voltage borrowing on the word line, the access time when switching the selected word line and reading information will be shortened. Therefore, the speed increase becomes 1'+f.

Also, as VB<VE, the bit line potential VB at the time of writing
By making the potential VE lower than the high potential VE, it is possible to reduce the on-resistance of the transistor in the memory cell during writing.

This on-resistance is a factor that determines the time it takes for cell information to be inverted, and reducing it will speed up the writing time.

Furthermore, the potential VBB of a well or a semiconductor substrate where a transfer gate or a transistor in a memory cell is formed
By setting VBB<VB<VE instead of making it the same as VE, the p voltage between the potential of the rl-type electrode of the drain or source of the transistor in the transfer gate or memory cell and the well or semiconductor substrate 4% (p-type) is set to VBB<VB<VE. There is no possibility that a so-called latch-up will occur, where the n-junction turns on and current flows into the well or substrate. That is, as described above, by setting VBB<VB<VE, the latch-up resistance is improved while speeding up the read access time and write time.

The above is an example in which the transfer gate is NMO8O, but if it is PMO3, setting VBB>VB>VC will bring about the same effect.

Embodiment FIG. 1(a) is a diagram showing a first embodiment of the present invention. The difference between FIG. 1(a) and FIG. 2(b) is that in FIG. 1(a), in order to speed up the access time when reading information by switching the selected word line, Change the voltage signal from 2.4■ (=-0,8-(-3,2)) to 1
．． The amplitude is reduced to 6v (=-0, 8-(-2, 4)). In other words, the word line non-selection level VWL
is increased from -3.2V to -2.4V. Therefore, when the word line is at the non-selection level VWL (-2, 4V),
In order to prevent the transistors MTL and MTR from turning on, the potential VE is also set to the word line non-selection level VWL (-2
, 4V). Here, in a normal memory, the relationship between the potential VE and the bit line potential VBL during writing is VE≦VBL, so this example also follows this, and the bit line potential VBL during writing is increased by the increase in VE. If it is set higher, the M I) L when writing
Alternatively, the on-resistance of the MPR becomes thick (which increases the inversion time of the memory cell and slows down the write time. Therefore, in this embodiment, the bit line potential VB
L to -3.0V (=WE L level to QYL or Q
Voltage minus YR base-emitter voltage = -2,2
-0,8), VE (=-2,4V) is lowered, and the on-resistance of MPL or MPH during writing is reduced.Thus, the inversion time of the memory cell is reduced, and the writing time is is accelerated.

Furthermore, in this embodiment, the transistor MTL.

The potential VBB of the well or semiconductor substrate where MTR, MNL, and MNR are formed is set to VBB=VEE=-5,2.
V, and VBB (VE=-2.4V. (Here, VEE indicates the potential of one terminal of the power supply together with CC in FIG. 1(a).) Explain that latch-up resistance can be improved.In a normal memory, transistors MTL, MTR and MNL,
Potential VB of the well or semiconductor substrate where MNR is formed
B has VBB=VE. In FIG. 1(a), if VBB=VE=-2.4V, the potential of the bit line becomes -3.OV during writing, so the drain and source (n type) of MTL or MTR and the MNL
Alternatively, the voltage at the source (n-type) of the MNR becomes lower than the voltage VBB at the well or semiconductor substrate (p-type). Therefore, the pn junction between the drain or source and the well or semiconductor substrate is turned on, resulting in latch-up. On the other hand, as shown in FIG. 1(a), V
If BB=VEE=-5.2V, even if the potential of the bit line becomes -3.OV during writing, the pn junction will not turn on and latch-up will not occur.

Note that this example shows an example in which the transfer gate is NMO3, but if the transfer gate is PMO3,
It is clear that similar effects can be obtained by using VBB)VC.

Note that when VBB)VC or VBB<VE, latch-up resistance can be improved by changing the bit line potential VB to VB)VC or VB(
The present invention is not limited to the case where the drive is performed at VE. This is because, for example, in FIG. 2(b), the bit line potential undershoots during writing,
This is because V B < VE.

FIG. 1(b) is a diagram showing a second embodiment of the present invention. The difference between FIG. 1(b) and FIG. 1(a) is that in FIG. 1(b), QIBL and QIBR of FIG. 1(a) are removed and a constant current source IBL is used.

The only difference is that the IBR is directly connected to the bit line. Therefore, in this example as well, the argument described in FIG. 1(a) holds true, and it is possible to speed up the writing time and improve latch-up resistance.

In addition, in FIG. 1(b), the constant current sources I B I-, , I I
The reason why 3R is connected directly to the bit line is that by doing this, the number of driving transistors for vYINl and ■YIN2 is reduced, and the load on the bit line driver is reduced accordingly. This is because the access time when reading information can be further speeded up.

FIG. 3 is a diagram showing a third embodiment of the present invention. Chapter:
The difference between FIG. 3 (tl) and FIG. 1(b) is that read/write control signals 1. The only difference is that the input positions of FWE, DI, and DI' have been exchanged. Also, FIG. 3(b) is the third
The difference from Fig. 3(a) is that in Fig. 3(a), QWL, QW
Whereas the WE multiplied signal was input to the base of R, in Fig. 3(b), a constant voltage VWREF was input to the bases of QWL and QWR.
, and instead, the signal resulting from performing a logical 31 calculation (in this example, AND calculation) with the bit line selection signal VYIN and the read/write control signal WE is manually input to the base of QIWL and QIWR. Only. Therefore, in this example as well, the argument described with reference to FIG. 1(a) holds true, and it is possible to speed up the writing time and improve latch-up resistance.

It is clear that the same changes as the changes from FIG. 3(a) to FIG. 3(1)) can be made in FIG. 1 and FIGS. 4 to 9 described below.

FIG. 4 is a diagram showing a fourth embodiment of the present invention. Fourth
The difference between the diagram and Figure 1(b) is that in Figure 4, QYYL and QYYR in Figure 1(b) (QYL, QYYR in Figure 4)
The signal VYINI' (in Fig. 4, VY
), constant voltage source VYY, resistor RY, and transistor Q
The only difference is that the signal is generated from the signal VYINI by the constant current source IY and the constant current source IY. Therefore, in this example as well, Figure 1 (a
) is valid as is, and it is possible to speed up the writing time and improve latch-up resistance.

The reason why the signal VY is generated from the signal VYINI in FIG. 4 is that by doing so, there is no need to input the signal VYINI' from the outside.

5 is a diagram showing a fifth embodiment of the present invention. 1. The difference between FIG. 5 and FIG. 3(a) is that in FIG.
The only difference is that QYL and QYT transistors, which were not present in Figure (a), are added. Therefore, in this example as well, Figure 1 (
The argument described in a) holds true as is, and it is possible to increase the writing time and improve latch-up resistance.

The reason for adding transistors QYT, ..., QYR (=J) in Fig. 5 is that by doing this, the potential of the bit line when reading information is determined from WE2, and for example, I).
This is because even if the level of I, I)I' varies, it does not affect the potential of the bit line, so malfunction of the differential amplifier can be prevented.

FIG. 6 is a diagram showing a sixth embodiment of the present invention. 6th
The difference between Fig. 1(b) and Fig. 6(a) is that Fig. 6(a)
Now, Q Y I- in FIG. 1 (1)).

A signal corresponding to the signal WE manually input to Q y r< is connected to a constant voltage source VYY and a resistor RYI4. RYR, transistor QIYL, QIYR and constant current source IYL.

7YR, signal VYINI and signal 1) I.

1) Only points originating from I'. Therefore, in this example as well, the argument described in FIG. 1(a) is valid.7.
71) It is possible to speed up the reading time and improve latch-up resistance.

The reason why the signals manually input to QYL and QYR in Fig. 6 (a) are generated from the signal VY I N I and the signals DI and D Bi is that by doing this, there is no need to manually input the signal WE from the outside. It is from.

In addition, the capacitance CYL connected to the base of QYL and QYR,
CYR is written and QYL or Q Y R
This capacitance reduces the overshoot of the bit line that occurs when charging the bit line and speeds up the write recovery time.

In addition, the address buffer (AI) I) R shown in this example
1mi SS BUFFER), decoder (DECODER)
) and the output circuit ((lU'l'l) old Cll1C rule ``I'') are well-known circuits, so a description of the operation of these circuits will be omitted here.

Further, the explanation regarding the circuit operation of the driver (DPIVIER) shown in this example can be found in, for example, Japanese Patent Application No. 01-0848.
It is stated in No. 63. Note that these circuits are just examples, and the present invention is not limited to these circuits.

Further, the voltage values and current values shown in this example are only examples, and the present invention is not limited to these.

Figure 6(b) is different from Figure 3(a) in Figure 6(a).
FIG. 4 is a diagram showing an example in which a change similar to the change from FIG. 3(b) is made.

FIG. 7 is a diagram showing a seventh embodiment of the present invention. 7th
The difference between the figure and FIG. 6(a) is that in FIG. 6(a), V
IWL, I due to the potential relationship between the YIN signal and the DI, DI' signals.
While switching between WR, IYL, and IYR, the 7th
In the figure, IW, IY
The only difference is that the . 7, each of IWL, IWR, IYL, and IYR in FIG. 6(a) can be halved, resulting in lower power consumption. Note that WE in FIG. 7 may be a constant voltage, or DI.

It may be a differential signal with respect to the DI' signal.

It should be noted that changes similar to the changes from FIG. 6(a) to FIG. 7 can be made in FIGS. 1, 3 to 5, and FIGS. 8 to 9 described below. it is obvious.

FIG. 8 is a diagram showing an eighth embodiment of the present invention. 8th
The difference between the figure and FIG. 6(a) is that in FIG. 8, the capacitances CYL and CYR in FIG. 6(a) are removed, and instead,
The only difference is that a constant voltage source VCL and transistors QCLL and QCLR are provided. Therefore, in this example as well, Figure 1 (
The argument stated in a) holds true as is, and it is possible to speed up the writing time and improve latch-up resistance.

In this example, the reason why CYL and CYR are removed and VCL, QCLL and QCLR are provided in their place is that the potential of the bit line at the time of reading information is determined from QCLL and QCLR, and instead, the resistors RYL, Increase the resistance value of RYR and QCL L.

This is because even if the time constant of the emitter node of the QCLR is increased, overshoot of the bit line that occurs when writing ends can be reduced, and the write recovery time can be increased.

FIG. 9 is a diagram showing a ninth embodiment of the present invention. 1. The difference between FIG. 9 and FIG. 6(a) is that in FIG. 6(a), the data of the memory cell is output as is. Whereas,
In FIG. 9, the only difference is that the data in the memory cell and the data from the outside are compared for each bit line, and the comparison results are output.

Therefore, in this example as well, the argument described with reference to FIG. 1(a) holds true, and it is possible to speed up the writing time and improve the resistance to deception and build-up.

Note that in this example, the exclusive OR of the data in the memory cell and the data from the outside (AL, AR) is performed.
OR) and output the result to DL and DR.

The above embodiments mainly show examples in which the memory cell is configured by cross-coupling a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor. It is not limited to. That is, for example, a memory cell in which the above insulated gate field effect transistor is replaced with a junction field effect transistor, or a memory cell configured with a resistive load and an N-channel field effect transistor may be used. ,Also,
A memory cell configured with a resistive load and a P-channel TA field effect transistor may also be used.

[Effects of the Invention] As described above, by using the present invention, it is possible to speed up the writing time and improve latch-up resistance.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are circuit diagrams showing the first and second embodiments of the present invention, respectively. FIG. 2(a) is a circuit diagram showing a conventional example, and FIG. 3(a) and 3(b) are circuit diagrams showing a third embodiment of the present invention; FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention; FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention, FIG. 6(a), (
b) is a circuit diagram showing the sixth embodiment of the present invention, FIG. 7 is a circuit diagram showing the seventh embodiment of the present invention, and FIG. 8 is a circuit diagram showing the eighth embodiment of the present invention. 9 are circuit diagrams showing a ninth embodiment of the present invention. 1 Explanation of symbols 11 to MC22...Memory cell, W2...
...Word line 1, BRI, BL2. BR2...Bit line, Nl
, VYIN2...Bit line selection signal. C Wl. L I YI

Claims (1)

[Claims] 1. A memory cell is provided at the intersection of a word line and a bit line, and the memory cell has potentials VC and VE (VC>VE).
In a semiconductor memory having a configuration of a flip-flop made of a field effect transistor to which is applied, and a transfer gate that transfers data between the flip-flop and the bit line, when writing data to the memory cell. Let the potential VB of the bit line be VB>VC
Alternatively, a semiconductor memory characterized by being driven such that VB<VE. 2. A memory cell is provided at the intersection of a word line and a bit line, and the memory cell has potentials VC and VE (VC>VE).
In a semiconductor memory having a configuration of a flip-flop made of a field effect transistor to which is applied, and a transfer gate that transfers data between the flip-flop and the bit line, the transfer gate or the flip-flop is configured. The potential VBB of the well or semiconductor substrate where the transistor is formed, and the potential VB of the bit line when writing data to the memory cell.
A semiconductor memory characterized in that: VBB>VB>VC or VBB<VB<VE.