JPH04217387A - Electroless plating method for conductor pattern and electroless plating jig - Google Patents

Electroless plating method for conductor pattern and electroless plating jig

Info

Publication number
JPH04217387A
JPH04217387A JP41142190A JP41142190A JPH04217387A JP H04217387 A JPH04217387 A JP H04217387A JP 41142190 A JP41142190 A JP 41142190A JP 41142190 A JP41142190 A JP 41142190A JP H04217387 A JPH04217387 A JP H04217387A
Authority
JP
Japan
Prior art keywords
jig
conductor pattern
electroless plating
plating
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP41142190A
Other languages
Japanese (ja)
Inventor
Hideki Shibuya
渋谷 秀樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Chemi Con Corp
Original Assignee
Nippon Chemi Con Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Chemi Con Corp filed Critical Nippon Chemi Con Corp
Priority to JP41142190A priority Critical patent/JPH04217387A/en
Publication of JPH04217387A publication Critical patent/JPH04217387A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form an equalized conducting layer regardless of the types of conductor patterns or the degree of activity of their surface by further enhancing the equipotential of a conductor pattern to be plated and carrying out plating processing. CONSTITUTION:An equipotential jig 6 is used as an electroless plating jig which produces the uniform potential of each conductor pattern 4 by bringing the jig into contact with the conductor pattern 4 in a circuit board 2. This equipotential jig 6 is designed to project a large number of contactors 10 into a net-like conductor frame 8 where the span of each contactor is set so that it may respond to a minimum span between each conductor pattern 4 or smaller. The circuit board 2 is submerged in a plating solution 14 in a plating tank 12. When it is submerged, each contactor 10 of the equipotential jig 6 is placed into contact with the conductor pattern 4 while the equipotential jig is grounded as well.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、回路導体に無電解め
っきを施す場合に用いる導体パターンの無電解めっき方
法及び無電解めっき用治具に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for electroless plating of conductor patterns and a jig for electroless plating, which are used when electroless plating is applied to circuit conductors.

【0002】0002

【従来の技術】混成集積回路等に用いられる回路基板で
は、絶縁材料で形成された基板上に目的とする回路形態
に応じた導体パターンを印刷等で形成し、この導体パタ
ーン上に導体抵抗を低下させる目的でCu層を無電解め
っきによって形成することが行われている。
[Prior Art] In circuit boards used for hybrid integrated circuits, etc., a conductor pattern corresponding to the desired circuit form is formed on a board made of an insulating material by printing or the like, and a conductor resistor is placed on this conductor pattern. For the purpose of reducing this, a Cu layer is formed by electroless plating.

【0003】0003

【発明が解決しようとする課題】ところで、無電解めっ
きによる導体パターンへのCu層の生成は、導体パター
ンの面積等の形態や、その表面の活性度等に依存するこ
とが知られ、層の厚さや局所的にCu層が生成しないむ
らを生じさせるものである。このようなむらを防止する
には、長時間めっき液に回路基板を浸漬すればよいが、
その浸漬時間が長くなると、Cuの析出が良好な部分で
はCu層の厚さが部分的に厚くなり、却ってCu層の厚
さにばらつきを生じ、平坦度が損なわれることになる。 また、めっき液中への浸漬時間が長くなると、その分だ
け製造時間が長くなり、製造コストを増大させることに
もなる。
[Problems to be Solved by the Invention] Incidentally, it is known that the formation of a Cu layer on a conductor pattern by electroless plating depends on the form such as the area of the conductor pattern and the activity level of its surface. This causes unevenness in thickness and localized Cu layer formation. To prevent such unevenness, it is possible to immerse the circuit board in the plating solution for a long time.
When the immersion time becomes longer, the thickness of the Cu layer becomes thicker in parts where Cu is well deposited, and the thickness of the Cu layer becomes uneven, which impairs the flatness. Furthermore, if the immersion time in the plating solution becomes longer, the manufacturing time increases accordingly, which also increases the manufacturing cost.

【0004】そこで、この発明は、導体パターンの形態
や、その表面の活性度に無関係に均一な導体層が形成で
きる導体パターンの無電解めっき方法の提供を第1の目
的とする。
[0004] Accordingly, a first object of the present invention is to provide a method for electroless plating of a conductor pattern, which can form a uniform conductor layer regardless of the form of the conductor pattern or the degree of activity of its surface.

【0005】また、この発明は、導体パターンの形態や
、その表面の活性度に無関係に均一に、めっきすべき導
体パターンをめっき液中で等電位化できる無電解めっき
用治具の提供を第2の目的とする。
Another object of the present invention is to provide an electroless plating jig that can uniformly equalize the potential of a conductor pattern to be plated in a plating solution, regardless of the form of the conductor pattern or the activity level of its surface. 2 objectives.

【0006】[0006]

【課題を解決するための手段】即ち、この発明の導体パ
ターンの無電解めっき方法は、多数の導体パターン(4
)が形成された回路基板(2)をめっき液(14)に浸
漬するとともに、導体めっきを施すべき前記導体パター
ンを等電位化してめっき処理を行うことを特徴とする。
[Means for Solving the Problem] That is, the electroless plating method for conductor patterns of the present invention provides a method for electroless plating of conductor patterns in a large number of conductor patterns (4
) is characterized in that the plating process is performed by immersing the circuit board (2) on which the plating pattern (2) is formed in a plating solution (14) and equalizing the potential of the conductive pattern to which conductive plating is to be applied.

【0007】また、この発明の導体パターンの無電解め
っき用治具は、回路基板(2)に形成された導体パター
ン(4)に接触するとともに、共通に接続された複数の
接触子(10)を備えたことを特徴とする。
[0007] The jig for electroless plating of a conductor pattern of the present invention also contacts a conductor pattern (4) formed on a circuit board (2), and also has a plurality of commonly connected contacts (10). It is characterized by having the following.

【0008】[0008]

【作用】無電解めっきによって導体層を形成すべき回路
基板の導体パターンはめっき液中で等電位化されるので
、各導体パターンにはめっき液中から導体層が均一に析
出され、その導体層の形成むらや厚さむらの発生が確実
に防止される。
[Operation] The conductor patterns of the circuit board on which the conductor layer is to be formed by electroless plating are equalized in potential in the plating solution, so a conductor layer is uniformly deposited from the plating solution on each conductor pattern, and the conductor layer is The occurrence of uneven formation and uneven thickness is reliably prevented.

【0009】また、無電解めっき用治具には、多数の接
触子が形成され、各接触子は共通に接続されている。し
たがって、めっきを施すべき導体パターンに接触子をめ
っき液中で接触させ、各接触子を通して各導体パターン
の等電位化、例えば、接地すれば、導体パターンに対す
る導体層の形成を均一化することができる。
[0009] Furthermore, a large number of contacts are formed on the electroless plating jig, and each contact is commonly connected. Therefore, by bringing a contact into contact with the conductor pattern to be plated in a plating solution and equalizing the potential of each conductor pattern through each contact, for example, by grounding, it is possible to uniformize the formation of the conductor layer on the conductor pattern. can.

【0010】0010

【実施例】図1及び図2は、この導体パターンの無電解
めっき方法及び無電解めっき用治具を示す。アルミナ等
の絶縁材料を以て回路基板2が形成されており、この回
路基板2の表面には、実装される電子回路を構成すべき
回路パターンに応じて多数の導体パターン4が導体ペー
スト、例えばAgペースト等で印刷により形成されてい
る。
EXAMPLE FIGS. 1 and 2 show a method for electroless plating of a conductor pattern and a jig for electroless plating. A circuit board 2 is formed of an insulating material such as alumina, and a large number of conductor patterns 4 are formed on the surface of the circuit board 2 with a conductor paste, such as Ag paste, depending on the circuit pattern to constitute the electronic circuit to be mounted. It is formed by printing, etc.

【0011】この回路基板2の導体パターン4に接触さ
せて各導体パターン4を等電位化する無電解めっき用治
具としての等電位化治具6が用いられる。この等電位化
治具6は、網目上の導体枠8に多数の接触子10を突出
させたものであり、各接触子10の間隔は、各導体パタ
ーン4間の最小間隔以下に対応する大きさに設定されて
いる。
A potential equalization jig 6 is used as an electroless plating jig that contacts the conductor patterns 4 of the circuit board 2 to equalize the potential of each conductor pattern 4. This potential equalization jig 6 has a large number of contacts 10 protruding from a conductor frame 8 on a mesh, and the distance between each contact 10 is a size corresponding to the minimum distance between each conductor pattern 4 or less. It is set to

【0012】そして、回路基板2は、図1に示すように
、めっき槽12内のめっき液14中に浸漬され、このと
き、その導体パターン4には等電位化治具6の各接触子
10を接触させるとともに、その等電位化治具6を接地
する。この結果、回路基板2の各導体パターン4は、等
電位化治具6を通して共通化されるとともに接地され、
各導体パターン4の活性点及び不活性点は等電位化治具
6を以て等電位化され、この場合、接地電位に等電位化
される。
Then, as shown in FIG. 1, the circuit board 2 is immersed in the plating solution 14 in the plating bath 12, and at this time, each contact 10 of the potential equalization jig 6 is attached to the conductor pattern 4. are brought into contact with each other, and the potential equalization jig 6 is grounded. As a result, each conductor pattern 4 on the circuit board 2 is shared and grounded through the potential equalization jig 6.
The active points and inactive points of each conductor pattern 4 are equalized using a potential equalization jig 6, and in this case, the potential is equalized to the ground potential.

【0013】即ち、図3の(A)に示す回路基板2上の
導体パターン4は、等電位化治具6を以て等電位化され
、めっき液14中でその表面にめっき金属の析出が始ま
る。この析出の開始により、等電位化治具6は回路基板
2から外す。一旦、めっきが開始されると、連続的にめ
っき金属の析出が始まり、図3の(B)に示すように、
めっき液14のめっき金属に応じ、導体パターン4の表
面には導体層として例えば、Cu層16が析出し、Cu
層16は一様の膜厚に形成される。このCu層16の析
出反応式を次に示す。
Specifically, the conductor pattern 4 on the circuit board 2 shown in FIG. With the start of this deposition, the potential equalization jig 6 is removed from the circuit board 2. Once plating has started, the plating metal begins to be deposited continuously, as shown in FIG. 3(B).
Depending on the plating metal of the plating solution 14, for example, a Cu layer 16 is deposited as a conductive layer on the surface of the conductive pattern 4,
Layer 16 is formed to have a uniform thickness. The precipitation reaction formula of this Cu layer 16 is shown below.

【0014】[0014]

【化1】[Chemical formula 1]

【0015】このように、無電解めっき処理において、
回路基板2の導体パターン4の全部を等電位化治具6を
以て等電位化したことにより、導体パターン4の形状、
大きさ等により、活性点から不活性点に対する電子(e
− )の移動によって抑制される結果、表面の活性度が
異なることによって生じていためっき層の偏りやむらの
発生が防止され、均一な膜厚を持つCu層16が析出さ
れる。しかも、各導体パターン4には等電位化治具6の
接触により、同時にめっきが進行することから、所定の
膜厚を得るに必要な処理時間が短縮化される。
[0015] In this way, in the electroless plating process,
By equipotentializing all of the conductor patterns 4 of the circuit board 2 using the potential equalization jig 6, the shape of the conductor patterns 4,
Depending on the size, etc., the electron (e) from the active point to the inactive point
As a result of being suppressed by the movement of (-), unevenness and unevenness in the plating layer caused by differences in surface activity are prevented, and a Cu layer 16 having a uniform thickness is deposited. Moreover, since the plating progresses at the same time by contacting each conductor pattern 4 with the potential equalization jig 6, the processing time required to obtain a predetermined film thickness is shortened.

【0016】また、等電位化治具6は、極めて簡単な構
造であり、その取扱いもめっき金属の析出時に回路基板
2から取り外せばよいため、めっき処理ごとに取替える
必要はなく、半永久的に使用できる。
In addition, the potential equalization jig 6 has an extremely simple structure, and can be handled semi-permanently without having to be replaced every time the plating process is performed, since it can be handled by simply removing it from the circuit board 2 at the time of depositing the plating metal. can.

【0017】[0017]

【発明の効果】以上説明したように、この発明の無電解
めっき方法によれば、無電解めっきを施すべき多数の導
体パターンが形成された回路基板は、めっき液中で等電
位化するので、各導体パターンに均一に導体層を形成す
ることができ、めっき処理時間を短縮することができ、
品質の向上とともに製造コストを低減できる。
[Effects of the Invention] As explained above, according to the electroless plating method of the present invention, the circuit board on which a large number of conductor patterns to be electroless plated are formed is made to have an equal potential in the plating solution. A conductor layer can be formed uniformly on each conductor pattern, reducing plating time.
It is possible to reduce manufacturing costs while improving quality.

【0018】また、この発明の無電解めっき用治具によ
れば、無電解めっきを施すべき導体パターンが形成され
た回路基板を、めっき液中で容易かつ確実に等電位化す
ることができ、導体パターンに形成すべき導体層の形成
を均一かつ高速度化することができる。
Further, according to the electroless plating jig of the present invention, a circuit board on which a conductor pattern to be electroless plated is formed can be easily and reliably equalized in potential in a plating solution. A conductor layer to be formed on a conductor pattern can be formed uniformly and at high speed.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明の導体パターンの無電解めっき方法及
び無電解めっき用治具を示す図である。
FIG. 1 is a diagram showing a method for electroless plating a conductor pattern and a jig for electroless plating according to the present invention.

【図2】無電解めっきを施すべき導体パターンが形成さ
れた回路基板及び無電解めっき用治具を示す斜視図であ
る。
FIG. 2 is a perspective view showing a circuit board on which a conductor pattern to be subjected to electroless plating is formed and an electroless plating jig.

【図3】無電解めっきの処理前及び処理後を示す導体パ
ターンが形成された回路基板を示す断面図である。
FIG. 3 is a cross-sectional view showing a circuit board on which a conductive pattern is formed, showing before and after electroless plating.

【符号の説明】[Explanation of symbols]

2    回路基板 4    導体パターン 6    等電位化治具 10  接触子 14  めっき液 2 Circuit board 4 Conductor pattern 6 Potential equalization jig 10 Contact 14 Plating solution

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  表面に導体パターンが形成された回路
基板をめっき液に浸漬するとともに、導体めっきを施す
べき前記導体パターンを等電位化してめっき処理を行う
ことを特徴とする導体パターンの無電解めっき方法。
1. Electroless plating of a conductor pattern, characterized in that a circuit board with a conductor pattern formed on its surface is immersed in a plating solution, and the conductor pattern to be subjected to conductor plating is made to have an equal potential to perform the plating process. Plating method.
【請求項2】  回路基板に形成された導体パターンに
接触するとともに、共通に接続された複数の接触子を備
えたことを特徴とする無電解めっき用治具。
2. A jig for electroless plating, comprising a plurality of contacts that come into contact with a conductor pattern formed on a circuit board and are connected in common.
JP41142190A 1990-12-18 1990-12-18 Electroless plating method for conductor pattern and electroless plating jig Pending JPH04217387A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP41142190A JPH04217387A (en) 1990-12-18 1990-12-18 Electroless plating method for conductor pattern and electroless plating jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP41142190A JPH04217387A (en) 1990-12-18 1990-12-18 Electroless plating method for conductor pattern and electroless plating jig

Publications (1)

Publication Number Publication Date
JPH04217387A true JPH04217387A (en) 1992-08-07

Family

ID=18520433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP41142190A Pending JPH04217387A (en) 1990-12-18 1990-12-18 Electroless plating method for conductor pattern and electroless plating jig

Country Status (1)

Country Link
JP (1) JPH04217387A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249854A (en) * 1994-03-10 1995-09-26 Sakae Denshi Kogyo Kk Method and device of plating printed board
JP2001240976A (en) * 2000-02-29 2001-09-04 Toshiba Tec Corp Electroless plating method, method for manufacturing ink jet head and electrode substrate
JP2007524757A (en) * 2003-07-01 2007-08-30 フリースケール セミコンダクター インコーポレイテッド Electroless and immersion plating of integrated circuits using activated plates.
JP2010238949A (en) * 2009-03-31 2010-10-21 Hitachi Metals Ltd Circuit board, and method of manufacturing the same
JP2012241236A (en) * 2011-05-19 2012-12-10 Nitto Denko Corp Electroless plating apparatus, electroless plating method and method for manufacturing wiring circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249854A (en) * 1994-03-10 1995-09-26 Sakae Denshi Kogyo Kk Method and device of plating printed board
JP2001240976A (en) * 2000-02-29 2001-09-04 Toshiba Tec Corp Electroless plating method, method for manufacturing ink jet head and electrode substrate
JP2007524757A (en) * 2003-07-01 2007-08-30 フリースケール セミコンダクター インコーポレイテッド Electroless and immersion plating of integrated circuits using activated plates.
JP2010238949A (en) * 2009-03-31 2010-10-21 Hitachi Metals Ltd Circuit board, and method of manufacturing the same
JP2012241236A (en) * 2011-05-19 2012-12-10 Nitto Denko Corp Electroless plating apparatus, electroless plating method and method for manufacturing wiring circuit board

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