JPH04215323A - Paging receiver - Google Patents

Abstract

PURPOSE:To manage the product as a single product by writing a frequency division number of a programmable frequency divider into a writable ROM. CONSTITUTION:With a power switch Sw turned on, a CPU 1 detects it and gives a start signal to a decoder 22. The decoder 22 receiving the signal reads a frame, an address and frequency division information or the like given to itself from a PROM 21 and the frame, address are set in a register of the decoder 22 and the frequency division information is fed to a programmable frequency divider 20, in which the information is set therein. Thus, a signal lower than the signal to be received by a mixer circuit 6 is given from a PLL synthesizer 15. The reception signal given to the mixer circuit 6 is mixed with a signal from the PLL synthesizer 15 in the mixer circuit 16 and the result is converted into a 455kHz signal by a frequency conversion circuit and the result is given to a frequency discriminator 12. A CPU 1 implements lighting of a LED 29, calls a speaker 31, display to a display section 32 and storage to a RAM 25.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a paging receiver.

[Prior art and its problems] A conventional paging receiver is equipped with a local oscillation circuit using a crystal as an oscillation source, and a mixer circuit that mixes a constant frequency signal from the local oscillation circuit with a received signal is provided at a subsequent stage. The frequency band of the signal that can pass is fixed and a narrow band pass filter (crystal filter, surface acoustic wave filter, etc.) is provided, and the received signal has a predetermined frequency difference with respect to the frequency signal output from the local oscillation circuit. The configuration was such that only the second part of the signal was demodulated by the subsequent circuit. In other words, in the conventional paging receiver, the frequency of the signal that can be received is determined at the stage of incorporating the local oscillator in the manufacturing process.

By the way, in a paging system, in order to prevent interference between a certain paging service area (area where you can receive paging service with one contract) and other paging service areas nearby, the transmission frequency is gradually changed for each paging service area. It's changing. Therefore, when manufacturing paging receivers, it is necessary to incorporate a crystal oscillation circuit (local oscillation circuit) into each paging receiver that matches the transmission frequency of the paging service area in which the paging receiver is used. In the end, it was necessary to manufacture a large number of models with different configurations for each frequency, which caused the inconvenience of not being able to manage the manufacturing of a single product.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a paging receiver that can be manufactured and managed as a single product.

[Summary of the Invention] In order to achieve the above object, the present invention uses a PLL synthesizer as a local oscillation circuit of a frequency conversion section, and individually calls the frequency division number of a programmable frequency divider that determines the oscillation frequency of this PLL synthesizer. The gist is that the information is provided by writing it into a writable ROM that stores information.

[Example] The present invention will be specifically described below based on an example shown in the drawings. In this embodiment, a plurality of transmission signals having a frequency of 280 MHz are received, and the receiving section includes a double superheterodyne receiving circuit in which the first intermediate wave is 21.4 MHz and the second intermediate wave is 455 KHz. We are hiring.

Configuration FIG. 1 shows the circuit configuration of this embodiment. That is, the configuration is such that each circuit is connected to the CPU 1. The CPU 1 is a circuit that processes and processes data from each circuit section and sends it out, and also sends control signals to each circuit to control them.

The receiving unit 3 is a circuit unit that receives a frequency-modulated reception signal from the antenna 2 and demodulates it. In this embodiment, as described above, the first intermediate wave is 21.4 MHz.
, the second intermediate wave is composed of a double superheterodyne receiving circuit of 455 KHz. The RF amplifier 4 is a circuit that amplifies the high frequency reception signal received via the antenna 2, and the bandpass filter 5 amplifies components in a predetermined frequency range in order to remove noise etc. from the high frequency reception signal amplified by the RF amplifier 4. This circuit selectively extracts and sends it to the mixing circuit 6. Note that the predetermined frequency range in this case is a range that covers the frequencies of all transmission signals that may be set for reception. The mixing circuit 6 is a PL described below.
This is a circuit that mixes the frequency signal from the L synthesizer 15 with the signal from the bandpass filter 5. The bandpass filter 7 mixes the frequency signal from the L synthesizer 15 with the signal from the mixing circuit 6 at a predetermined frequency (21.4 MHz in this embodiment). This circuit selectively takes out only the components and sends them to the mixing circuit 8. Therefore, only the received signal with a frequency difference of 21.4 MHz from the output frequency of the PLL synthesizer 15 is sent to the mixing circuit 6, the PLL
A frequency conversion circuit including a synthesizer 15 and a bandpass filter 7 converts the frequency to 21.4 MHz. The mixing circuit 8 is a circuit that mixes the frequency signal from the local oscillation circuit 9 with the signal from the band-pass filter 7 and sends it to the band-pass filter 10.
0 is a circuit that extracts only a component of a predetermined frequency (455 KHz in this embodiment) from the signal wave from the mixing circuit 8 and sends it to the IF amplifier 11. That is, the local oscillation circuit 9,
A second frequency conversion is performed by the mixing circuit 8 and the bandpass filter 10, and the bandpass filters 7 to 21.
A 4MHz signal is converted to 455KHz. The IF amplifier 11 undergoes frequency conversion twice as described above,
This circuit amplifies the received signal as a 455KHz intermediate frequency signal. The frequency discriminator 12 is the IF amplifier 11
The low-pass filter 13 removes high frequency components from the signal wave demodulated by the frequency discriminator 12, and then sends the signal wave to the waveform shaping circuit 14. This is a circuit that does this. Further, the waveform shaping circuit 14 is a circuit that adjusts the waveform of the signal from the low-pass filter 13.

As described above, the PLL synthesizer 15 is a circuit that works as a local oscillator that sends a frequency signal to the mixing circuit 6. In this PLL synthesizer 15, the reference oscillation circuit 16 is a circuit that sends out a constant frequency signal, and the phase comparator 17 outputs the frequency signal from the reference oscillation circuit 16 and the divided output from the programmable frequency divider 20. The frequency and phase of the two are compared and an average DC voltage proportional to the error is generated. The output voltage from this phase comparator 17 is given to a voltage controlled oscillator 19 via a loop filter 18, and the pressure controlled oscillator 19 changes the output frequency in a direction that reduces the error based on the given voltage, and finally is a circuit that sends out a signal wave of a constant frequency, and this signal wave is given to the mixing circuit 6 and the programmable frequency divider 20. The programmable frequency divider 20 is a circuit that divides the frequency of the signal wave from the voltage controlled oscillator 19 based on frequency division number information sent from the PROM 21 via the decoder 22 and provides the divided signal wave to the phase comparator 17. Therefore, the reference oscillation circuit 16
The frequency of the signal from is f0, and the programmable frequency divider 2
When the frequency division number given to 0 is N, the frequency f1 of the signal output from the voltage controlled oscillator 19 is f1=N
・It becomes f0.

The PROM 21 is a writable ROM that stores not only frames and addresses individually assigned to the paging receiver, but also division number information given to the programmable frequency divider 20 described above. The stored data is sent to the decoder 22 under the control of the decoder 22.

Note that writing or rewriting of the frequency division number information and the like to the PROM 21 is performed by a ROM writer at the manufacturer immediately before shipping, and at a paging service company when the receiver is rented out. For example, when the frequency to be received is 280 MHz and the output frequency of the reference oscillation circuit 16 of the PLL synthesizer is 25 KHz, the frequency division information written in the PROM 21 is "10344",
The frequency to be received is 280.025M of the adjacent channel
If it is Hz, it is "10345". Decoder 2
2 transfers the received signal demodulated by the receiver 3 to the PROM 2.
It is a circuit section that decodes data based on the data from CPU 1 and, when it is sent to itself, sends a coincidence detection signal and a subsequently received message information signal to CPU 1. The decoder 22 also turns on and off the electronic switch 23 in accordance with the timing of transmission to itself based on the frame data from the PROM 21, and controls the battery 35.
It also has a function of intermittent power supply to the receiving unit 3 via the power switch Sw.

The RAM 25 stores data from the CPU 1 under the control of the CPU 1, and also transfers the stored data to the CPU.
This is a circuit that sends data to 1. The oscillation circuit 26 is a circuit that always sends a signal of a constant frequency to the CPU 1 as a timing signal. The key input unit 27 is a circuit that includes a large number of keys and sends a corresponding key input signal to the CPU 1 when any one of the keys is operated. When there is reception, the drive circuit 28 receives a signal from the CPU 1 and outputs an L signal.
This is a circuit that drives the ED 29, and the LED 29 is driven by the drive circuit 28 to light up or blink to notify reception. The drive circuit 30 controls the CPU when there is reception.
The speaker 31 is driven by the drive circuit 30 and generates a ringing tone or the like. The display unit 32 is a circuit unit that includes a liquid crystal display panel and displays data from the CPU 1 thereon.

The booster circuit 34 is a circuit unit that boosts the voltage of the power supply from the battery 35 to a predetermined voltage, and supplies the voltage to the PLL synthesizer 15 and the display unit 32. Power switch S
w is a switch that is controlled to be turned on or off by a user's operation, and that cuts off the power supply to the decoder 22 and the like. Note that the CPU 1 detects whether the power switch Sw is on or off using the signal D. Also, CPU1, RAM25
, oscillation circuit 26, etc., the processing circuit section 33 is always equipped with
The configuration is such that power is supplied from a battery 35.

Operation Next, the operation of this embodiment configured as described above will be explained.

When the power switch Sw is turned on, CPU1
detects this using signal D and provides an activation signal to decoder 22. Upon receiving this activation signal, the decoder 22
The frame, address, frequency division number information, etc. given to the decoder 22 are read from the ROM 21, and the frame and address are respectively set in specified registers in the decoder 22, and the frequency division information is set in the PLL synthesizer 15.
The signal is sent to the programmable frequency divider 20 and set.

As a result, a signal whose frequency is 21.4 MHz lower than the frequency of the signal to be received is provided from the PLL synthesizer 15 to the mixing circuit 6. And antenna 2, RF amplifier 4
The received signal given to the mixing circuit 6 via the band pass filter 5 is mixed with the frequency signal from the PLL synthesizer 15 in the mixing circuit 6, and converted to a 21.4 MHz frequency signal via the band pass filter 7. be done.

The received signal frequency-converted in this way is further converted into a 455 KHz frequency signal by a frequency conversion circuit consisting of a mixing circuit 8, a local oscillation circuit 9, and a band-pass filter 10, and then sent to a frequency discriminator 12 via an IF amplifier 11. The signal is then demodulated by the frequency discriminator 12, passed through the low-pass filter 13, the waveform shaping circuit 14, and then sent to the decoder 22.

As described above, when a received signal is sent to the decoder 22, the decoder 22 checks whether the received signal is sent to itself based on the address data from the PROM 21, and determines whether the received signal is sent to itself. If so, a match detection signal and a subsequently received message information signal are sent to the CPU 1. At this time, the CPU 1 controls the drive circuit 2.
8 and 30 to issue a call notification using the LED 29 and speaker 31, and store the received data in the RAM 25 and display it on the display unit 32.

Note that the present invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the gist of the present invention. For example, in this embodiment, the frequency conversion in the receiving section is
A PLL synthesizer was used as a local oscillator for frequency conversion on one side of a paging receiver that performs the frequency conversion in stages, but the present invention is not limited to this. Of course, it may also be used.

Furthermore, in this embodiment, only the receiving section 3 was driven intermittently by the electronic switch 23, but the PLL synthesizer 15
An electronic switch controlled on and off by a signal from the decoder 22 may also be provided between the PLL synthesizer 15 and the booster circuit 34, and the PLL synthesizer 15 may also be driven intermittently. In this case, considering that it takes a certain amount of time for the oscillation in the PLL synthesizer 15 to stabilize, the PLL synthesizer 15 should be driven at a faster timing than the receiving section 3 for that certain period of time. is preferred.

[Effects of the Invention] As described in detail above, the present invention uses a PLL synthesizer as a local oscillation circuit of a frequency converter, and uses a programmable frequency divider that determines the oscillation frequency of the PLL synthesizer to individually call the frequency division number. Since the present invention relates to a paging receiver in which such information is provided by writing it into a writable ROM, it is possible to provide a paging receiver that can be manufactured and managed as a single product.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. 1...CPU, 2...Antenna, 3...Receiving section, 4...
RF amplifier, 5, 7, 10...Band pass filter, 6
, 8...Mixing circuit, 9...Local oscillation circuit, 11...IF
Amplifier, 12... Frequency discriminator, 13... Low pass filter, 14... Waveform shaping circuit, 15... PLL synthesizer, 16... Reference oscillation circuit, 17... Phase comparator, 1
8...Loop filter, 19...Voltage controlled oscillator. 20...Programmable frequency divider, 21...PROM, 2
2...Decoder, 23...Electronic switch, 25...RA
M, 26...Oscillation circuit, 27...Key input section, 28...
Drive circuit, 29...LED, 30...Drive circuit, 31...
...Speaker, 32...Display section, 33...Processing circuit section, 3
4... Boost circuit, 35... Battery, Sw... Power switch. Patent applicant Casio Computer Co., Ltd.

Claims (1)

[Claims] A PLL synthesizer is used as a local oscillation circuit in the receiving section, and the frequency division number of a programmable frequency divider that determines the oscillation frequency of this PLL synthesizer is provided by writing it into a writable ROM that stores information related to individual calls. A paging receiver characterized by: