JPH04211132A - Heterojunction bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce dispersion in base resistance dependent on the thickness of a base extraction region by a method wherein a compound semiconductor layer containing In of less than a critical film pressure is inserting between an emitter or collector layer and a base layer as the etching stopper. CONSTITUTION:An emitter layer 2, a base layer 3, a p-In0.3Ga0.7As layer 4, and a collector layer 5 are deposited one after another on a semiinsulating substrate 1. The collector layer 5 forms a collector region by patterning with an Au-Ge-Ni layer 8, a silicon oxide film 9, and a photoresist film 10. At this time, base plane exposure is conducted by reactive ion beam etching; therefore, etching stops at the p-In0.3Ga0.7As layer 4, so that the collector layer 5 can be etched selectively. It follows that the step of base plane exposure can be conducted with high controllability over the whole wafer and that increases in base resistance due to underetching or overetching can be prevented.

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor and a method of manufacturing the same. [0002]

2. Description of the Related Art Bipolar transistors have an excellent feature of greater current driving capability than field effect transistors. Therefore, in recent years, research and development of bipolar transistors using not only silicon but also compound semiconductors such as gallium arsenide have been actively conducted. In particular, we focus on heterojunction bipolar transistors using compound semiconductors (
Hereinafter, it will be referred to as HBT. ) has the advantage that emitter injection efficiency can be maintained high even if the base is heavily doped by making the forbidden band width of the emitter larger than that of the base. [00031] Next, an example of a collector-up type HBT will be described along with its manufacturing process.

[0004] First, on a semi-insulating substrate made of GaAs, an n Al 2 O, 25 GaAs upper layer (emitter layer),
The p-GaAs layer (base layer) and n-GaAs layer (collector layer) are sequentially formed using molecular beam epitaxy (hereinafter referred to as MBE).
(written as law). Next, after forming a collector electrode with a predetermined pattern having a silicon oxide film on the surface,
Using this as a mask, the n-GaAs layer is etched to form a collector region. Subsequently, the exposed p-GaAs
A base electrode is formed in a predetermined pattern on the layer. Next, the surface portions of the p-GaAs layer to which the base electrode is not deposited and the underlying nAlO, 25GaO, 75As layers are removed, and an emitter electrode is formed on the exposed n-AlGa+-As layer. [0005] The thickness of the p-GaAs layer on which the base electrode is formed is determined by the etching process (base surface exposure process) for forming the collector layer. In the base surface exposing process, the upper n-GaAs layer is etched to expose a part of the surface of the p-GaAs layer, but if the etching of the n-GaAs layer is insufficient, the gap between the base layer and the base electrode contact resistance increases. Such an increase in contact resistance can be avoided by etching the surface portion of the p-GaAs layer. However, the thickness of the p-GaAs layer (base extraction region) under the base electrode is smaller than that of the active base layer (portion in contact with the collector layer).
Since it becomes thinner, the base resistance increases. In practice, the thickness of the base extraction region must be slightly thinner than the active base layer to avoid an increase in contact resistance. [0006] Therefore, the quality of this process greatly influences the high speed and high frequency characteristics of the final transistor. Furthermore, since the base layer is extremely thin, at 70 to 1100 nm, variations in etching depth within the wafer are one of the causes of significantly reducing the uniformity of device characteristics. Conventionally, it has been very difficult to perform this process over the entire wafer with sufficient controllability, and it has been impossible to avoid variations of about 20 nm on 2-inch wafers. [0007] In the case of an emitter-up type HBT, the base surface exposing process involves etching the AlGaAs layer. It has also been reported that it is possible to selectively remove the AlGaAs layer by wet etching. In other words, "GaAlAs/GaAS" such as Aspek etc.
Heterojunction Bipolar Transistors: Issues and Prospects for Applications'', International Transactions on Electron Devices (P, M, A
SBECK et al., “GaAlAs/G
aAsHeterojunction Bipola
r Transistors: l5sue an
dProspects for Application
ation-IEEE TRANSACTIONS
ON ELECTRON DEVICE)
, Volume 36, No. 10, Page 2032, 1989,
According to October, it is possible to perform surface leveling with a standard deviation of 3 to 4 nm on a 2-inch wafer. However, the inventor was unable to confirm this with sufficient reproducibility. Selective removal of AlGaAs layers is not a fully mature technology. Further, from the viewpoint of simplifying the process, it is not preferable to use wet etching in combination. As far as dry etching is concerned, there is no known means for selectively removing the AlGaAs layer with respect to the GaAs layer, so the same problem as the collector-up type HBT exists. [0008] An object of the present invention is to provide a bipolar transistor with small variations in base resistance and a method for manufacturing the same. [0009]

[Means for Solving the Problems] The HBT of the present invention has a compound semiconductor layer containing In, preferably InGa+-A, between the emitter layer (or collector layer) and the base layer.
s, (0<x<1). Thus, the emitter layer, base layer and collector layer are all made of a semiconductor containing no In. Since the vapor pressure of In chlorides and fluorides is low, dry etching using a gas containing chlorine or fluorine makes it possible to stop etching at the surface of a compound semiconductor layer containing In with good controllability. . Therefore, the controllability of the extraction process for forming the mesa-shaped emitter region (or collector region) is improved. In other words, variations in the thickness of the base lead-out region are reduced, and variations in base resistance are reduced.

0010

[Example] Collector-up type H of the first embodiment of the present invention
BT and its manufacturing method will be explained. (00111 First, as shown in FIGS. 1(a) and 1(b), a film with a thickness of 5 mm is placed on a semi-insulating substrate 1 made of GaAs.
00nm, impurity concentration I per cubic centimeter
n-Al0.25 Gao7s AS layer 2 (emitter layer) of E17 (meaning 10 to the 17th power; hereinafter the same shall apply), 80 m thick, p-GaAs layer 3 (base layer) with impurity concentration of 2E19 per cubic centimeter. layer), 5 nm thick, impurity concentration 2 per cubic centimeter
E19 p-Ino3Gao7As layer 4 and thickness 50
0nm, impurity concentration 2E per cubic centimeter
Seventeen n-GaAs layers 5 (collector layers) are sequentially deposited by the MBE method at a growth temperature of 550°C. Next, HBT
Protons are injected into the portion excluding the rectangular region 6 forming the insulating region 7. [0012] Next, as shown in FIGS. 2(a) and 2(b), an Au-Ge-X1 layer 8 is formed by vapor deposition, a silicon oxide film 9 with a thickness of 500 nm is deposited, and a rectangular region 6 is formed. A rectangular photoresist film 10 crossing over the
form. Using the photoresist film 10 as a mask, the silicon oxide film 9 is patterned by reactive ion beam etching, and Au-Ge-N is etched by ion milling.
Pattern the i-layer 8. [0013] Next, as shown in FIGS. 3A and 3B, after cleaning with an organic solvent and removing the photoresist film 10, using the silicon oxide film 9 as a mask,
The n-GaAs layer 5 is removed by reactive ion beam etching to expose the surface of the p-Ino3Gao7As layer 4. In this way, the collector region is formed. A mixed gas of CCl2F2 and He can be used as the etching gas, but CI2 is preferable from the standpoint of environmental pollution. ECR (Electron Cyclotro)
The etching chamber was set to 1 using a
After exhausting to below μTorr, CI2 gas is introduced to perform etching under the following conditions. [0014] CI2 Gas current 358CCM gas pressure
700μTorr Input microwave power 300W Magnet current 10.2A RF bias power to substrate OW Substrate holder temperature 40-60℃ According to these conditions, the thickness of the GaAs layer or AlGaAs layer is approximately 200nm/m
Although it is etched at a rate of in, p-Ino3Gao
The 7As layer is hardly etched. [0015] Next, a silicon oxide film with a thickness of 200 nm is formed on the entire surface by the CVD method, and by anisotropic reactive ion beam etching, the n-GaAs layer 5 and the Au-G
Insulating sidewalls 11 are formed on the side surfaces of a rectangular parallelepiped made of e-Ni layer 8 and silicon oxide film 9. Next, Figure 4(a)
, as shown in (b), p-Ino3Gao7AS
Light wet etching is performed to remove surface damage to layer 4. Since the p-Ino3Gao7As layer 4 is as thin as 5 nm, it may be completely removed except for the area immediately below the rectangular parallelepiped surrounded by the insulating sidewalls 11. As an etchant, use 4. H3PO4. A solution containing H202 and L H20 mixed in a ratio of 155 is used. In the case of a conventional collector-up HBT, there is no p-Ino3Gao7As layer, but since the insulating sidewalls are formed by reactive ion beam etching, surface damage is usually removed by wet etching. Therefore, this step is not a special additional step. Subsequently, an Au-Zn-Ni layer 12 is formed by a vapor deposition method. The insulating side wall 11 is formed by vapor deposition from above.
The Au--Zn--Ni layer 12 is not deposited on the side surfaces of. [0016] Next, as shown in FIGS. 5(a) and 5(b), the insulating side wall 1 is
A photoresist film 13 covering almost the entire area surrounded by 1
Cover. Subsequently, the Au--Zn--Ni layer is etched by ion milling using the photoresist film 13 as a mask to form the base electrode 12a. [0017] Next, after dissolving the photoresist film 13 in an organic solvent, a photoresist film 15 having U-shaped openings 14 is formed, as shown in FIGS. 4. The p-GaAs layer 3 and n-Alo2s are formed using a solution containing 1 part hydrogen peroxide and 90 parts water.
The surface portion of the Gao7sAS layer 2 is removed. Subsequently, an Au--Ge--Ni layer is formed by vapor deposition from above using the photoresist film 15 as a mask, and lift-off is performed to form the emitter electrode 16. Furthermore, after forming a photoresist film (not shown) with a flat surface over the entire surface, this photoresist film is etched by reactive ion beam etching, and the Au-Zn-Ni layer 12 above the collector layer is removed by ion milling. . [0018] Next, after removing the aforementioned photoresist film, a silicon oxide film 17 with a thickness of 500 nm is formed on the entire surface, as shown in FIGS. 7(a) and 7(b). Figure 7 (a
), the portion covered only with the silicon oxide film 17 is drawn with a solid line. Subsequently, contact holes 18B, 18C, and 18E are provided at predetermined locations in the silicon oxide film 17. The base electrode 12a, collector electrode 8. Emitter electrode 1
Pads (not shown) connected to the silicon oxide film 17 are formed on the silicon oxide film 17. By using etching gas such as C12, InGa+-As (0<Y<1
It is generally known that AI Ga+-As (0≦X≦1) can be selectively etched with respect to ). This is thought to be mainly due to the difference in vapor pressure between the chlorides of Al and Ga and the chlorides of In. ). [0019] According to the present invention, by providing a thin InGa+-As layer at the base-collector junction of a collector-up type HBT whose collector layer is made of GaAs, this layer can function as an etching stopper. This allows the GaAs layer corresponding to the collector layer to be selectively etched in the above-described base surface exposing step. [00201] Thereafter, wet etching is performed to remove surface damage, but since it is not necessary to completely remove the InGa+-As layer, overetching of the base layer can be limited to about 5 nm at most. In addition,
The contact resistance between the pIn Ga+-As layer and the Au-Zn-Ni layer is approximately the same as that between the p-GaAs layer and the Au-Zn-Ni layer. Therefore, it can be seen that the variation in base resistance is improved. [0021] The thickness of the InGa+-As layer is such that no misfit dislocations are caused by this layer at the base-collector junction, that is, the thickness of the GaAs
It is necessary to keep the film thickness below the critical film thickness. This critical film thickness varies depending on the In composition ratio y, but Matthews et al.
J. Matthews et al. (Journa on Crystal Growth)
lof Crystal Growth)), vol. 27,
1974, p. 118, for example, when y=Q, 3, it is about 9 nm. [00221 Next, the collector up type H of the first embodiment
The characteristics of BT will be explained. FIG. 9 is an energy band diagram when bias voltages Vbe and Vbc are applied to this first embodiment. However, for convenience, the emitter-base junction is a stepped junction. Emitter (n-GaAs layer 2
) into the base p-GaAs layer 3 becomes pIn
When entering the o3Gao4 As layer 4, it receives kinetic energy corresponding to EC2 (about 0.2 eV) due to the potential energy difference at the bottom of the conduction band. The electron diffusion coefficient is p-G
It is larger in p Ino3Gao7As layer 4 than in aAs5. Moreover, when new energy is added, an electron velocity overshoot effect occurs, so it is clear that electrons travel faster than those due to diffusion. Therefore, if the base layer thickness is the same (Fig. 8 The thickness of the base layer 3a in FIG.
If the total thickness of the Gao7As layer 4 is equal to the total thickness of the Gao7As layer 4), the time required for electrons to pass through the base layer is considered to be shorter than that of a conventional collector-up HBT. However, you must overcome the spikes at the base-collector junction. The tip of the spike is p-Ga
It is lower than the bottom of the conduction band of the As layer 3 by ΔE. ΔE is the energy difference from the bottom of the valence band to the Fermi level p-
Assuming that the GaAs layer 3 and the p-Ino3Gao7As layer 4 are equal, it can be regarded as approximately equal to ΔEv2. When the thickness of the pIno3Gao4 As layer 4 is smaller than the mean free path of electrons, there is no problem because the electrons cross the spike and reach the collector. Here ΔE
v2 is pGaAs and p -I no,s Gao7As
It is the potential difference in the valence band of , and has a value of about 0.1 eV. Therefore, it can be said that there is a possibility that the base running time is shortened and the cut-off frequency of the HBT is increased. [0023] The case where the conductivity type of the InGa+-As layer is p has been described above. [0024] A non-doped In Ga+-As layer can also be used as an etch stopper. In that case, it serves as a spacer layer at the base-collector junction. Since the p-GaAs layer 3 is heavily doped, it is considered that it will become a p-In Ga+-As layer when it is completed as a transistor, so it can be said that the electrical characteristics will be almost the same as those of the above-mentioned embodiments. [0025] Also, the n-In Ga+-As layer may be used as an etching stopper. In that case, since it plays a role as a part of the collector, it is sufficient to completely remove it where the base electrode is provided. This layer is thin, so
There is little change in the thickness of the base extraction region by removing this layer. The electrical properties other than the base resistance are considered to be almost the same as conventional collector-up type HBTs. [0026] Next, a case of an emitter-up type will be described as a second embodiment. [0027] The vertical relationship between the emitter layer and the collector layer of the collector-up type may be reversed, and the etching stopper may be placed under the emitter layer. [0028] On the semi-insulating substrate 1, an n-GaAs layer 5,
p-GaAs layer 3, p-Ino3Gao, y As
Layer 4, nAlo, s Gao7As layer 2 are sequentially deposited. The subsequent steps may be performed in the same manner as in the case of collector-up type HBT. [0029] When patterning the n-A1o3Gao7As layer 2 to form an emitter region, the underlying pIno3Gao7As layer 4 is used as an etching stopper. As previously explained, AI Ga+-As can be etched selectively over In Ga+-As. AI Ga+-
Since the lattice constant of As hardly depends on the AI component ratio, it can be considered that the critical film pressure is also almost the same. Therefore, even in an emitter-up type HBT, according to the present invention, variations in base resistance can be reduced. [00301 FIG. 10 is an energy band diagram when the present invention is applied to an emitter-up type HBT. The broken line shows the potential distribution when the p Ino3Gao7As layer 4 is not inserted. The height of the spike seen from the emitter is lowered by approximately ΔEv2 (approximately 0.1 eV),
The base-emitter on-voltage is reduced by that amount. Therefore, characteristics particularly advantageous in application to digital circuits and A/D conversion circuits can be obtained. [00311 The case of the p-In Ga+-As layer has been described above, but the non-doped In Ga+-As layer
The layer can also be used as an etch stop. In that case, it will act as a spacer layer at the emitter-base junction, and the electrical characteristics will be p-
This is almost the same as when an InGa+-As layer is used. [0032] Also, the n-In Ga+-As layer may be used as an etching stopper. In that case, since it plays a role as a part of the emitter, it is sufficient to completely remove the base electrode where it is provided, and there is little change in the thickness of the base lead-out region. The electrical characteristics other than the base resistance are considered to be almost the same as conventional emitter-up type HBTs. [0033] In G as an etching stopper
In addition to the a+-AS layer, a compound semiconductor layer containing In can be used. Especially AI In Ga+--A
The s-layer is preferable in terms of lattice constant and forbidden band width. [0034] Furthermore, the HBT is not limited to a stepped junction structure, and may be of an inclined junction type. Furthermore, the HBT is not limited to the npn type HBT, but may be a pnp type HBT. [0035]

As explained above, according to the present invention, a compound semiconductor layer containing In below the critical film pressure is inserted as an etching stopper between the emitter layer or collector layer and the base layer, so that the base surface can be exposed. Since the process can be performed over the entire wafer with good controllability, increases in base resistance due to under-etching or over-etching can be prevented, and as a result, compound semiconductor heterojunction bipolar transistors with excellent high-speed and high-frequency characteristics can be realized. There is an effect. Furthermore, there is an effect that the uniformity of device characteristics within a wafer can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view (FIG. 1(a)) and a cross-sectional view (FIG. 1(b)) used to explain a first embodiment of the present invention.

FIG. 2 is a plan view (FIG. 2(a)) and a cross-sectional view (FIG. 2(b)) used to explain the first embodiment of the present invention.

FIG. 3 is a plan view (FIG. 3(a)) and a cross-sectional view (FIG. 3(b)) used to explain the first embodiment of the present invention.

FIG. 4 is a plan view (FIG. 4(a)) and a cross-sectional view (FIG. 4(b)) used to explain the first embodiment of the present invention.

FIG. 5 is a plan view (FIG. 5(a)) and a cross-sectional view (FIG. 5(b)) used to explain the first embodiment of the present invention.

FIG. 6 is a plan view (FIG. 6(a)) and a cross-sectional view (FIG. 6(b)) used to explain the first embodiment of the present invention.

FIG. 7 is a plan view (FIG. 7(a)) and a cross-sectional view (FIG. 7(b)) used to explain the first embodiment of the present invention.

FIG. 8 is an energy band diagram of a conventional GaAs-AlGaAs HBT.

FIG. 9 Collector-up type HB according to the first embodiment of the present invention
FIG. 2 is an energy band diagram of T.

FIG. 10: Emitter-up type H according to the second embodiment of the present invention.
It is an energy band diagram of BT.

[Explanation of symbols] 1 Semi-insulating substrate 2 n-A1o2sGao7s AS layer 3p-GaAs
Layer 4 p-I no, 3 Gao4 As layer 5n-G
aAs layer 6 Rectangular region 7 Insulating region 8 Au-Ge-Ni layer 9 Silicon oxide film 10 Photoresist film 11 Insulating sidewall 12 Au-Zn-Ni layer 12a Base electrode 13 Photoresist film 14 Opening 15 Photoresist film 16 Emitter electrode 17 Silicon oxide Membrane 18B Contact hole 18C Contact hole 18E Contact hole

[Figure 1]

[Figure 2]

[Figure 8]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 9]

[Figure 10]

Claims (7)

[Claims] 1. One of an emitter layer and a collector layer made of a first conductivity type compound semiconductor not containing In formed on a semi-insulating substrate, and an emitter layer and a collector layer formed on one of the emitter layer and the collector layer. a base layer made of a second conductivity type compound semiconductor not containing In; a compound semiconductor layer containing In formed on the base layer;
A heterojunction bipolar transistor comprising an emitter layer and a collector layer, both of which are made of a first conductivity type compound semiconductor that does not contain In, formed on a compound semiconductor layer that contains n. 2. The heterojunction bipolar transistor according to claim 1, wherein one of the emitter layer and the collector layer is made of AI Ga+-As (0(X(1)), and the base layer is made of GaAs. 3. The compound semiconductor layer containing In
The heterojunction bipolar transistor according to claim 1 or 2, consisting of nGa+-As(0(Y(1)). 4. The heterojunction bipolar transistor according to claim 1, wherein the conductivity type of the In-containing semiconductor layer is the same as that of the base layer. 5. A first layer containing no In on a semi-insulating substrate.
a step of depositing one of a conductivity type emitter layer and a collector layer, a step of depositing a second conductivity type base layer not containing In on one of the emitter layer and collector layer, and a step of depositing an In-containing base layer on the base layer. a step of depositing a compound semiconductor layer containing a compound semiconductor layer; a step of depositing the other of an emitter layer and a collector layer of a first conductivity type on the compound semiconductor layer;
A method for manufacturing a heterojunction bipolar transistor comprising the step of patterning the other emitter layer into a predetermined shape by dry etching using a gas containing chlorine to locally expose the compound semiconductor layer. 6. The method for manufacturing a heterojunction bipolar transistor according to claim 5, wherein the chlorine-containing gas is C12 gas. 7. An AI Ga+-As layer as one of the emitter layer and the collector layer, (0<X<1),
A GaAs layer is deposited as the base layer, and a GaAs layer is deposited as the base layer.
6. The method of manufacturing a heterojunction bipolar transistor according to claim 5, wherein said collector layer is patterned by dry etching using I2 gas.