JPH0421059A - Switching system for inter-processor coupling device - Google Patents

Abstract

PURPOSE:To continue the communication without being aware of a communication address change caused by switching by restoring PCI management information from drawback information at the time of integrating a PCI, and changing a fault PCI address of communication address information in the other PCI to a communication address of a stand-by PCI. CONSTITUTION:Plural processors 2 - 4 are connected to a closed communication channel 1 of a ring shape or a bus shape through inter-processor coupling devices (PCI) 5 - 8, respectively, and in each PCI 5 - 8, mapping tables 9 - 12 in which a communication address and an entry number of the PCI 5 - 8 which become the other parties of communication are set, and a secondary medium for drawing back its information are provided. In such a state, when a communication by the existing PCI 5 is interrupted, mapping information 16 which is drawn back is reset to the mapping table 10 of the stand-by PCI 6, and a communication address is changed from the fault PCI 5 to the stand-by PCI 6, and informed to the other processors 3, 4 of communication. In such a way, even after the PCIs 5, 6 are switched, the communication can still be continued as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing method for switching an inter-processor coupling device in a multi-purpose computer system from active to standby.

[Conventional technology]

Conventionally, compound computer systems have been used in which a plurality of processors are connected using communication paths such as optical loops.

In such a system, an inter-processor coupling device (hereinafter referred to as PC) is used as a device for coupling processors to each other.
Written as r, Process.

rCommunication I nterf
ace Unit) is connected, and when setting up a communication link, the managing processor specifies the PCI address and subchannel used for communication to the communication requesting processor, allowing communication between the processors. .

Conventionally, in such a system, as a countermeasure against failure of the PCI that connects the processor to the communication path, the processor is connected to the communication path via multiple PCIs in advance, so that even if one PCI fails, the other PCI will fail. There was a method to continue communication by switching the connection to the PCI of the PCI.

There are two methods for installing multiple PCIs: (i) a hot standby method, in which communication paths are prepared in advance for multiple PCIs, and if one PCI fails, the remaining path on the PCI is used to continue communication; ) In the event of a PCI failure, a spare PCI is installed and the communication path is reset.

In the former case, a path is always set in the backup PCI, so it is necessary to prepare the backup PCI exclusively for the processor. Furthermore, a program on the processor is required to manage multiple paths and have a bus switching function triggered by a PCI failure. On the other hand, the latter allows backup P
Although a hardware function is required to transfer the processor to the CI, the path information of the failed PCI is restored to the spare PCI, so the program on the processor can continue to use the conventional path. Therefore, there is no need to manage multiple paths in consideration of PCI failures. Further, by adding a switching function of N + 1 (N is the number of shared processors) between the PCI and a plurality of processors, it is also possible to share the spare PCI with a plurality of processors.

In addition, as this type of conventional literature, rloOMb/
s Inter-processor coupling system using optical token ring,” Journal of the Information Processing Society of Japan, Vol. 27°Na3 (198
6), co-authored by Satoko, Koyanagi, and Uozumi.

[Problems to be Solved by the Invention] As described above, when switching the currently used PCI to another PCI due to a PCI failure, it is necessary to notify the communication partner of the communication address of the newly used PCI. Therefore, in the conventional method (hot backup method), multiple PCs are
A method has been used in which a communication path is set on PCI, and when one PCI becomes unavailable, communication is continued using the path on the other PCI. As a result, in the program, it is necessary to manage a plurality of working and backup paths, and at the same time, it is also necessary to set a path for the backup PCI.

In addition, in inter-processor communication via a closed communication path using a ring or path format such as an optical loop, a unique communication address is assigned to the PCI that connects the processor to the communication path. , P.C.I.
A new function is required to change the communication address. It is necessary to make the program on the communication partner processor aware of changing the communication address. Therefore, the PCI communication address change process becomes even more complicated.

The purpose of the present invention is to solve such conventional problems and to
Provides an inter-processor coupling device switching method that does not make the program aware of the change in communication address due to I switching, allows communication to continue with the same address as before after switching, and eliminates the need for a communication path on the backup PCI. It's about doing.

[Means to solve problems]

In order to achieve the above object, the inter-processor coupling device switching method of the present invention provides a one-to-one connection between a spare PCI prepared in case of failure of the working PCI and a communication path provided in each PCI and managed by a program. The corresponding communication address information is used as an entry, and the PC that becomes the communication partner is used as the entry information.
It has a mapping table in which I's communication address and entry number are set, and a secondary medium for saving the information in the mapping table.When communication by the current PCI is interrupted, the information can be saved to the secondary medium. Reset the mapping information that has been stored in the mapping table of the backup PCI, obtain the communication address and entry number of the communication partner PCI from the saved mapping information, and set the communication address in the mapping information via the communication path to the mapping table of the failed PCI. The feature is that the communication address is changed to the communication address of the backup PCI, and the change in the mapping table is notified to the program on the communication partner processor.

[For production]

In the present invention, even when a closed communication channel such as a loop is used, it is possible to continue communication without making the program on the processor aware of the communication address change due to cold standby switching of PCI. In a closed communication path such as a loop, it is necessary to add a transmission address corresponding to the communication path to the transmission message and send it to the communication path, so the sender holds the communication address information of the other party. The present invention provides a function for managing communication address information within PCI and at the same time saving communication address information, a function for restoring PCI management information from the saved information when installing PCI, and
I When the communication address is changed, check the other party's address from the saved communication partner address information and directly check the faulty PC of the communication address information in the other party's PCI via the communication path.
By using the function to change the I address to the communication address of the backup PCI, the program on the processor can
, 1 switching makes it possible to continue communication without being conscious of changing the communication address.

[Example〕 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a compound computer system showing a first embodiment of the present invention.

In FIG. 1, 1 is a ring-shaped high-speed loop communication channel;
2, 3.4 is a group of processors connected to a loop, 5, 6
, 7.8 is a processor-to-processor coupling device (PCI) that couples each processor into a loop and enables communication with other processors.
), 9, 10, 11° 12 is a communication address mapping table (hereinafter referred to as CTBL) managed by PCI,
13 is a path management table (hereinafter referred to as PT) for managing communication path numbers and corresponding CTBL entry numbers;
4 changes the communication path number to the CTBL entry number,
A communication control program that sends and receives communication data to and from the PCI;
15 is a PCI that saves and restores CTBL information in the PCI
A management program, 16 indicates saved CTBL information in the secondary medium, and 17 indicates a group of programs to be communicated.

The parts newly provided in the present invention are the hatched parts in FIG. Next storage medium 16 and path management table (PT)
13 and the PCI management program.

Figures 2 and 3 are diagrams showing the contents of the PT (path management table) of each processor in Figure 1, and the PCI
FIG. 2 is a diagram showing the contents of CTBL (communication address mapping table) of FIG.

As shown in Figure 2, the PT includes a path number for each processor, and a PC to be used for each path number for transmission/reception distinction.
The I number, CTBL entry number, and communication target processor are shown.

In addition, as shown in Fig. 3, the CTBL includes, for each PCI, the CTBL entry number of its own PCI, the CTBL entry information, the distinction, the PCI communication address, and the CTBL entry information.
Each L entry number is shown.

In this case, one path is defined between each processor, and the communication addresses of PCl5-8 are set as 05-08.

PCl5, 7.8 is the current PC with each processor.
Used as I. PCI6 is a cold spare PCI of processor 2, and the value of CTBL is invalid.

FIG. 4 is a frame configuration diagram showing the format of communication data transmitted via the loop communication path.

As shown in Figure 4, the communication data frame includes a delimiter, a destination PCI communication address (DA) (8 bytes), a source PCI communication address (SA) (8 bytes), and a loop command (LC) ( 8 bytes), communication information (
I) (8n bytes), frame check sequence (P
C5) (16 bits) and a delimiter (D).

The communication information (1) includes the communication target entry number (N) of the CTBL of the destination PCI and the subcommand (S C
) and data (DATA). FIGS. 5 and 6 are processing flowcharts of the communication target program on each processor.

First, in the transmission process (a), the processes are performed in the following order. Here, a case is shown in which data is transmitted from processor 2 to processor 3.

The communication target program 17 on each processor requests the communication control program 14 to specify bus number 1 and send data to the processor 3 (step 101). Correspondence system - Program 14 selects PCI corresponding to bus number 1 - from PT.
(PCI 5) and CTBL entry number (value = 1) are acquired (step 102), and entry number 1 is specified to request P(j5 to send data (step 103))
. The PCI5 acquires the communication address (value=07) and entry number (value=2) of the destination PCI7 from the specified entry (value=1) in the CTBL (step 104), generates a transmission frame, and loops. Send data to (
Step 105).

The destination PCI7 uses its own PCI communication address (value = 0
When the frame 7) is received (step 111), the CT specified by the entry number (value = 2) in the frame is received.
From the information in the BL entry, the communication address of the source PCI (
value = 5), and calculate the source address (SA value = 5) in the frame.
) (Step 1 and Step 2). If they match, it is recognized that the correct data has been received, and the received data is transferred to the communication control program 14 (step 1).
13).

In step 114), the communication control program 14 acquires the bus number (value=1) corresponding to the PT reception entry number (value=2), contrary to the transmission, and the communication target program 17 waits for reception data from that path. The data is passed to (step 115). In other words, both the communication target program 17 and the communication control program 14 on the processor specify the logical bus number and CTBL entry number without being directly aware of the PCI communication address, and communicate between the processors, and perform PCI communication. Conversion to address is PCI
It is shared in

Next, referring to FIG. 6, the PCI switching process when a PCI fails will be explained.

Now, assume that PCl5 has failed.

Since the processor 2 has a spare PCI 6 in addition to the current PCI 5, it is possible to secure a physically normal communication path by using the PCI 6. At this time, the PCI communication address of processor 2 is changed from 05 to 06, so processor 3 that communicates with processor 2
, 4 also needs to change the communication address of PCl5 set in the CTBL of PCI to P(j6.

In the present invention, it is possible to switch to the backup PCI without preparing a path in advance for the backup PCI and without changing the bus number, which is the logical communication ID of the program on the processor. Conventionally, there was no way to change the communication address from the processor 2 to the processor 3/4 side, so a bus was also defined in advance for the backup P (j6), and a hot A backup method was used, but in the present invention, it is not necessary.
In order to take over the CTBL information of the CI to the backup PCI, the PCI management program is provided with a function of saving the CTBL information set in advance in the PCI to a secondary medium and at the same time modifying the saved information in accordance with changes in the CTBL information.

When the communication control program 14 detects a permanent failure in the current PCI 5, it sets this as a failure state (step 201). Next, a request is made to the PCI management program 15 to install the spare PCI 6 (step 202).

The PCI management program 15 reads the CTBL information of the PCI6 saved in the secondary medium, and updates the CTBL information of the PCI6.
The data is restored to L (step 203). Since the communication address of the faulty PCI5 is also set in the CTBL of another processor that has set up a communication bus with the processor 2, it is necessary to change it to the communication address of the new PCI6. For this reason, in this embodiment, a specified entry in the CTBL is created so that the CTBL of the PCI of the communication target processor can be directly rewritten via a loop from the processor that has switched the PCI, which can determine the necessity of address change and the contents of the change. The entry data setting function of PCI subcommand (SPC
(command).

The PCI management program 15 of the processor 2 is
Read the CTBL information of 15 sequentially from entry 1 (step 205), specify the entry number (N), and
6, the PCI 6 is instructed to change the entry (EN) information of the communication partner PCI corresponding to the entry (N) (step 206).

Change information can be determined as follows. Sending entry (ES) and receiving entry (ER) are E
Since there is a bear relationship of R = ES + 1, the transmission/reception division of EN is l (reception) when N is an odd number, and 0 (transmission) when it is an even number.
decided on.

The PCI communication address of EN is determined to be 06, which is the address of PCI6. The CTBL entry number for EN is N.
be equivalent to. PCI6 uses the SPC for CTBL rewriting based on the EN and N values given from the P(l management program).
A command transmission frame is generated (step 207).

The destination address in the frame is <DA), which is the local number N.
It is determined from the AN of the TBL entry. The PC,I management program 15 checks the destination PCI's C for all entries.
After modifying the TBL, the communication control program 14 is notified of the completion of the installation of the PCI 6 (step 210). Taking this notification as an opportunity, the communication control program 14 changes PCl5 in the managed PT to P(16) and restarts the communication service for the communication control target program 17 (step 211).

On the processor side, where the CTBL has been changed by the SPC command, the CTBL from the PCI is changed as shown in Figure 6 (C).
In response to the BL change notification, the PCI management program saves CTBL information to a secondary medium. In other words, own P
When the frame is received by the CI (step 301), and the subcommand is SPC (step 302), the value of the entry EN in the mapping table is changed to the received data (step 303). Next, PCI management program 1
Notify the mapping table change to 5 (Step 3)
04). Then, the mapping table is read and saved in the secondary medium (step 305).

FIG. 7 is a block diagram of a compound computer system showing a second embodiment of the present invention.

In FIG. 7, 21 is a high-speed communication path forming a ring shape, 22 to 26 are a group of processors coupled to the loop 21, 27 to 31 are PCIs of each processor, and 34 to 38 are P
This is CTBL in CI.

Processor 22 and processor 23 constitute a duplex system. Here, it is assumed that the processor 22 is the active system and the processor 23 is the backup system. 32 is an active system file, which is initially connected to the active processor 22; 33 is a standby system file, which is initially connected to the processor 23; PCl27 and PCl2
8 are used as PCIs of processors 22 and 23, respectively.

In the present embodiment, the current processor 22 has a processor failure.
When the current system file 32 is connected to the PCl 28 of the processor 23 and the current system is restarted on the processor 23, the service can be continued. In this case as well, since the PCI used is changed, processing for changing the PCI address is required. In this embodiment, the change of the PCI address is done without making the program on the processor aware of it.
Can be implemented. In other words, when restarting the standby system, P
Saved CTBL information 39 of Cl27 to CTB of PCl28
By restoring to L35 and changing the PCI communication address of CTBL information 36 to 38 of other PCIs 29 to 31 from PCI 27 to PCI 28 in the same manner as shown in FIG. You can continue to use the bus number and CTBL entry number that you had at the time.

FIG. 8 is a block diagram of a compound computer system showing a third embodiment of the present invention.

In FIG. 8, l is a high-speed communication path forming a ring shape, 51 to 55 are a group of processors connected in a loop, and 56
~61 is the PCI of each processor, of which PC
158 is used as a common reserve for PCl56 and PCl57. That is, the spare Plj is shared by a plurality of processors (51 and 52). For that purpose, PCl56-58
and the processor 51, 52, a changeover switch 70
(hereinafter referred to as PSU, PCI Switch
g 0nit). In Figure 8, P(
A specific processor 55 (hereinafter referred to as SCP, SWit
changing P CI Processor),
Added PCI switching control. 80 is 5CP5
5 to a control interface (hereinafter referred to as CI, C.

PCI failure notification of SCP 55A and P from 5CP55.
Used to instruct switching to SU70.

Now, assume that the current PCI 56 of the processor 51 becomes unusable. The processor 51 is unable to use inter-processor communication using the loop due to the failure of the PCI 56, and is managing the spare PCI through the CI route.
Notify the CP55 of the failure of the PCl56. 5CP55
In order to allocate the spare PCl 58 to the processor 51,
After switching the PSU 70 through the CI route, the processor 51 is notified (■) that the PSU 58 can be used through the CI route. Thereafter, the PCI CTBL information is restored and modified based on the Pct address change process of the present invention. In other words, the CTBL save information 6 on the secondary medium
3, restore the CTBL of PCl58, and
CTB of other PCl57.59-61 by PC command
Change the PCI communication address of the L information to PCl58.

As described above, in the second embodiment, when a processor failure occurs in a system with a duplex configuration and the PCI used is changed by switching the processor, the program can be implemented without making the program conscious of changing the PCI communication address due to the PCI switching. In addition, in the third embodiment, there is no need to prepare a communication bus in advance for the spare PCI, and by arranging a changeover switch between the plurality of processors and the spare PCI, the spare PCI can be shared among the plurality of processors. It is possible.

〔Effect of the invention〕

As explained above, according to the present invention, even when a processor-to-processor coupling device (PCI) fails and is switched to a spare PCI, the program on the processor can be made aware of the change in the PCI communication address due to PCI switching. Instead, it is possible to continue communication as is using the logical path number and CTBL entry number managed by the program that was being used before switching.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a compound computer system showing the first embodiment of the present invention, FIG. 2 is a diagram showing the contents of the bus management table (PT) in FIG. 1, and FIG. 3 is a diagram showing the PCI in FIG. FIG. 4 is a diagram showing the format of the communication data frame flowing on the communication path in FIG. 1. FIG. Figure 6 is a flowchart of the PCI switching process in Figure 1;
FIG. 7 is a block diagram of a compound computer system showing a second embodiment of the invention, and FIG. 8 is a block diagram of a compound computer system showing a third embodiment of the invention.

Claims (1)

[Claims] (1) A processor in which a plurality of processors are each connected to a ring-shaped or bus-shaped closed communication path via an interprocessor coupling device (hereinafter referred to as PCI), and data is transmitted and received between each other via the communication path. In the inter-communication method, entry information is communication address information that corresponds one-to-one to a spare PCI prepared in case of failure of the current PCI and a communication bus provided in each PCI and managed by a program, and communication is performed as entry information. It has a mapping table in which the communication address and entry number of the other PCI are set, and a secondary medium for saving the information in the mapping table, and when communication by the current PCI is interrupted, the secondary medium The mapping information saved in the medium is reset to the mapping table of the spare PCI, the communication address and entry number of the communication partner PCI are obtained from the saved mapping information, and the communication address in the mapping information is set via the communication path. An inter-processor coupling device switching method characterized in that the communication address of a failed PCI is changed to the communication address of a spare PCI, and a program on a communication partner processor is notified of the change in the mapping table.