JPH0421047A - Address converter - Google Patents

Abstract

PURPOSE:To improve the transplantability at the time of transplanting an operating system for operating on a processor whose address width is small to a processor whose address width is large by providing a base address, and setting the contents of an address conversion table as a relative address. CONSTITUTION:The entry contents of a conversion table corresponding to at least a logical address subordinate part are set as a relative address, and a middle stage table relative address storage means 102 and a base address storage means 103 are provided. Accordingly, an address conversion table structure in a processor of small address width, and an address conversion table structure of a middle stage table and thereafter shown by the middle stage table relative address storage means 102 in a processor of large address width, that is, an address conversion table structure of the part corresponding to an address space of the processor of small address width become the same. In such a way, transplantability at the time of transplanting an operating system for operating on the processor of small address width to the processor of large address width is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address translation device for a computer system.

[Conventional technology]

A user of a computer system having a virtual memory function can treat the computer as if it had more memory than the main memory installed in the system. In such a system, memory is dynamically allocated according to the needs of a user program, and a logical address, which is an address handled by the user program, is allocated to the memory.

Therefore, the computer system needs to convert the logical address into a physical address of the installed main memory.

An address translation device is a device that translates such a logical address into a physical address. That is, the input of the address translation device is a logical address, and the output is a physical address.

Here, a conventional address translation device will be explained using an address translation device for a 32-bit processor as an example. In a conventional address translation device, a logical address is divided as shown in FIG. In FIG. 8, 311 is a section index, 312 is a page index, and 313 is an offset. These section indexes 311. The page index 312 is used as an index to refer to each table in the process of address translation. The offset 313 is used as an offset for determining the physical address in the final process of address translation. Section index 311 is 1
0 bit, page index 312 and offset 31
3 is 11 bits.

Next, the concept of address translation is shown in FIG. In FIG. 6, reference numeral 601 denotes a first-stage table absolute address register 114 that stores the absolute address of the first-stage conversion table.
is the section table, 115 is the page table, 10
4 is the main memory.

In a computer system having a virtual memory function, main memory is divided into fixed-length blocks called pages, and a plurality of pages collectively constitute a section.

Each entry of the page table 115 stores the start address of a page, and each entry of the section table 114 stores the start address of the page table 115. First stage table absolute address register 601. The contents of each section table 114 entry and page table 115 entry are absolute addresses, and the size of each entry is all 32 bits.

Address translation is performed according to the procedure shown in FIG.

First, the first stage table absolute address register 601 and the section index 311 are added to obtain the address of the section table 114 entry corresponding to the input logical address (step 7o1). Next, the address of the page table 115 entry is obtained by adding the obtained contents of the section table 114 entry and the page index 312 (step 702). lastly,
The content of the obtained page table 115 entry and the offset 313 are added to obtain the target physical address (step 703).

In this way, the conventional address translation device divides a logical address into a plurality of fields and includes an address translation table with a number of stages corresponding to the number of fields. Then, a multi-stage address translation table is searched using each field of the logical address as an index of the translation table, and the logical address is translated into a physical address.

Regarding the conventional address translation device, for example, “H
32/2QQ Operational Architecture Manual, Chapter 4.

[Problem to be solved by the invention]

In conventional address translation devices, the structure of address translation tables between processors with different address widths differs greatly, which poses a problem in that the portability of the operating system is reduced.

For example, when comparing the address translation table structures of a 32-bit processor equipped with a conventional address translation device and a 64-bit processor, the following two points differ.

First, since the contents of each translation table entry are absolute addresses, the bit widths of the translation table entries are different.

Second, the number of stages of the conversion table also differs. This means that when the address width becomes wider as in a 64-bit processor, the size of the physical page and translation table is increased by 3, rather than increasing the size of the physical page or translation table by setting the number of stages of the translation table to be the same as that of a 32-bit processor.
If the size is the same as that of a 2-bit processor and the number of stages of the conversion table is increased, the main memory can be used more effectively, so the 64-bit processor has a larger number of stages of the conversion table.

In this way, when the address width differs, the bit width of the translation table entry and the number of stages of the translation table differ. These differences in address translation table structures reduce the portability of operating systems.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address translation device that is equipped with a conventional address translation device and improves portability when an operating system running on a processor with a small address width is ported to a processor with a large address width. .

[Means to solve the problem]

In order to achieve the above object, the address translation device of the present invention provides a base address and makes the contents of the address translation table a relative address.

More specifically, the logical address is greatly increased in the upper part.

The address translation table is divided into two lower parts, and the content of each entry in the address translation table corresponding to at least the lower part of the logical address is a relative address from the base address, and the content of each entry in the remaining address translation table is an absolute address. and base address storage means for storing the base address, and a relative address from the base address of the topmost table in the table corresponding to the logical address lower part of the logical address whose upper logical address part is O. intermediate table relative address storage means;
and first stage table absolute address storage means for storing the absolute address of the first stage table. Further, when the upper part of the logical address is 0, the table search is started from the intermediate table indicated by the intermediate table relative address storage means, and the address conversion means converts the logical address into a physical address, and the upper part of the logical address is 0. If it is not 0, the first address indicated by the first stage table absolute address storage means is
An address conversion means is provided which starts table search from the stage table and converts a logical address into a physical address.

Further, instead of the first stage table absolute address storage means, first stage table relative address storage means is provided for storing a relative address from the base address of the first stage table.

[Effect]

In the present invention, the entry contents of the translation table corresponding to at least the lower part of the logical address are relative addresses, and by providing intermediate table relative address storage means and base address storage means, small address translation devices equipped with a conventional address translation device can be used. Address conversion table structure in a wide address width processor and address conversion table structure after the middle table indicated by the middle table relative address storage means in a large address width processor equipped with the address translation device of the present invention, that is, the small address Since the address translation table structure of the part corresponding to the address space of a wide-width processor is the same, it is easy to port an operating system running on a small address-width processor equipped with a conventional address translation device to a large-address-width processor. improves portability.

〔Example〕

(Example 1) An embodiment of the present invention will be described below with reference to the drawings.

Here, the present invention is applied to an address translation device for a 64-bit processor.

In this embodiment, a 64-bit logical address is roughly divided into two parts, an upper part and a lower part, as shown in FIG. 3, and each of the upper part and lower part is further divided into three parts. In FIG. 3, 30 is an upper part of a logical address, 31 is a lower part of a logical address, 301, 302, 303, and 311 are section indexes, 312 is a page index, and 313 is an offset. Logical address upper part 30. Lower part 3
Each 1 is 32 bits.

The logical address lower part 31 corresponds to the logical address of the 32-bit processor shown in FIG. Section indexes 301, 302, 303° 311 and page index 312 are conversion table indexes,
Offset 313 is an offset within the physical page.

Section inches 301 and 311 are 10 bits, and section indexes 302 and 303, page index 312 and offset 313 are 11 bits. Therefore, one page is 4 bytes.

FIG. 1 shows the concept of address translation according to this embodiment.

In FIG. 1, 101 is a first-stage table absolute address converter that stores the absolute address of the first-stage translation table, and 102 is a relative address of the section table 114 corresponding to a logical address whose logical address upper part 30 is 0. Intermediate table relative address register for storing 1
03 is the section table 114. Page table 11
5 and a base address register for storing the base address of the physical address; 111 is a first stage section table corresponding to the section index 301; 112;
is the second stage section table corresponding to section index 302, and 113 is section index 3.
03 is a section table in the third stage, 114 is a section table in the fourth stage corresponding to the section index 311, and 115 is a page table which is a conversion table in the fifth stage corresponding to the page index 312. The first stage table absolute address register 101 and the base address register 103 are 64 bits, and the intermediate stage table relative address register 102 is 32 bits. Each entry in section tables 111, 112, 113 is 64 bits, and section table 114. Each entry in page table 115 is 32 bits.

In this way, the address translation device of this embodiment has the section table 114 .corresponding to the logical address lower part 31 .
The content of each entry in the page table 115 is a relative address from the base address, and the logical address upper part 30
The content of each entry in the section table 111, 112, 113 corresponding to the above is set as an absolute address, and the base address register 103 that stores the base address and the section table 114 corresponding to the logical address whose logical address upper part 30 is 0 are stored. Intermediate table relative address 1 for storing relative addresses from the base address
02 and a first stage table absolute address register 101 that stores the absolute address of the section table 111.

The process of address translation in this embodiment will be explained according to the procedure shown in FIG. First of all, the logical address upper part 30
is O (step 201). If the logical address upper part 30 is O, the base address register 103. Intermediate table relative address register 10
2 and the value of section index 311 are added,
The address of the section table 114 entry corresponding to the logical address is determined (step 2o2). and,
Base address register 1o3. Page index 3
12 and the content of the section table 114 entry just found to find the address of the page table 115 entry corresponding to the logical address (step 207
). Finally, base address 103. offset 313
and the content of the page table 115 entry just obtained to obtain the physical address corresponding to the logical address (step 208).

On the other hand, if the logical address upper part 30 is not 0, the first stage table absolute address register 101 and the section index 301 are added to find the address of the section table 112 entry corresponding to the logical address (step 2o3). Next, the content of the conversion table 111 entry just found and the section index 302 are added to find the address of the section table 112 entry corresponding to the logical address (step 2o4). Furthermore, the contents of the section table 112 entry just found and the section index 303 are added to find the address of the section table 113 entry corresponding to the logical address (step 2o5).

Then, the contents of the section table 113 entry just found and the section index 311 are added to find the address of the section table 114 entry corresponding to the logical address (step 206). After this, as in the case where the logical address upper part 30 is O,
Base address register 103. Page index 3
12 and the content of the section table 114 entry just found to find the address of the page table 115 entry corresponding to the logical address (step 207
). Finally, base address 103° offset 313
and the content of the page table 115 entry just obtained to obtain the logical address corresponding to the logical address (step 208).

As described above, the structure of the address translation table of a 32-bit processor equipped with a conventional address translation device and the intermediate table relative address register 102 of this embodiment are as follows. Section table 114 and page table 115 have the same structure.

(Embodiment 2) Next, another embodiment of an address translation device including means for storing a relative address from the base address of the first stage table in place of the first stage table absolute address register 1010 will be described.

FIG. 4 shows the concept of address translation according to this embodiment.

In FIG. 4, 401 is a first-stage table relative address register that stores the relative address from the base address of the first-stage translation table, 103 is a base address register that stores the base address of all translation tables and physical addresses, and 411 is a base address register that stores the base address of the entire translation table and physical addresses. A first stage section table 412 corresponds to the section index 301, a second stage section table 412 corresponds to the section index 302, and a third stage section table 413 corresponds to the section index 303. The base address register 103 has 64 bits, and the first stage table relative address register 401 and the intermediate stage table relative address register 102 have 32 bits. Each entry in section tables 411, 412, 413, 414 and page table 115 is 32 bits.

Comparing this embodiment with the embodiment shown in FIG. 1, with respect to the translation table entry corresponding to the upper part 30 of the logical address and the address register pointing to the first stage section table, in the embodiment 1 shown in FIG. However, in the second embodiment shown in FIG. 4, it is a relative address from the base address. In this way, the address translation device of this embodiment uses the content of each entry in the entire translation table as a relative address from the base address, and instead of the first stage table absolute address register 101 in FIG. A relative address register 401 is provided.

The process of address translation in this embodiment will be explained according to the procedure shown in FIG. In addition, in FIG. 5, steps 203 and 204 in the address conversion procedure of the first embodiment shown in FIG.
, 205, 206 in steps 503, 504, 5
05, 5061. My knees are weird. In other words, the address translation procedure when the logical address upper part 30 is O is the same as the address translation procedure of the first embodiment in FIG. 2, but when the logical address upper part 30 is not 0, the section table 114 entry The procedure up to the stage of obtaining an address is different from the address conversion procedure of the first embodiment shown in FIG.

First, it is determined whether the logical address upper part 30 is O (step 201). Logical address upper part 3
If 0 is O, the base address register 103. The values of the intermediate table relative address register 102 and the section index 311 are added to find the address of the section table 114 entry corresponding to the logical address (step 202).
.

And base address register 1o3. Page index 312 and section table 114 just obtained
The contents of the entries are added to find the address of the page table 115 entry corresponding to the logical address (step 207). Finally, base address register 103.
Offset 313 and the page table 115 just found
The contents of the entries are added to find the physical address corresponding to the logical address (step 208).

On the other hand, if the logical address upper part 30 is not O, in this embodiment, the base address register 103, the first stage table relative address register 401, and the section index 301 are added, and the address of the section table 411 entry corresponding to the logical address is determined. (step 503).

Next, base address register 103. Section index 302 and section table 4-
The contents of the 11 entries are added to find the address of the section table 412 entry corresponding to the logical address (step 5o4). Furthermore, base address register 103. The section index 303 and the content of the section table 412 entry just found are added to find the address of the section table 4-3 entry corresponding to the logical address (step 505). And base address register 103. The section index 311 and the content of the section table 413 entry just found are added to find the address of the section table 114 entry corresponding to the logical address (step 506). After this, the above-mentioned logical address upper part 30
As in the case where is O, the base address register 10
3. Add the contents of the page index 312 and the section table 114 entry just found to find the address of the page table 115 entry corresponding to the logical address (step 20?).Finally, the base address register 103. Add the offset 313 and the content of the page table 115 entry just found to find the logical address corresponding to the logical address (step 208).
.

As described above, the structure of the address translation table of a 32-bit processor equipped with a conventional address translation device and the intermediate table relative address register 102 of this embodiment are as follows. Section table 114 and page table 115 have the same structure.

〔Effect of the invention〕

According to the present invention, an address translation table structure in a small address width processor equipped with a conventional address translation device and an intermediate table relative address storage means in a large address width processor equipped with the address translation device of the present invention are shown. Address translation table structure after the intermediate table.

That is, the address translation table structure of the portion corresponding to the address space of the processor with the small address width becomes the same.

Therefore, the present invention improves the portability of an operating system running on a small address width processor with a conventional address translation device to a large address width processor.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the concept of address translation in one embodiment of the present invention, FIG. 2 is a flowchart showing the address translation procedure in one embodiment of the present invention, and FIG. 3 is a logic diagram in one embodiment of the present invention. FIG. 4 is an explanatory diagram showing the concept of address conversion in another embodiment of the present invention. FIG. 5 is a flowchart showing an address translation procedure in another embodiment of the present invention, FIG. 6 is an explanatory diagram showing the concept of address change in a conventional address translation device, and FIG. 7 is an address translation in a conventional address translation device. FIG. 8 is a flowchart showing the procedure, and is a diagram showing a logical address division method in a conventional address translation device. 101.601...First stage table absolute address register, 1o2...Intermediate stage table relative address register, 103...Base address register, 104...
・Main memory, 111 to 114, 411 to 413...Section table, 115...Page table, 20
1-208, 503-506... Address conversion procedure in the embodiment of the present invention, 30... Upper part of logical address, 31... Lower part of logical address, 301-303.3
11... Section index, 312... Page index, 313... Offset, 401...
・First stage table relative address register, 701 to 70
3...Address translation procedure in a conventional address translation device. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. In an address translation device that converts an input logical address into a physical address by multi-stage table search, the logical address is roughly divided into two parts, an upper part and a lower part, and at least the logical address The table corresponding to the lower part has its entry contents as a relative address from the base address, and the remaining tables have their entry contents as absolute addresses, and have a base address storage means for storing the base address, and a logical address whose upper part is 0. intermediate table relative address storage means for storing a relative address from the base address of the top table in the table corresponding to the lower logical address part of a certain logical address; and a middle table relative address storage means for storing the absolute address of the first table. a one-stage table absolute address storage means; and an address conversion means for starting a table search from the table indicated by the middle-stage table relative address storage means and converting the logical address into a physical address when the upper part of the logical address is 0; An address translation device comprising address conversion means for starting a table search from the table indicated by the first-stage table absolute address storage means when the upper part of the logical address is not 0, and converting the logical address into a physical address. 2. The address translation device according to claim 1, further comprising first stage table relative address storage means for storing a relative address from said base address of said first stage table in place of said first stage table absolute address storage means.