JPH04207543A - Quality class control system in channel of atm exchange - Google Patents

Abstract

PURPOSE:To prevent the characteristic of a cell class from being affected by the effect of a cell of a class with lower priority than that of the inputted cell by adding a class of abort and delay to a cell and providing an abort control section and a delay control section for the system. CONSTITUTION:A quality class CL(m, n) in response to an abort characteristic and a delay characteristic is added to a cell, and one buffer memory is divided into an area corresponding to the quality class CL(m, n) depending on the arrival quantity. When an inputted cell is written in an area of the quality class CL(m, n) corresponding the buffer memory, an abort control section 4 controls to abort a cell whose abort quality class is in excess of a independently preset threshold level corresponding to the total amount to be used of the buffer memory. A delay control section 5 applies priority control of the read sequence corresponding to the delay quality class at the read from the buffer memory. Thus, the abort characteristic and the delay characteristic are independently controlled and the characteristic is not affected by the cell with lower priority than that of its own cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a quality class control method in a communication path of an ATM switch in which a switching element connecting a plurality of input/output highways is provided with a buffer memory.

A, in which the discard characteristics and delay characteristics can be controlled independently, and the characteristics are not influenced by cells with lower priority than the own cell;
The purpose is to provide a quality class control method for communication paths of TM exchanges.

A quality class corresponding to a discard characteristic and a delay characteristic is added to the cell, and the two buffer memories are divided into areas corresponding to the quality class according to the amount of arrival.

The discard control unit, when writing five cells into the area of the corresponding quality class of the buffer memory, exceeds a threshold value independently preset for each F4 millet quality class, corresponding to the total usage of the buffer memory. The delay control unit is configured to perform control to discard cells that have been stored in the buffer memory, and to perform priority control on the read order in accordance with the delay quality class when reading from the buffer memory.

[Industrial Field of Application] This invention relates to a quality class control system in the communication path of an ATM switch in which switching elements connecting a plurality of input/output highways are provided with buffer memories.

ATM switches centrally handle communications that are sensitive to delays, such as voice, and communications that are difficult to discard, such as data. On the other hand, an ATM switch is known in which a switching element equipped with a buffer memory is provided at each intersection of a plurality of input/output highways, and a communication path is formed by driving the switching element.

In the communication path of such an ATM switch, if the capacity of the buffer memory is increased, the number of discarded cells can be reduced, but the delay will be increased. Conversely, if the capacity of the buffer memory is reduced, the delay will be reduced, but there is a trade-off relationship in that more cells will be discarded, making it difficult to centrally process all communications9. It is desired to control cell discard and delay according to the situation.

[Conventional technology] FIG. 6 is an explanatory diagram of a conventional example.

A in FIG. 6 is the configuration of an ATM switch.

A buffer memory 60 is provided at each intersection of a plurality of input highways (HW) #1 to #P and a plurality of output highways (HW) #1 to #Q. Destination information (VPI/VCI, etc.) included in the header (consisting of a 48-byte data section)
The cells are stored in a buffer memory 60 that identifies and connects to the corresponding output HW. The buffer memory 60 is provided to prevent collisions when cells destined for the same output HW are input from multiple input HWs at the same time, and the cells stored in the buffer memory are sequentially read out by the selector 61 corresponding to the output HW. and output to the output HW.

In the conventional ATM switching system described above, since the capacity of the buffer is limited, for example, when many cells are concentrated on one output HW, cells are discarded when the cells cannot be stored in the buffer memory.

When a large number of cells are stored in the buffer memory, the cell delay time increases. A conventional priority control method adopted in such a case is shown in FIG. 6B.

In this example, priority information indicating whether the priority is high or low is added to the cell header, and the buffer memory 60 corresponding to the input HW is the high priority cell buffer memory 601.
and a low priority cell buffer memory I7602. When a cell is input from the input HW, the priority information of the cell is determined and stored in one of the two buffer memories 601 and 602 depending on whether it is a high priority cell or a low priority cell.

The stored cells are controlled by the read control unit 62 so that they are read out preferentially from the high priority cell buffer memory 601 and output from the selector 61. Therefore 5
In the conventional system, when the delay amount is plotted on the vertical axis and the discard amount is plotted on the horizontal axis as shown in C1 of FIG. 6, the high priority cell has a small delay amount and a small discard amount.

Low-priority cells are subject to control such that the amount of delay is large and the amount of discards is large.

[Problems to be Solved by the Invention] In the conventional method described above, the discard characteristics and delay characteristics cannot be controlled independently, so only one-dimensional control is possible: a high-priority class with fewer discards and less delay, and a low-priority class that is the opposite. Therefore, there was a problem in that it was not possible to control, for example, the delay was small and the number of discards was large. 9 For example, if a low-priority cell occupies the buffer memory, even if a high-priority cell arrives tertiary, it will be discarded. There was a problem that the characteristics were affected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a quality class control method for a communication path of an ATM switch, which can independently control discard characteristics and delay characteristics, and whose characteristics are not affected by cells having a lower priority than the own cell.

[Means for solving the problem] Figure 1 (al is the first principle configuration diagram of the present invention, Figure 1 ('
b) is a diagram illustrating the operation of the first principle configuration, and FIG. 2 is a diagram illustrating the second principle configuration of the present invention.

In Fig. 1(a) and Fig. 2, 1-1 to 1-n and 1'-1 to 1'-n are disposal means, and 2-1 to 2-n are divided and allocated according to each disposal class. 3-1 to 3-n are buffer amount measuring means for measuring the amount of buffer actually used in each of the areas, 4.4' is a discard control section, 5 is a delay control section, 6 is a selector, 7 is a discard class identification means, and 8 is a class comparison means.

In the present invention, each class of discard and delay is assigned to a cell, and the first configuration stores one buffer memory provided at a position connecting a nine-person highway to an output highway in a variable header allocated to each class. By changing the discard class of cells to be discarded according to the usage rate of the buffer memory at that time, cells with a high discard class are protected,
For reading, priority is given to those with a higher delay class. Also the second
The configuration is such that when the buffer memory is full and there is a class lower than the class of the input cell, the cell is discarded from the area of the lower class and the input cell is stored in the empty area.

[Operation] In FIG. 1(a), as shown in B, the input cell has a delay class (one of 1 to m) representing delay quality and a discard class (one from 1 to m) representing discard quality in the header part. 1 in 1-n
) are set in advance and input, and classes representing two qualities are expressed by CL (m, n). in this case,
The smaller the number representing the first delay class, the higher the priority (smaller delay).The smaller the number representing discard after 1, the higher the priority (fewer discards). In addition, each area 2-1 to 2-n in the buffer memory is used by physically dividing one buffer memory into n discard classes, and each area is further divided into n discard classes corresponding to the delay class. It is divided into m pieces.

Cells input from the input HW are supplied to discard means 1-1 to 1-n according to the discard class. At this time.

The discard control unit 4 obtains the usage amount of each buffer memory from the buffer amount measuring means 3-1 to 3-n, thereby knowing the usage amount of the entire buffer memory. on the other hand.

The discard control unit 4 is provided with a table for discard control as shown in A in FIG. 1, etc., and the discard control unit 4 performs discard control in accordance with this table.

This table shows that the buffer usage is Ql (usage rate is 100)
%), input cells of all classes (1 to n) are discarded, and when the usage is Q2 (corresponding to a usage rate of 90%), cells of classes 2 to n are discarded (only class 1 In addition, if the usage amount Qn (corresponds to a usage rate of 70%), only class n is discarded. Disposal control section 4
supplies the result of the determination (whether or not it should be discarded) to one of the discarding means 1-1 to 1-n corresponding to the input cell.

If not discarded, the input cell is stored in one of the areas 2-1 to 2-n of the corresponding buffer memory.

The delay control unit 5 divides the areas divided into delay classes (1 to m) in each area 2-1 to 2-n into B in FIG.
As shown in , the high priority class (lower number) is given priority and read control is performed.

Next, the operation of the second principle configuration shown in Fig. 2 will be explained.
Areas 2-1 to 2-2 by class of buffer memory in Figure 2
○ has a configuration similar to that shown in FIG. 1, and input cells from the 8-manpower HW are stored in divisions eMk&21 to 2-n of the buffer memory corresponding to the discard class. At this time, the waste control section 4' controls each of the Hanfa quantity measuring sections 3-1 to 3.
The amount of the buffer memory in which the cells are stored is checked from -n to determine whether the buffer is in a full state where cells are stored in the entire buffer memory. As a result, when it is found that the buffer is full, the discard class of the manually-powered cell is identified by the discard class identification means 7, and it is determined whether there is a cell lower than that class in the buffer. Discarding means corresponding to discarding the class 1'-1~
Drive 1'-〇. In this way, an empty space is created in the buffer memory, and the empty area is used as an area for the discard class of input cells for storage. If there is no cell in the buffer of a lower class than the discard class of the input cell, the input cell is discarded.

[Example: - Figure 3 is a block diagram of the first embodiment, Figure 4 (a) is a diagram of the principle block diagram of the buffer memory according to the present invention, and Figure 4 (b) is a diagram of cell discard and delay in the first embodiment. Control characteristics.

FIG. 5 is a configuration diagram of the second embodiment.

First, the principle structure of the buffer memory according to the present invention will be explained with reference to FIG. 4(a). In this example, the class is CLI-C
An example with Ln is shown.

Writing and reading of cells are performed in the buffer memory 42. A buffer memory 42 is provided in the free address queue 40.
Cells within are not stored (empty state). Atlus in an area of 1 cell are stored sequentially as a queue. In addition, each class uses the address key 41 for class l cells.
-1 to class n cell usage address queues 41-n are provided, and addresses of cells written in the one-buffer memory 42 are queued for each class.

In this cell write operation to the buffer memory 42, when a cell is input, the class is identified, and the first free address of the free address queue 40 (address 3 in the example shown) is assigned, and if the primary write is possible ( (by discard control), the input cell is written to the allocated free address in the buffer memory 42, and the write address is stored in the cell use address queue 41 corresponding to the identified class.

Reading is controlled to give priority to the delay priority class. For example, if class 1 is given priority, class 1
(CL-1) The cell at the address stored at the beginning of the cell use address queue 41-1 (address 2 in the example shown) is read from the buffer memory 42 as a read address. The read address 2 is stored at the rear end of the empty address queue 40.

Next, in Figure 0 for explaining Example 1 shown in Figure 3, 2
0 is a buffer memory, 21 is a quality class identification circuit, 22
23 is a cell arrival detection circuit, and 23 is an empty address queue 224.
The buffer usage measurement circuit 125 is class I (CLI
) Cell address queue.

26 is a class 2 (CL2) cell address queue.

27-1 and 27-2 are comparison circuits, 28 is a read queue selection section, and 29 is a read control section.

Embodiment 1 shows a configuration related to a buffer memory of one switching element in a communication path of an ATM switch.
In this example, there are two quality classes.

A case is shown in which class 2 has more discards than class 1 but has a smaller delay, and class 2 has a larger delay than class l but has fewer discards.

FIG. 4(b) shows this example. To explain the cell discard and delay control characteristics, when the buffer memory 20 usage is 100%, both class I and class 2 cells are discarded, and when it is 80%, class 2 cells are discarded. . Also, what is the delay priority?

Class 2 cells are read out with priority over class 1 cells.

The buffer memory 20 of the first embodiment is controlled by the same principle as shown in FIG. 4(a) above, and the operation shown in FIG. 3 will be explained below.

When a cell is input from the input HW, the cell arrival detection circuit 22
When the arrival of a cell is detected, the head address of the empty cell area in the buffer memory 20 is taken out from the empty address queue 23, and an attempt is made to write the arrived cell into the buffer memory 20 from that address. At this time, writing judgment is made based on the discard characteristic shown in FIG. 4 Φ). Namely.

In the buffer usage measurement circuit 24, the buffer memory 2
The current usage amount (usage rate) of 0 is measured.

The usage rate is supplied to the comparison circuits 27-1 and 27-2. The comparator circuit 27-1 receives 100% as the usage amount Q1 from another input terminal, and the usage amount Q2 of 8% is input to the comparison circuit 27-2.
0% is entered. As a result, the comparison circuit 27-1
If the usage does not reach 100%, 1" is generated. In the case of a class 1 cell, "1" is generated from the AND circuit A1 and is supplied to the buffer memory 20 as a write control signal to perform writing. At the same time, the write address (empty address) of the cell is stored in the CLI cell address queue 25. When the usage reaches 100%, writing to CLI cells (including Cl3 cells) is prohibited (from the comparison circuit 27-1). O” occurs).

Comparison circuit 27-2 indicates that when the usage is less than 80%, °°
0'' is generated and the AND circuit A2 is class 2 (Cl3
), the write address of the cell is stored in the 1CL2 cell address queue 26, and if the usage is 80% or more, the comparison circuit 27-2 to 1
``'' occurs, AND circuit A2 is inhibited, and class 2 cells are not written (discarded). In this way, the number of class 1 cells discarded is reduced.

CLI cell address queue 25. The CL2 cell address queue 26 is provided with a 1 empty flag, and if at least one queue is stored, this flag is set to "1". The read control unit 29 performs read when a read permission signal (a control signal input at a timing when cell output is allowed in this switch) is input. First, the 2 read control unit 29 monitors the empty flag of the cell address queue for each class by the read queue selection unit 28, and if both classes 1 and 2 are written in the buffer memory, the class 2 cell is read out first. . In this case, the head address of the queue is taken out from the CL2 cell address key '-26.

It is supplied as a read address to the buffer memory 20 via gate G2. The read cells are output to the output HW. The read address at this time is written to the free address queue 23 under the control of the read control unit 29.

In addition to the above, for read control, it is also possible to use a method of changing the read frequency between classes without assigning absolute read priorities to each class.

Next, the configuration of the second embodiment shown in FIG. 5 will be explained.

In Figure 5, 20-23.25.26.28 and 2
9 corresponds to each device with the same reference numeral shown in FIG. 3, and 5 names are the same.

In the case of Example 2, there are two quality classes as in Example 1 above, and class 2 has more discards than class 1, but the delay is smaller, and class 1 has more delays than class 2, but fewer discards. This is the case.

To explain the operation, the cell arrival detection circuit 22 receives the input H
When the arrival of a cell from W is detected, the free address queue 2
An attempt is made to write the arriving cell from 3 to the buffer memory 20. The writing judgment at this time is made as follows. That is, first, the quality class identification circuit 21 identifies the quality class of the cell that has arrived, and a signal representing whether or not the buffer memory is full is extracted from the free address queue 23, and the AND circuit A3. Enter on A4. The full state of the buffer memory 20 is indicated by a signal (empty flag) indicating that no free address is stored in the free address queue 23. If the signal representing the full state is "1".

AND circuit A4 is prohibited and cannot write to class 2 cells (discarded). However, if the input cell is class 1, and the buffer memory is full, there is already a class 2 cell in the buffer memory 20. If the cell has not been written (the empty flag of the CL2 cell address queue is 1').

The read'-control unit 29 outputs a read signal from the 2 read signal line 290 to the CL 2 cell address queue 26. As a result, the CL2 cell address key 26 address (head of the queue) is read (class 2
3 cells in question are discarded), and are written to the free address queue 23 as a free address via the OR circuit ORI (
full state is released). In this way, the input class 1
The cell is written into the buffer memory 20 at the location indicated by the free address read from the free address queue 23, and at the same time, the address is stored in the CLI cell address queue 25. In this way, class I cell discards are reduced.

At the time of reading, in the reading control unit 29.

The empty flags of the address queues 25 and 26 for each class are monitored, and if both classes 1 and 2 are written in the buffer memory 20, delay control is performed to read out the class 2 cells first. This allows the class 2 delay to be reduced.

[Effects of the Invention] According to the present invention, since the discard characteristics and the delay characteristics can be controlled independently, it is possible to realize control of various quality classes, for example, a class with many discards but a small delay, and vice versa. By restricting writing to low-priority cells depending on the amount of buffer memory used or discarding them, the characteristics of the class will no longer be affected by the influence of cells of a class with a lower priority than manually generated cells.

[Brief explanation of the drawing]

FIG. 1(a) is the first principle configuration diagram of the present invention, FIG. 1(b)
1 is an explanatory diagram of the operation of the first principle configuration, FIG. 2 is a diagram of the second principle configuration of the present invention, FIG. 3 is a diagram of the configuration of Example 1, and FIG.
a) is a principle block diagram of the buffer memory according to the present invention, No. 4
FIG. 5 shows the control characteristics of cell discard and delay in the first embodiment, FIG. 5 shows the configuration of the second embodiment, and FIG. 6 shows an explanatory diagram of the conventional example. Figure 1 (a), 5 in Figure 2 ■-1 to 1-n: Disposal means 1'-1 to 1'-n: Disposal means 2-1 to 2-n: Data in the buffer memory for each discard class. Each area 3-1 to 3-n/Buffer amount measuring means 4, 4': Discard control section 5: Delay control section 6: Selector 7: Discard class identification means 8: Class comparison means

Claims (2)

[Claims] (1) In a quality class control method for the communication path of an ATM switch that is equipped with a buffer memory in a switching element that connects a plurality of input/output highways, quality classes are added to cells according to their discard characteristics and delay characteristics; The discard control unit divides one buffer memory into areas corresponding to the quality class according to the amount of arrival thereof, and the discard control unit divides the input cells into areas of the corresponding quality class of the buffer memory according to the total usage of the buffer memory. control to discard cells that exceed a preset threshold independently for each discard quality class, and the delay control unit performs priority control of read order in accordance with the delay quality class when reading from the buffer memory. A quality class control method for the communication path of an ATM switch, which is characterized by performing the following: (2) In a quality class control method for the communication path of an ATM switch that is equipped with a buffer memory in a switching element that connects a plurality of input/output highways, quality classes are added to cells according to their discard characteristics and delay characteristics; When writing an input cell to the buffer memory, the discard control unit divides the input cell into areas corresponding to the quality class according to the amount of arrival, and when the input cell is written to the buffer memory, the discard control unit divides the input cell into areas corresponding to the quality class based on the output of the full state detection means of the total usage of the buffer memory. Cells are discarded from areas of classes lower than the cell discard quality class, the empty area is allocated as an area for the quality class of the input cell, and the input cell is controlled to be written, and the delay control unit corresponds to the delay quality class. An ATM characterized by performing priority control of reading order by
A quality class control method for the communication path of an exchange.