JPH04206814A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain a potential barrier on a hetero junction interface, and prevent the increase of resistance, by inserting a III-V compound semiconductor layer having a specified thickness which contains P and As, between hetero junction interfaces. CONSTITUTION:In the hetero junction structure of the title semiconductor device, (1) is a P-GaAs substrate, (2) are P-InGaAsP layers which are lattice-matched with GaAs, (3) is a P-InGaAs layer which is lattice-matched with GaAs, (4) is a P-GaAs layer, and 5a, 5b are ohmic electrodes for current flow. According to the current-voltage characteristic shown in figure, it can be known that, by inserting the P-InGaAsP layers 2 between the P-InGaAs layer 3 and the GaAs layers 1, 4, the current-voltage characteristics excellent in linearity can be obtained, and the resistance value is decreased at a voltage lower than or equal to 0.5V.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to the structure of a heterojunction of a ■-V group compound semiconductor.

[Conventional technology]

A heterojunction formed by successively growing different materials is a structure used in many devices such as optical devices and electronic devices.

By the way, in devices that allow current to flow through this heterojunction, the discontinuity of the energy band at the heterojunction often becomes a barrier to the current, resulting in an increase in resistance.

For example, FIG. 2(a) shows a P-GaAs layer P-1nGaP
FIG. 2(b) is a cross-sectional view showing a heterojunction structure composed of a P-GaAs layer, and FIG. 2(b) shows a current-voltage characteristic curve diagram of FIG. 2(a).

In the figure, (1) is a P-GaAs layer, and (3) is a GaAs layer.
P-1nGaP layer lattice matched to (4) is P-GaA
The s-layers (5a) and (5b) are ohmic electrodes for flowing current.

This structure consists of a P-GaAs substrate Cl1l, a P-1nGa
After epitaxially growing the P layer (3) and the P-GaAs layer (4) one after another by MOCVD, the area containing the P Kawaguchi Ga and P layer (3) was processed by mesa etching to form a 40 μm×
It is processed to have a size of 40 μm, and ohmic electrodes (5a) and (5b) are formed on the P-GaAs layers (1) and (4).

The current-voltage characteristics of this device exhibit nonlinearity as shown in Figure 2(b), and the P-1nGaP layer (3) and P-GaAs
It appears that an energetic barrier exists at the interface between layers (1) and (4).

This nonlinearity results in increased resistance and sometimes causes device deterioration.

In a heterojunction like the one described in item 1, group V elements can be easily substituted at the hetero interface, for example, P and P- in the P-InGaP layer (3).
By replacing As in the GaAs layers (1) and (4), InGaA
This may be due to the formation of compounds such as s or GaP. InG
aAs has a smaller band gap than InGaP and GaAs (and GaP has a larger band gap than both of them. Therefore, when these compounds are formed at the interface, the original l n Ga P and GaAs It is thought that an energy gap larger than the band gap difference is generated, resulting in large current-voltage nonlinearity.

[Invention or problem to be solved]

Conventional semiconductor devices having this type of heterojunction are as follows:
The presence of a potential barrier at the junction interface, as shown in Figure 1, causes non-linearity in current-voltage characteristics, resulting in an increase in resistance.

This invention was made to solve the above-mentioned problems, and aims to suppress the increase in resistance due to the presence of a bottom barrier and to obtain a heterojunction with low resistance.

[Means to solve the problem]

The semiconductor device according to the present invention comprises a ■-V group compound semiconductor having a layer thickness of 500 Å or more containing only P as a group ■ element;
■ With a layer thickness of 500 Å or more containing only As as a group element
In a heterojunction of a -V group compound semiconductor, a -V group compound semiconductor having a layer thickness of 20 Å to 200 layers containing both P and As is inserted at the heterojunction interface.

[Effect]

The semiconductor device according to the present invention suppresses interference at the hetero interface and suppresses an increase in resistance.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 1(a) is a sectional view showing a heterojunction structure of a semiconductor device which is an embodiment of the present invention, and FIG. 1(b) is a sectional view of FIG. 1(a).
The current-voltage characteristic curve diagram is shown. In the figure, (1) is P
-GaAs substrate, (2) is P- lattice matched to GaAs
InGaAsP layer (3) is P layer lattice matched to GaAs
-InGaP layer, (4) is P-GaAs layer, (5a),
(5b) is an omic electrode for passing current.

This structure is the same as the structure of the previous one in 1jir.
It is manufactured by epitaxial growth using the MOCVD method, mesa etch, and electrode formation.

FIG. 1(b) shows the current-voltage characteristics of the device of the present invention in comparison with that of the structure shown in FIG. 2(a).

As is clear from this current-voltage characteristic, P-InGa
P- between the P layer (3) and the P-GaAs layers (1) and (4)
By inserting the InGaAsP layer (2), current-voltage characteristics with good linearity can be obtained, and 0.5VJ),
It can be seen that the resistance value also decreases at the lower voltage level.

In addition, in Embodiment 1, the case of a heterojunction between an InGaP layer and a GaAs layer was described, or lnA, ffxGa
Similar effects can be obtained in the case of the l□P layer and the AlyGa1-yAs layer.

Also, lnA, i? Needless to say, the same applies to the case of a heterojunction between a zGal-zAS layer and a 111P layer.

Furthermore, although the above embodiments have described a P-type heterojunction, the same effect can be achieved in the case of an N-type heterojunction.

〔Effect of the invention〕

As described in 2 below, according to this invention, a group IV compound semiconductor having only P as a group V element and
By inserting the -V group compound semiconductor containing both P and As into the heterojunction interface of the -V group compound semiconductor, a heterojunction with a low resistance value can be realized.

[Brief explanation of the drawing]

FIG. 1(a) is a cross-sectional view showing a heterojunction structure of a semiconductor device according to an embodiment of the present invention, and FIG.
Fig. 2(a) is a cross-sectional view showing the heterojunction structure of a conventional semiconductor device; Fig. 2(b) is a current-voltage characteristic curve diagram.
is a current-voltage characteristic curve diagram of FIG. 2(a). In the figure, (1) is a P-GaAs substrate, (2) is a P-GaAs substrate, and (2) is a P-GaAs substrate.
InGaAsP layer, (3) is P-InGaP layer, (4)
indicates a P-GaAs layer, and (5a) and (5b) indicate ohmic electrodes. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A layer with a thickness of 500 Å or more containing only P as a group V element
A semiconductor device composed of a heterojunction of a III-V compound semiconductor and a III-V compound semiconductor with a layer thickness of 500 Å or more containing only As as a group V element, which has both P and As at the heterojunction interface. 20Å~200
1. A semiconductor device characterized in that a III-V group compound semiconductor having a layer thickness of Å is inserted.