JPH04206783A - Light-emitting element array driver - Google Patents

Abstract

PURPOSE:To make it possible to obtain a light-emitting element array driver having a simple configuration and a low power consumption by varying independently and in multiple stages the pulse width for driving each light-emitting element by pulse width-determining means in response to the input signal with a plurality of bits. CONSTITUTION:A picture signal DATA of n bits per picture element is sequentially applied to a shift register 2. The picture signal DATA sequentially shifts through the shift register 2; and the picture signal is held by a latch circuit 5 within a basic processing unit 1 when the data of one line is taken in the shift register 2 and is input to a comparator 6 until the end of a next line. This comparator 6 monitors the output from the latch circuit 5 and the output from a counter 4 and sends out a coincidence pulse to a flip-flop 7 when both of them have agreed.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an optical element array driving device.

(Prior Art) Devices have been put into practical use that record characters and images using an LED array in which many light emitting diodes (hereinafter abbreviated as LEDs) are arranged in high density.

One pixel is recorded by blinking each LED on the LED array, but the characteristics of the LEDs are not necessarily uniform, and the fact is that variations in the amount of light of about ±30% are unavoidable in the manufacturing process.

However, since this fluctuation in the amount of light from the LED directly causes uneven recording density, the driving device corrects it.

FIG. 3 is a schematic configuration diagram showing an example of a conventional LED array driving device.

This drive device is disclosed in Japanese Patent Application Laid-Open No. 2-4547. In the figure, PIX is an image signal of n bits per pixel that is serially input from the outside pixel by pixel, and CK is 1 bit of the image signal PIX. Tarotuku, LCK synchronized every time
is a line clock synchronized with the shift of the image signal PIX by one line. 11 is the LED array, 12 is this LE
a driver unit 13 that drives each LED on the D array 14;
14 is a correction ROM that stores N bits of light intensity variation correction data for each LED on the LED array 11; and 14 is an address counter that receives the clock CK and line clock LCK as input and generates a read address for the correction ROM 13.

According to this read address, correction data corresponding to each pixel of the image signal PIX is read out from the correction ROM 13 as an N-bit correction signal.

] 5 is a conversion ROM which inputs an N-bit correction signal and an n-bit image signal PIX, and outputs a multiplied signal of both signals as a Q-bit correction signal *PIX. 16 is a serial/parallel converter that sequentially takes in and shifts the correction signal *PIX outputted from the conversion ROM 15 in Q bits in parallel at the timing of the aforementioned clock CK. When the input of one line of image signal PIX is completed, this serial/
The parallel converter 16 outputs correction signals *PIX of all pixels for one line in parallel. 17 is serial/
This is a false part that latches the corrected image signals from the parallel converter 16 all at once at the timing of the strobe signal STB and holds them until the recording is completed.

] 8 is a chopper generation circuit (generation unit) consisting of a chopper generation circuit associated with each LED on the LED array 11;
A gradual signal corresponding to ED is output continuously within one line scanning period in synchronization with clock CK. Each LE
The Chiyo/Sono signal for D has a duty ratio according to the corresponding corrected image signal input from the latch section 17,
The signal is input to the driver section 12 as a light emission time control signal. This driver section 12 time-divisionally drives each LED 0 times. At this time, current is applied to each LED only during the high level of the chopper signal to cause it to emit light. The corrected image signal held in the latch section 17 does not change during one line scanning time, and the duty ratio of each chopper signal at each time is also constant.

Therefore, in one line scanning time, each LED emits light zero times for a time corresponding to the duty ratio of the chopper signal.

In the above-mentioned LED array driving device, the light emitting time of each LED on the LED array 11 is controlled to correct variations in light amount according to a multi-bit correction signal, and is increased or decreased according to a multi-bit input image signal PIX,
It is possible to reduce uneven recording density due to variations in light amount.

(Problem B to be Solved by the Invention) In the conventional LED array drive device having the above configuration, the individual LEDs constituting the LED array 11
A chopper generation circuit is required to generate a chopper signal.

FIG. 4 is a diagram showing one chopper generating circuit in the chopper generating section 18 of the drive device shown in FIG. 3. FIG.

In the figure, 21 is this chopper generation circuit, 22 is one latch circuit in the latch section 17, 23 is one constant current drive circuit in the driver section 12, and 24 is one LED in the LED array 11. It is.

As shown in the figure, one chopper generation circuit 21 in the chopper generation section 18 includes a comparator 25, a counter 26,
It consists of a JK flip-flop 27, and has the problem of a complicated circuit configuration and high power consumption. Furthermore, when increasing the number of signal bits and performing highly accurate control, there arises the problem that the circuit scale and power consumption further increase.

The optical element array driving apparatus of the present invention has been made with attention to the above points, and is an optical element array driving apparatus that drives each optical element individually by simple means and has a simple configuration and low power consumption. The purpose is to obtain.

(Means for Solving the Problems) In the driving device of the present invention, the pulse width determining means corresponding to each element of the optical element array is composed of a latch circuit, a comparator, and a flip-flop, and a counter that generates a comparison reference signal for the comparator. is common to all the optical elements. With this configuration, the above-mentioned purpose is achieved by making the rising edge of the pulse simultaneous for all of the optical elements and determining the falling edge of the pulse individually based on the output of the comparator.

(Function) As described above, in the present invention, the pulse width for driving each light emitting element is independently changed in multiple stages by the pulse width determining means in accordance with a plurality of bits of input signals.

(Embodiment) FIG. 1 is a schematic diagram showing an embodiment of an optical element array driving device of the present invention.

In the figure, 1 is a basic processing unit for one light emitting element, 2 is a shift register for sequentially shifting image signals in time series, which will be described later, 3 is a light emitting element array, and 4 is a counter for counting a clock, which will be described later. It is. The basic processing unit 1 includes a latch circuit 5, a comparator 6,
It is composed of a flip-flop 7 and a driver 8 that drives one light emitting element 9 in the light emitting element array 3.

Next, signals will be explained. In the same figure, DATA
The abbreviated signal is an image signal of n bits per pixel that is input serially. Similarly, CLK is a reference signal (hereinafter referred to as clock) synchronized with each bit of this image signal, and LCLK is a signal for one line. a period for capturing the image signal;
That is, it is a latch clock that operates every one line drive period.

The operation will be explained based on the figure.

The image signal DATA of n bits per pixel is sequentially applied to the shift register 2. The shift register 2 has a capacity that can take in the number of light emitting elements in the light emitting element array 3 multiplied by the number of bits n of the input signal, that is, data for driving one line. The image signal DATA is sequentially shifted in the shift register 2, and when one line of data is taken into the shift register 2, the basic processing unit is started.

The image signal is held by the latch circuit 5 in the unit 1 and is input to the comparator 6 until after the next line.

As can be seen from the figure and the above description, the basic processing unit 1 corresponds to one light emitting element 9 in the light emitting element array 3, and further includes a latch circuit 5 and a comparator 6.
correspond to the signal amount of n bits, respectively.

On the other hand, the clock CLK is counted by counter 4,
The output is input to comparator 6.

This comparator 6 monitors 17 the output from the latch circuit 5 and the output from the counter 4, and sends a matching pulse to the flip-flop when the two match.

FIG. 2 is a diagram showing a timing chart of each part of the drive device of FIG. 1.

(a) to (f) in Figure 2 are each (a) described in Figure 1.
) to (f). The explanation will be continued with reference to FIG.

As shown in FIGS. 2(a) and (b), the latch clock LCLK falls upon detecting the end of one line driving period of the image signal DATA, and immediately before the start of one line driving period of the next data. It is configured to rise up, and can be easily realized using a logic circuit IC. This latch clock signal L
CLK is applied to the flip-flop 7 as shown in FIG. 1 after being delayed for a desired time by the delay circuit 10 as shown in FIG. 2(b). This flip-flop 7 is connected to a delay circuit 10 as shown in FIGS. 2(e) and 2(f).
It outputs a pulse that rises in response to the passed latch clock LCLK and falls upon detecting the rise of the matching pulse of the comparator 6.

The output of this flip-flop 7 is shown in FIG. 2(e).

As shown in (f), the light is applied to the driver 8 at the same timing, causing the light emitting element 9 to emit light.

From the above explanation, it is understood that the pulse time width for causing each light emitting element to emit light can be controlled with precision that can be expressed by the number of bits of data.

As shown in FIG. 1, the basic processing unit 1 of the drive device of this embodiment is composed of a latch circuit 5, a comparator 6, a flip-flop 7, and a driver 8. here,
The latch circuit 5 is, for example, TEXAS INSTRU
In addition to the 74L5 373 manufactured by MENT Co., Ltd., the comparator 6 can be realized using the 74LS 85 manufactured by the same company. Similarly, the flip-flop 7 can be realized by using 74LS 73 manufactured by the same company, and the driver 8 can be realized by a simple circuit consisting of a combination of a transistor and a resistor. In this way, the drive device of this embodiment can be realized by combining existing ICs and electronic components.

In this embodiment, the pulse width is controlled by digital signal processing, but each block in FIG. 1 can also be realized by analog circuits.

As the optical elements constituting the optical element array, not only light emitting elements such as light emitting diodes and laser diodes, but also light receiving elements such as light receiving diodes can be applied.

Furthermore, since the present invention converts a serial signal into a parallel signal and drives it using a simple circuit, it is applicable not only to one-dimensional optical element driving but also to a two-dimensional optical modulation device which has a large circuit scale and is complicated. It can also be applied, and its effects are great.

(Effects of the Invention) The optical element array driving device of the present invention having the above configuration converts the drive signal level of each element constituting the array into a pulse width size by a simple means, and drives each element. can be driven in parallel, and an optical element array driving device can be provided with a simple configuration and low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of an optical element array driving device of the present invention, FIG. 2 is a diagram showing a timing chart of each part of the driving device of FIG. 1, and FIG. 3 is a diagram showing a conventional LED array driving device. A schematic configuration diagram showing an example of the device, FIG. 4 is a diagram showing a chopper generating circuit of the drive device of FIG. 3. 1... Basic processing unit for one light emitting element, 2
...Shift register (signal shifting means), 3...Light emitting element array, 4...Counter (pulse width determining means), 5...Latch circuit (pulse width determining means), 6...Comparator (comparison) 7... flip-flop (pulse width deciding means), 9... one light emitting element (optical element) in the array 3, 8... driver (output means). Patent applicant: Victor Japan Co., Ltd.

Claims (2)

[Claims] (1) In an optical element array driving device having a plurality of independent optical elements, a signal shifting means for sequentially shifting an input signal in time series, and a signal shifting means for sequentially shifting an input signal for one horizontal scanning period for each of the optical elements in the signal shifting means. a pulse width determining means for determining a pulse width in accordance with the magnitude of an input signal; and an output means for outputting the pulse determined by the pulse width determining means to each of the optical elements; The optical element array driving device is characterized in that the pulse width determining means determines the pulse width to be output in the next horizontal scanning period in accordance with the signal output from the optical element array. (2) The pulse width determining means that determines the pulse width has a comparator that compares two input signals, and the first
As an input signal, a value obtained by counting the reference signal is applied, and as a second input signal, an input signal of one horizontal scanning period taken into the signal shifting means is applied, and the pulse width determining means applies a value obtained by counting the reference signal. 2. The optical element array driving apparatus according to claim 1, wherein the pulse generation is started at the same time as the horizontal scanning period starts, and the pulse generation is stopped when the two input signals match.