JPH04205887A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the characteristic of an element resulted from a decline in the breakdown voltage caused by the miniaturization of the element by giving two different currents and voltages for an input-output circuit and internal circuit from the outside and converting the supply voltage for internal circuit into a voltage of a level suitable for each circuit by means of an internal regulator. CONSTITUTION:A power supply terminal 1a across which the first power supply voltage Vcc1 of 5V is applied and another power supply terminal 1b across which the second power supply voltage Vcc2 of 3.3V is applied are provided. On the other hand, the second voltage Vcc2 is supplied to the peripheral circuit 3 of a memory array 5 and directly drives the circuit 3. At the same time, the voltage Vcc2 is also supplied to a voltage conversion circuit 4, such as switching regulator, etc., and the circuit 4 supplies a voltage Vcc' suitable for driving the memory array 5 to the memory array 5 after converting the voltage Vcc2 into the voltage Vcc'. Therefore, the deterioration of the breakdown voltage of an element caused by the miniaturization of the element can be prevented without lowering the noise margin which invites an increase in power consumption of the LSI.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to an IC power supply system, such as a power supply system in a TTL compatible MO8 type memory. Concerning techniques that can be used effectively.

[Prior Art] In recent years, as the miniaturization of LSIs has progressed, in MO6LSIs, if the power supply voltage remains constant at 5V, there will be some problems in device characteristics such as short channel effects, generation of hot electrons, and reduction in breakdown voltage.

Therefore, as shown in FIG. 4, a step-down circuit 4 is installed inside the LSI.
', the human output buffer 2 is driven with a power supply voltage Vcc such as +5V supplied from the outside, and the memory array section 5, decoder, etc. An LSI memory adapted to drive the peripheral circuit 3 has been proposed (Patent Application No. 1-658).
No. 40).

[Problems to be Solved by the Invention] The invention of the prior application has the advantage that each circuit can be driven with a voltage that matches the breakdown voltage of the element.

However, a relatively large current flows through the output circuit, which is driven at a voltage higher than the voltage of the internal circuit and is configured to have a large load driving force. Therefore, if one power supply voltage is applied from the outside, the input/output circuits are driven directly by that power supply voltage, and the internal circuits are driven by the voltage stepped down by the internal step-down circuit, the problem occurs in the output circuit. Power supply noise may be transmitted to internal circuits, causing malfunctions or reducing noise margins. Also, +
Since an external power supply voltage such as 5V is converted into a voltage with a large level difference such as 3V, there is a problem in that the power consumption of the step-down circuit is large.

Furthermore, if the output is wire-ORed with the output of another LSI and a pull-down resistor is connected to the output signal line, it is expected that current will flow from the power supply voltage Vcc to the outside through the output buffer. Therefore, if the power supply voltage is common as in the past, the step-down circuit, internal circuit, or board on which the LSI is mounted must be designed in consideration of such a situation. There is a problem that it becomes troublesome.

Moreover, the power supply voltage of the output circuit is at a high level of 2°4V (mi
As long as n) is satisfied, the power supply voltage supplied to the step-down circuit is required to be as stable and accurate as possible, although there may be some unevenness in the level. Therefore, if the power supply voltage of the output circuit and the step-down circuit is common as in the past, the power supply voltage of the output circuit must be at an accurate level and stable even when a large current flows in accordance with the step-down circuit. must be designed.

An object of the present invention is to provide a semiconductor integrated circuit technology that can prevent deterioration of breakdown voltage of elements due to miniaturization without increasing power consumption or reducing noise margin, and also allows easy board design. be.

Another object of the present invention is to provide a semiconductor memory that can be easily backed up in the event of a power outage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem] It is expected that the withstand voltage of elements will further decrease in the future due to the miniaturization of elements due to advances in process technology, and it is necessary to lower the external power supply potential supplied to semiconductor memory chips. It will stop happening. On the other hand, current semiconductor memories are TTL compatible, and it is expected that memory control devices on the same memory board will continue to have TTL interfaces.

The present invention has been made in consideration of the above situation.

A summary of typical inventions disclosed in this application is as follows.

In other words, two different power supply voltages (for example, 5V and 3.3V) are applied from the outside for the input/output circuit and the internal circuit, and the power supply voltage for the internal circuit is further supplied internally, and a regulator is used to adjust the level suitable for each circuit. Convert it to voltage and supply it. Along with this, MOS F that constitutes the input/output circuit
The ET has a gate insulating film formed thicker than that of the MOSFET that constitutes the internal circuit.

In the above case, it is preferable that the internal regulator is provided with an adjustment means for finely adjusting the generated voltage. Adjust accordingly.

[Operation] According to the above-described means, the MOS forming the input/output circuit
Since FET has a high withstand voltage, there is no deterioration in element characteristics even when a high power supply voltage such as 5V is applied, and the TTL level interface condition of 2)4 (min) can be guaranteed, and the internal circuit is Since it can be driven with a power supply voltage as low as 0.3 mm, it is possible to prevent deterioration of device characteristics even if the withstand voltage decreases as the device becomes smaller.

Moreover, according to the above-mentioned means, since the power supply voltage for the input/output circuit and the power supply voltage for the internal circuit are supplied separately, the internal regulator only needs to generate the desired voltage from a low voltage, reducing power consumption. In addition, there is no risk that power supply fluctuations generated in the input/output circuit will be transmitted to the internal circuit and reduce the noise margin.

Furthermore, the power supply voltage supplied from the outside only needs to be accurate and stable even for the internal circuit, and the magnitude and fluctuation of the current in the input/output circuit section do not affect the internal circuit, making the design easier.

In addition, when applied to semiconductor memory, the power supply voltage is 2
If there is one, only the low-potential power supply voltage for internal circuits needs to be supplied during a power outage, making backup easier and reducing power consumption.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a semiconductor memory.

In the figure, each circuit block surrounded by a dashed line A is formed on a single semiconductor substrate such as single crystal silicon.

In the memory of this embodiment, a power supply terminal 1a to which a first power supply voltage Vccl such as 5V is applied from the outside;
A power supply terminal 1b to which a second power supply voltage ~'cc2 such as 3.3V lower than this first power supply voltage Vccl is applied.
and is provided.

Of these, the first power supply voltage ˜ccl is supplied to the traffic buffer circuit 2 so that TTL level signals can be input and output.This ensures a TTL interface.

On the other hand, the second power supply voltage Vcc2 is supplied to the memory array peripheral circuits 3 such as decoders and sense amplifiers to directly drive them, and is also supplied to the voltage conversion circuit 4 such as a switching regulator to drive the memory array. 3) It is converted into a suitable voltage Vcc' such as OV and applied to the memory array 5.

FIG. 2 shows a second embodiment of a semiconductor memory to which the present invention is applied.

Similar to the first embodiment, this embodiment is provided with power supply terminals 1a and lb to which two power supply voltages Vccl and Vcc2 having different potentials are applied from the outside, and a 5V system power supply voltage Vc
The human output buffer circuit 2 is configured to be driven by cl. The difference is that the voltage conversion circuit 4
For example, 3. based on the power supply voltage ■cc2. Ov and 3.6
It is possible to generate two voltages Vcc' and Vcc'' such as V, so that the peripheral circuit 3 and the memory array 5 are each driven with an optimum power supply voltage.

In both the embodiments shown in FIG. 1 and FIG. 2, the power conversion circuit 4 includes means for adjusting the level of the generated voltage.

FIG. 3 shows an example of the configuration of the voltage conversion circuit 4. As shown in FIG.

The voltage conversion circuit 4 of this embodiment has a voltage of 1.1V at the inverting input terminal.
A differential amplifier 41 to which a reference voltage Vref such as
and a voltage dividing means 42 consisting of MOSFETs Ql to Q4 connected in series between the power supply voltage Vcc2 and the ground point;
The first and second MOSFETs Ql of this voltage dividing means 42
, Q2 connection node pasting and 3rd) 4th (7) MOSFET
Q3. A MOSFET is connected between Q4 and connection node n2.
Q21゜Q22 and fuse F1 and MOSFET
The first voltage regulating means 4 is formed by connecting Q23 in series.
3a, and a MOSF between the connection node n2 and the ground point.
ET Q24, fuse F2 and MOSFET
A second voltage regulating means 43b formed by connecting Q25 in series.
By applying the potential of the node n2 to the non-inverting input terminal of the differential amplifier 41, 3
．． A reference voltage VL such as OV is generated. This reference voltage VL is applied to the inverting input terminal of the differential amplifier 44, and the internal power supply voltage Vcc' is generated by the buffer amplifier 45 at the subsequent stage.

The voltage conversion circuit 4 includes voltage adjustment means 43a.

The gate terminals of MOSFETs Q23 and Q24 constituting MOSFET 43b are connected to the power supply voltage terminal Vcc2 via pull-up resistors R1 and R2, respectively, and the pad P
L, connected to P2. These pads PL and P2 are connected to the MOSFET Q by applying a ground potential during probe testing.
This is provided to obtain the optimum internal power supply voltage Vcc' by turning off Q23 or Q24 and changing the reference potential VL. Internal power supply voltage V c c during probe inspection
' If it is determined that it is desired to set the value higher, the fuse Fl is cut using a laser. On the other hand, the internal power supply voltage
If you decide that you want to set cc' lower, just disconnect fuse F2.

As explained above, in the above embodiment, two different power supply voltages are applied from the outside, one for the input/output circuit and the other for the internal circuit, and the power supply voltage for the internal circuit is further converted by an internal regulator into a voltage at a level suitable for each circuit. In addition, the MOSFETs that make up the input/output circuit are supplied with MOSFETs that make up the internal circuit.
Since the gate insulating film is made thicker than that of the SFET, there is no deterioration of the device characteristics even when a high power supply voltage of 5 µ is supplied to the input/output circuit, which meets the TTL level interface conditions. 2, 4 V (min)
In addition, since the internal circuit can be driven with a low power supply voltage such as 3.3V, it is possible to prevent deterioration of device characteristics even if the withstand voltage decreases as the device becomes smaller.

In addition, since the power supply voltage for the input/output circuits and the power supply voltage for the internal circuits are supplied separately, the internal regulator only needs to generate the desired voltage from a low voltage, reducing power consumption. There is no risk that power fluctuations generated in the circuit will be transmitted to the internal circuit and reduce the noise margin.

Further, the power supply voltage supplied from the outside only needs to be accurate and stable even for the internal circuit, and the design is facilitated because the magnitude and fluctuation of the current in the input/output circuit section do not affect the internal circuit.

Furthermore, when applied to a semiconductor memory, if there are two power supply voltages, only the low potential power supply voltage for internal circuits needs to be supplied in the event of a power outage, making backup easy and reducing power consumption.

Furthermore, if the voltage conversion means such as an internal switching regulator is provided with a means for finely adjusting the voltage, it is possible to adjust the voltage to a level that increases the operating margin of the circuit during probe testing or to the optimum level that increases the operating speed of the circuit. It becomes possible to generate and supply power supply voltage.

Further, since the internal power supply regulator can suppress fluctuations in the internal power supply potential to a constant level with respect to potential fluctuations in the external power supply, the dependence of each characteristic on the external power supply voltage can be reduced. Moreover, by adjusting the potential generated by the regulator, it is possible to supply a power supply voltage that compensates for the deterioration of the power supply margin, refresh characteristics, and access time due to process variations from lot to lot, factory to factory, and chip to chip. It is possible to improve yield and product grade distribution.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, a fuse cut by a laser is used as a voltage fine adjustment means in a regulator serving as a voltage conversion means, but this fuse may be cut by passing a current through it.

In the above explanation, the invention made by the present inventor was mainly applied to semiconductor memory, which is the background field of application. It can be used in general circuit devices.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to prevent deterioration in breakdown voltage of elements due to miniaturization without increasing the power consumption of the LSI or reducing the noise margin. Also, backup in case of power outage becomes easy.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment in which the present invention is applied to a semiconductor memory, and Fig. 2 shows a second embodiment in which the present invention is applied to a semiconductor memory. FIG. 3 is a circuit diagram showing an example of a switching regulator as a voltage conversion means, and FIG. 4 is a block diagram showing an example of a power supply system in a conventional semiconductor memory. la, lb...power supply terminal, 2...input/output circuit section, 3
- Memory peripheral circuit, 4... Voltage conversion means (switching regulator), 5... Memory array. Figure 1 Figure 2

Claims (1)

[Claims] 1) It has a plurality of power supply terminals that receive power supply voltages of different levels supplied from the outside, and is equipped with an internal voltage conversion means, and the input/output circuit section receives power supply voltages that are higher than the power supply voltages supplied from the outside. 1. A semiconductor integrated circuit device, characterized in that it is driven by a power supply voltage, and the internal circuit is configured to be driven by a low power supply voltage and/or a voltage converted by the voltage conversion means. 2) The semiconductor integrated circuit device according to claim 1, wherein the voltage conversion means includes fine adjustment means for finely adjusting the generated voltage. 3) The semiconductor integrated circuit device according to claim 1 or 2, wherein the input/output circuit is comprised of elements having a higher withstand voltage than elements constituting the internal circuit.