JPH04205798A - Row decoder circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the leakage of a word line driving signal from occurring by simultaneously separating a word line driving signal when a faulty decoder is separated at the time of laser trimming. CONSTITUTION:The faulty row decoder is replaced with a spare row decoder by blowing a fuse 4 at the time of laser trimming. At the beginning of a cycle, signals (xi), (xj), and (xk) obtained by predecoding a row address are 'L', so that potential at a node A is 'H'. Since the fuse 4 is blown when a next row address is fetched and a predecoding signal is generated, the potential at the node A is still 'H' and potential at a node B is 'L' whether the (xi), the (xj), and the (xk) are 'H' or 'L'. Therefore, a transistor 12 is turned off and the leakage of the word line driving signal RX through transistors 9 and 10 is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a row decoder circuit for a semiconductor memory device.

[Conventional technology]

FIG. 2 is a circuit diagram of a row decoder circuit of a conventional semiconductor memory device.
), (9), (10) are n-type transistors, (4) is L
Fuse for T (laser trimming), (5), (6)
is a P-type transistor, (7) is an inverter, (lυ is a word line, X11XLxh is a signal obtained by predecoding the row address, and Rx is a word line drive signal.

The following operation will be explained. First, a case will be described in which the fuse (4) is not blown during LT. At the beginning of the cycle, xi, xj.

Since the xh times signal is Low, the potential of the node A is the old gh. Next, the row address is taken in and a predecode signal is generated. When both the xi and xLxh signals become old gh, point a becomes Low and the decoder is selected. At this point, the potential of node B is Vcc, and the potential of node C is Vc.
c-V+h (V+h is the threshold value of transistor (8)). When Rx is generated (the level of Rx is Vcc + V)
10hm (V0hm is the threshold value of the transfer gate of the memory cell) or more], and the potential of the node C rises to Vcc+α due to the coupling with the transistor (9). However, since the potential of node B is V'c'c, the transistor (
8) remains off. Therefore, the potential of node C remains at Vcc+α, and the word line (11) has Rx
The potential of is transmitted as is, and the voltage is increased to more than Vcc+V+hm.

A case will be described in which the fuse (4) is blown during the next LT. At the beginning of the cycle, Xl, xj, xh are L
OW, the potential of node A is High. Next, the row address is taken in and a predecode signal is generated. Here, fuse (4) is blown, so xi
The potential of the node A remains the old gh, regardless of whether the old gh of lxjSxh is Low or not.

Therefore, transistor (9) is off, transistor α0)
is turned on, and the word line is discharged to the GND level.

[Problem to be solved by the invention]

Since the row decoder circuit of a conventional semiconductor memory device is configured as described above, for example, if there is a contact failure between the diffusion layer of the transistor (8) and the AI of the node C in a certain row decoder, the Blow fuse (4), disconnect this row decoder, and replace it with a spare row coder. However, since node C is floating,
When the word line drive signal (Rx) is generated, the potential of the node C rises due to the coupling capacitance and the transistor (9
) turns on. Further, since the fuse (4) is blown, the potential of the node A is the old gh, and the transistor α0) is also turned on. Therefore, Rx or transistor (
There were problems such as leakage to GND through α0) and α0).

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a row decoder circuit that does not cause Rx leakage when LT is used.

[Means to solve the problem]

In the row decoder circuit according to the present invention, when a defective row decoder is disconnected during LT, the word line drive signal is also disconnected.

[Effect]

In the row decoder circuit according to the present invention, when the row decoder circuit is disconnected during LT, the word line drive signal is also disconnected, thereby eliminating leakage of Rx.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram of a row decoder circuit showing an embodiment of the present invention.
9), α0), 0 is n-type transistor, (4) is LT
fuses, (5) and (6) are P-type transistors, (7
) is an inverter, aυ is a word line, xilxjSxh is a signal obtained by predecoding a row address, and Rx is a word line drive signal.

Next, in the row decoder circuit according to the present invention, the transistor (8
The operation when there is a contact failure between the diffusion layer of ) and the AI of node C will be explained. The fuse (4) of this defective row decoder is blown during LT and is replaced with a spare row decoder. At the beginning of the cycle, xi, xjS
Since xh is Low, the potential of node A is High. A predecode signal is generated from which the next row address is taken. Here, since the fuse (4) is blown, the potential of node A remains the old gh regardless of the old ghSLow of X11xj, xh, and the potential of node B
The potential of is Low. Therefore, transistor 02 is turned off, and no leaf occurs in Rx through transistors (9), 00).

In addition, as shown in FIG. 3, if a fuse α3 is placed in place of the transistor 07J in FIG. The same effect as in the example can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate the stagnation of Rx in the row decoder that is separated during LT.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the row decoder circuit according to the present invention, FIG. 2 is a circuit diagram of a conventional row decoder circuit, and FIG. 3 is a circuit diagram of another embodiment of the row decoder circuit according to the present invention. It is a diagram. In the figure, (1), (2), (3), (8), (9)
, α0), (12 is n-type transistor, (4) is LT fuse, (5), (6) is P-type transistor, (7)
is the inverter, αυ is the word line, αa is the fuse, xi
lxj, xh are signals obtained by predecoding the row address, R
x is a word line drive signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A word line drive signal is connected to an input part, a first transistor is connected in series to the first transistor for driving the word line, and the word line is discharged to GND potential when the word line is not selected. 2nd to
In a row decoder circuit of a semiconductor memory device, which includes a transistor and a third transistor whose gate is supplied with a power supply voltage and whose output is connected to the gate of the first transistor, the row decoder circuit is determined to be defective during laser trimming and is cut. 1. A row decoder circuit for a semiconductor memory device, characterized in that a row decoder circuit for a semiconductor memory device is provided with means for simultaneously cutting a word line drive signal.