JPH04205063A - Logical simulation method - Google Patents

Abstract

PURPOSE:To realize high speed simulation processing by referencing how the intersignal line processing is done, and postponing the processing of memory elements. CONSTITUTION:Allocation of registration destinations of event is done by identifying what types of event processing are carried out for the destinations of connecting generated signals using a type of connecting table, and event information is registered in an event buffer. A selected even buffer is treated by the corresponding event processing section for connected destination event processing, and to connected destinations where event occurs, event registration destination buffers are allocated. When it is detected that an event buffer allocated becomes empty, input data processing is carried out for an input pattern to be taken at the next time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a logic simulation method suitable for use in an event-driven logic simulator that verifies descriptions at a behavioral level or a structural level.

(Prior Art) Simulation is a common method for verifying descriptions at the behavioral level or structural level. There has been no research to confirm the validity of the description without simulation, but there is no practical use of it. The simulation methods include the compilation method and the event method.The compilation method is a method that converts a circuit into instruction code for a certain machine and directly executes it.

Although it has the advantage of fast execution speed, it is difficult to simulate with consideration of delay, and there are also limits to the range that can be handled. In contrast, the event-driven method represents a circuit in a table format and simulates it without tracing it.

An event-based logic simulator uses a facility table that contains information such as the type and bit width of signal lines, a connection table that shows connection relationships, a calculation table that contains calculation information for processing between signal lines, and information about each signal line. Processing was carried out using a value table that was available. However, if the processing procedure is not leveled by the logical model or compiler, registers and
If processes related to storage elements such as latches are not performed after events (changes in value) other than the storage elements have stabilized, the events will occur multiple times on the same signal line at the same time, causing malfunctions of the storage elements.

When performing processing related to such a memory element, if it is a memory element process while processing information in the calculation table, the process is interrupted, and after events other than the memory element have stabilized,
The memory elements were once again processed.

(Problem to be Solved by the Invention) As described above, in the conventional method, it is necessary to check whether or not the processing is for a storage element during arithmetic processing.
There was an inconvenience that processing of the calculation table before checking was wasted.

This invention was made in view of the above circumstances, and includes information on whether processing between signal lines is performed (register processing, latch processing, gate processing, etc.) in the connection table used in logic simulation. The purpose of the present invention is to provide a logic simulation method that increases the speed of simulation processing by postponing element processing and by referring to this.

[Structure of the Invention] (Means for Solving the Problems) The logic simulation method of the present invention is a logic simulator that verifies a logic model without leveling by simulation. Execution processing is performed by tracing a connection table containing information, an operation table containing information for performing arithmetic processing of connection destination signals, and a value table possessed by the signal line, and the processing contents of the connection destination are stored in the memory element in the connection table. It is characterized in that the process for the storage element is performed last by adding information that identifies whether or not the data is stored, and by referring to this information.

(Function) With the above configuration, refer to the information on the processing between signal lines (register processing, latch processing, gate processing, etc.) in the connection table used in logic simulation. By deferring the processing of the memory element, it is possible to speed up the simulation processing.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, reference numeral 1 is a facility table, which corresponds to the signal line A indicated by nine frames in the figure, and has pointers to three types of connection tables. Reference numeral 2 is a gate connection table, which has an operation table pointer for gate processing to which the signal line A is connected. Reference numeral 3 is a latch connection table, which has an arithmetic table pointer for latch processing that is a connection destination to a signal line. Reference numeral 4 is a register connection table, which has an arithmetic table pointer for register processing to which the signal line A is connected.

Reference numerals 5 to 8 are arithmetic tables, which are information for performing arithmetic processing corresponding to registers, latches, and gate circuits.

In the figure, nine frames are circuit models, which correspond to the respective tables shown in 1 to 8 above.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

In the figure, reference numeral 11 is a step for processing input data, in which each signal value corresponding to the input pattern of test data is updated in the value table by one time.

Reference numeral 12 is a step for allocating events, in which event (change in value) information generated by input data processing, gate event processing, etc. is classified according to the type of connection table. Reference numerals 13 to 15 are steps for registering an event buffer, and event information is registered in the buffer specified in step 12. Reference numeral 16 is a step for executing buffer selection, and if event information is registered in codes 13 to 15, select the buffers to perform event processing in the order of gate, latch, and register buffers, and select all buffers. If no event information is registered in the buffer, the process returns to step 11. Code 17-1
9 is a step for executing event processing, in which event processing for the buffer selected in step 16 is performed using each table for facility, connection, and calculation, and when an event occurs at the connection destination, the value table is This is for updating.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. Functional simulation processing will be described in the case where a circuit model shown in nine boxes as shown in FIG. 1 is provided with information regarding circuit processing contents for connection tables other than the settlement table in the form of Tables 1 to 8 and a value table.

First, since the value of each signal line in the simulation is given by the human cover turn in the test data, the input process shown in step 11 in Fig. 2 updates the value of the input line for one time and the event ( Check for occurrence of signal change). In step 12, for the signal in which the event has occurred, the type of event processing to which the event is connected is identified by the type of the connection table, and the event information is registered in the event buffer. This distribution of event registration destinations is because it is difficult to level sort the logical model, so it is necessary to change the processing order depending on the content of the event processing. (Steps 13 to 15) In step 16, the processing order is determined based on the type of processing. Through this selection process, latch processing is performed after the gate system signal line event has stabilized, and register processing is performed. If so, perform this after the gate and latch signal line events have stabilized. In this way, the storage element performs the leveling operation of the model circuit within the same time processing.

The selected event buffer is subjected to connection destination event processing by the corresponding event processing section, and for those in which an event has occurred, in step 12, the event registration destination buffer is distributed.

As described above, steps 12 to 19 are processed in step 13.
Repeat until all event buffers indicated by 15 are empty. Step 16: The event buffer is empty.
In this case, input data processing for the input pattern at the next time is performed. The simulation ends when input data processing is completed for all input patterns of test data.

C. Effects of the Invention As explained above, the present invention includes information on the type of processing between signal lines (register processing, latch processing, gate processing, etc.) in the connection table used in logic simulation. By adding and referring to this, the processing of the memory element can be postponed, thereby speeding up the simulation processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the embodiment of the present invention. 1... Facility table 2.3.4... Connection table 5.6.7.8... Settlement table

Claims (1)

[Claims] In a logic simulator that verifies unleveled logic models through simulation, there is a facility table that has information about the signal line itself, a connection table that has connection information, and a calculation table that has information for performing arithmetic processing on connected signals. In addition, execution processing is performed by following the value table of the signal line, information is added to the connection table to identify whether or not the processing content of the connected destination is a storage element, and by referring to this information, the execution processing is performed by following the value table of the signal line. A logical simulation method that is characterized by performing the processing for the last step.