JPH04204632A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce the area occupied by gate lines to a half and to increase the opening rate of picture elements by providing scanning lines (gate lines) by every other one scanning row and connecting the respective gate lines to the transistors of the respective picture elements corresponding to two lines of the scanning rows of the odd number place and the even number place adjacent to each other. CONSTITUTION:The n channel TFT 12 provided at the picture element corresponding to the scanning row of the odd number place consists of an active layer 13a consisting of 1st poly-Si and a gate insulating film formed thereon as well as a gate 14a consisting of low-resistance 2nd poly-Si. The p channel TFT 12b provided at the picture element corresponding to the scanning row of the even number place consists of an active layer 13b consisting of the 1st poly-Si, a gate insulating film formed thereon, and a gate 14b consisting of the low--resistance 2nd poly-Si. Such display picture elements are arranged in a matrix form at 480 picture elements in a horizontal direction and 240 picture elements in a vertical direction. The signal lines 18 are arrayed by 480 pieces and the gate lines 17 by 120 pieces.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to an active matrix liquid crystal display device in which a switching transistor is provided for each display pixel.

(Prior Art) Recently, in order to increase the speed and quality of display in liquid crystal display devices, the active matrix type, in which a switching transistor is provided for each display pixel, has become mainstream. , amorphous silicon (a-3t), or polycrystalline silicon (poly
-3i) and other thin film transistors (T
PT) is commonly used.

Among these TFTs, the a-3i TFT can be formed over a large area on an inexpensive glass substrate, so it can be said to be suitable for office automation displays and wall-mounted large-sized liquid crystal display devices such as televisions. On the other hand, poly-8i TFTs have carrier (field effect electron) mobility of several tens to 2,000 m2/V·see, and have a fast response and are capable of driving liquid crystal display pixels even if their size is small. Because it is possible to integrate peripheral drive circuits on the same substrate, it is suitable for liquid crystal display devices that require small size and high definition, such as projection televisions and video camera viewfinders.

FIG. 5 is a top view partially showing a display pixel area in a conventional liquid crystal display device using poly-8i TFTs.

In this figure, it is assumed that the dotted area, the diagonal line area, and the white area are laminated from the bottom in this order, and the n-channel TPT
Show about.

As shown in the figure, TFTI consists of an active layer 2 made of a first poly-3i and a gate insulating film (
Not shown. ), and a second p of low resistance.

It consists of a gate (electrode) 3 of 1y-3t.

The portions of the active layer 2 on both sides of the gate 3 are implanted with P (phosphorus), which is an n-type dopant, and have a low resistance.
They are a source (or drain) 4 and a drain (or source) 5 of I. The drain 5 is connected to a signal line 6 made of AI, and the source 4 is connected to a storage capacitor 7 and a pixel electrode 8 made of ITo. Further, the gate 3 is integrated with two scanning lines (gate lines) made of the second poly-3t. Furthermore, the storage capacitor 7 is formed by the base layer 10 or the first poly-3
A storage capacitor line 11 made of a second poly-3i is integrated with the active layer 2 made of poly-3i, and is formed on the upper side with an insulating film (not shown) formed at the same time as the gate insulating film described above. It is formed.

(Problem to be Solved by the Invention) In the conventional liquid crystal display device configured as described above, when the display area is made small and high definition and the pixel pitch is made small, the aperture ratio becomes small for the following reasons. This caused the problem that the display screen became dark and the display became rough.

In other words, even if the pixel pitch is made smaller, the size of the TFTI and the width of the signal line 6 and the gate line 9 cannot be made below a certain value due to the limitations of the TPT formation process, so the aperture ratio will become smaller. . Further, the configuration is such that a change in the potential of the signal line 6 or the gate line 9 changes the potential of the pixel through the liquid crystal capacitance that exists between the signal line 6 and the pixel electrode 8 and between the gate line and the pixel electrode 8. Therefore, the distance between the signal line 6 and the gate line 9 and the pixel electrode 8 cannot be made very narrow.

Furthermore, in order to keep the amount of change in pixel potential small even if the interval is narrowed, it is sufficient to increase the storage capacitor 7, or else this would not meet the purpose of increasing the aperture ratio.

The present invention has been made to solve these problems, and an object of the present invention is to provide a liquid crystal display device with a large aperture ratio, a bright display, and a high quality display.

[Structure of the Invention] (Secret Means for Solving the Problem) The liquid crystal display device of the present invention is an active matrix type liquid crystal display device in which a switching transistor is provided for each display pixel. Corresponding pixels are provided with n-channel or n-channel transistors, respectively, and pixels corresponding to even-numbered scan columns are provided with p-channel or n-channel transistors opposite to the pixels corresponding to the odd-numbered scan columns, respectively. , and the gate electrodes of the transistors provided in the pixels corresponding to the two adjacent odd-numbered and even-numbered scanning columns are each connected to one scanning line.

(Function) In the liquid crystal display device of the present invention, the scanning line (gate line)
Each gate line is connected to the transistor of each pixel corresponding to two adjacent odd-numbered and even-numbered scan columns, and is configured to operate these transistors respectively. It is configured. Therefore, the number of gate lines is halved, and the area occupied by them is also halved, so that the opening and mesh size can be greatly increased.

Furthermore, in the liquid crystal display device of the present invention, each pixel corresponding to an odd-numbered scanning column has an n channel or an n channel.
A channel transistor is provided, and each pixel corresponding to an even-numbered scanning column is provided with a p-channel or n-channel transistor opposite to the odd-numbered pixel, so it is driven in the following manner. .

That is, for example, to select a pixel in an odd-numbered scan column in which an n-channel transistor is provided, a positive potential pulse is applied to the gate line, and a pixel in an even-numbered scan column in which a p-channel transistor is provided is selected. To do this, apply a negative potential pulse to the gate line. During the non-selection period, a voltage such as OV that turns off both the n-channel and p-channel transistors may be applied to the gate line.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a top view partially showing a display pixel area of a liquid crystal display device according to an embodiment of the present invention.

As shown in the figure, the n-channel TPT 12a provided in the pixel corresponding to the odd-numbered scan column is connected to the first pony-
3i, a gate insulating film (not shown) formed thereon, and a low resistance second pol.
The gate 14a is formed by y-3t. The portions of the active layer 13a on both sides of the gate 14a are implanted with P (phosphorus), which is an n-type dopant, and have a low resistance, forming the TFT 12a, the source 15a, and the drain 16a, respectively.

Furthermore, the p-channel TFT 12b provided in the pixel corresponding to the even-numbered scan column is composed of an active layer 13b made of the first poly-9J, a gate insulating film (not shown) formed thereon, and a low-resistance active layer 13b. A gate 14b formed by the second poly-Sj is formed.

The portions of the active layer 13b on both sides of the gate 14b are implanted with B (boron), which is a p-type dopant, and have a low resistance.
It becomes.

Gates 14a of these TFTs 12a and 12b,
14b is integrated with one gate line 17 made of second poly-8jl:. Also, the drain 16a
, 16b are each connected to a signal line 18 made of Al, and the sources 15a, 15b are respectively connected to separate storage capacitors 19a, 19b and a pixel electrode 20 made of ITO.
a, 20b. Furthermore, storage capacity 19a,
19b, each base layer 21a, 21b is the first p
It is integrated with the active layers 13a and 13b made of oly-3i, and has a second p
Storage capacitor lines 22a and 22b made of oly-St are formed, respectively.

Further, in the liquid crystal display area of the liquid crystal display device of the embodiment, such display pixels are arranged in a matrix of 480 pixels in the horizontal direction and 240 pixels in the vertical direction, and the signal line 1
8 and 120 gate lines 17 are arranged. Further, around the display area (not shown), peripheral circuits for driving pixels, that is, a signal line driver and a gate line driver, are formed simultaneously on the same substrate as the display area using poly-SiT F T.

Next, the n-channel and p-channel T of each pixel described above
An example of current-voltage characteristics of PT is shown in FIG.

Note that the threshold voltages are 9v and 11v for n and p channels, respectively.
v, which is set higher than normal.

A liquid crystal display device configured in this manner is manufactured, for example, by the following process.

That is, first, on a quartz substrate, a first poly-3t film, which will become the active layers 13a and 13b of the TFTs 12a and 12b and the base layers 21a and 21b of the storage capacitors 19a and 19b, is placed.
It is formed by a CVD method or the like and etched (patterned) into a predetermined pattern. Next, in order to control the threshold voltage during operation of the TFTs 12a and 12b, B (boron) is implanted into the active layer 13a and P (phosphorus) is implanted into the active layer 13b by ion implantation.

Note that, as the dopant for controlling the threshold voltage, instead of implanting different types of dopants into the respective active layers 13a and 13b as described above, the same type of dopant can be implanted with different doping amounts.

Next, an oxide film is formed on the active layers 13g and 13b by thermal oxidation to serve as a gate insulating film. At this time, the base layer 21a of the storage capacitors 19a and 19b.

An oxide film is also formed on the storage capacitor 19a119
This becomes the insulating film b. Next, a second poly-S+ film having low resistance is formed thereon, and the gate 14a114b, gate line 17, and storage capacitor line 22a122b are patterned, respectively. Here, the second pol with low resistance
Similar to the first poly-3t film, the y-3t film has a CV
It is formed by forming a film using the D method or the like and then diffusing P (phosphorus) over the entire surface, or by forming a film while doping P (phosphorus) from the beginning using the CVD method. Then, T.F.
P (phosphorus) is implanted into the portions of T12a that will become the source 15a and drain 16a, respectively, by ion implantation. Furthermore, B (boron) is implanted into the portions that will become the source 15b and drain 16b of the TFT 12b, respectively, by ion implantation. As a result, the TPT12a becomes an n-channel, and the TPT12a becomes an n-channel.
FT12b becomes a p-channel. Next, an SiO2 film is formed on the entire surface by CVD, contact holes are formed by etching, and then an AI film that will become the signal line 18 and an ITO film that will become the pixel electrodes 20a and 20b are formed and patterned.

Next, a method of driving the display pixels of the liquid crystal display device of the example manufactured in this manner will be explained.

FIG. 3 is a block diagram showing a gate line driver and a portion of the pixel area (for four scan columns) among the peripheral drive circuits formed simultaneously on the same substrate as the display pixels.

As shown in this figure, for 240 scan columns, 240
There are stages of shift registers 23, and each two stages are connected to one gate line 17 via one level setting circuit 24. The level setting circuit 24 includes two p-channel TFs.
T25a, 25b and two n-channel TFTs 26a, 2
It consists of 6b. Two n-channel TFTs 26a
, 26b are each connected to a positive potential (
+1, for example +20V) and a negative potential (-V1, for example -20V), and each source or drain is connected to the gate line 17, respectively. two ps
Channel TFTs 25a and 25b are connected in series, and the drain of one TFT 25a is at an intermediate potential (for example, O
V), and the source of the other TFT 25b is connected to the gate line 17.

FIG. 4 is a timing chart when the gate line driver shown in FIG. 3 is operated, and shows a two-field period corresponding to four scan columns (four stages of shift registers).

As shown in the figure, the shift registers at each stage sequentially output pulses during the initial IH period, and the level setting circuit outputs pulses to the first gate line (corresponding to the first and second scan columns) during the first H period. A positive voltage pulse is applied to the first gate line during the second H period, and a negative voltage pulse is applied to the second gate line (third and fourth lines during the third H period).
The configuration is such that a positive voltage pulse is applied to the second gate line (corresponding to the scan column) and a negative voltage pulse is applied to the second gate line during the 4th H period. The TPT of the odd-numbered pixels in the first and third scanning columns is n-channel, and the TPT of the even-numbered pixels in the second scanning column is n-channel.
．． Since the TPT of the pixel in the fourth scan column is p-channel,
Pixels in the first scan column in the first H period, pixels in the second scan column in the second H period, pixels in the third scan column in the third H period, pixels in the third scan column in the fourth H period,
During the H period, pixels in the fourth scan column are selected.

Note that if the potentials of +V and -v2 are the same for both, and if a driving method is used in which, for example, the odd field is a positive potential and the even field is a negative potential, the driver configuration is exactly the same, and interlaced driving is also possible. .

In this way, in the liquid crystal display device of the embodiment, the number of gate lines can be reduced to half of the conventional one, so the area occupied by the gate lines can be halved and the aperture ratio of the pixel can be increased. For example, in the conventional liquid crystal display device shown in FIG. 5, the aperture ratio was approximately 36%, but in this embodiment, the aperture ratio can be increased to 45%.

In addition, in the above example, TPT using poly-3t
Although the active matrix type liquid crystal display device has been described, the present invention is not limited to such an embodiment, and the a-3i
A similar effect can be achieved with a TPT active matrix type liquid crystal display device using
It is also effective to use single crystal St (c-St).

Furthermore, the gate line driver circuit is not limited to the above embodiment.

Furthermore, in the embodiment, the threshold voltage of the TPT of the pixel and the potential applied to the gate line were set higher than usual for the n-channel and the p-channel for the following reason.

That is, the signal potential that generally determines the voltage applied to the liquid crystal is usually inverted every certain period (for example, every field period). Therefore, the gate-source (or gate-drain) threshold voltage applied to the TPT of the pixel is not a constant value. Therefore, if the gate line potential during the non-selection period is set to Ov as in the above embodiment, a positive voltage with the gate-source threshold voltage of the n-channel TFT (or the gate-source threshold voltage of the p-channel TFT) is applied during the non-selection period. The voltage may become a certain negative voltage), and there is a risk that the off-state current of the TPT will increase. Therefore, the threshold voltage of the TPT of the pixel is set higher than usual.

[Effects of the Invention] As is clear from the above description, according to the present invention, the number of gate lines can be reduced to half that of the conventional one, so the area occupied by the gate lines is halved, which has the effect of increasing the aperture ratio of the pixel. There is.

By increasing the aperture ratio, the brightness of the display screen can be improved. For example, the screen brightness of a projection television manufactured using the liquid crystal display device of the present invention has increased from 200 t-L to 250 ft-L.
rise to Further, if the screen brightness is kept as usual, the power used by the light source can be reduced, the power consumption can be reduced, and the life of the light source can be extended.

Furthermore, the effects of the present invention are not limited to the above-mentioned points, but also have the effect that, by reducing the number of gate lines by half, the probability of gate line disconnection occurring during manufacturing is reduced, and therefore manufacturing yield is increased.

[Brief explanation of the drawing]

FIG. 1 is a top view of a display pixel area of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a graph showing the current-voltage characteristics of TPT of a pixel in the embodiment of FIG. 1, and FIG. teeth,
FIG. 4 is a block diagram showing the gate line driver and part of the pixel area in the drive circuit of the liquid crystal display device of the embodiment, and FIG. 4 is a timing chart when the gate line driver shown in FIG. 3 is operated. 1 is a top view of a display area of a conventional liquid crystal display device. 12a, 12b-=-=TFT 13a, 13b...Active layer 14a, 14b...Gate 15a, 15b-Source 16a, 16b...Drain 17...・・・・・・・・・・・・・・・Gate line 18・・・・・・・・・・・・・・・・・・
Signal lines 19a, 19b... Storage capacitors 20a, 20b... Pixel electrodes 21a, 21b... Base layers 22a, 22b... Storage capacitor line 23... ...
・・・・・・・・・・・・・・・Shift register 24
・・・・・・・・・・・・・・・・・・Level setting circuit specification tvLffVG (V) Fig. 2 Fig. 3 - IH initial interval 11 Fig. 4, -, - 5-1.

Claims (1)

[Claims] (1) In an active matrix liquid crystal display device in which a switching transistor is provided for each display pixel, an n-channel or p-channel transistor is provided in each pixel corresponding to an odd-numbered scanning column, and a switching transistor is provided in each pixel corresponding to an odd-numbered scanning column. P-channel or n-channel transistors opposite to the pixels corresponding to the odd-numbered scanning columns are provided in pixels corresponding to the columns, and pixels corresponding to the two adjacent odd-numbered and even-numbered scanning columns. The gate electrodes of the transistors provided in
A liquid crystal display device characterized in that it is connected to the scanning line of a book.