JPH04199924A - Delay correction method for plural channels - Google Patents

Abstract

PURPOSE:To eliminate the unnecessary use of memories by setting respective memories of channels to be one common memory and controlling accesses from respective correction circuits to the memory by means of a control signal from an access allocation circuit lest they collide with each other by means of time division. CONSTITUTION:The memory access allocation circuit 400 is provided for correcting delay by sharing the common memory 200 with respective channels and respective delay correction circuits 101-103 time-divisionally use the common memory 200 by the control. The memory access allocation circuit 400 outputs enable signals E1-E3 allowing the access of the respective delay correction circuits 101-103 for the common memory 200 and a control signal R/W designating reading (R)/writing (W) within the allowable time to the respective delay correction circuits 101-103 for control. Thus, the time difference of the plural channels can be corrected by using one memory 200 in common. Thus, the unnecessary use of the memories is eliminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-channel delay correction method, and is particularly suitable for correcting time differences between digital signals transmitted and received using a plurality of channels in a digital communication system. This invention relates to a delay correction method.

[Prior Art] In a digital communication system such as an I5DN digital switching network, a separate transmission channel is used for each channel signal, for example, to transmit stereo sound. At this time, it is not known which transmission route each channel will take to reach the receiving point, and the signals are normally sent along different routes. In this case, at the receiving point, the time difference between the received channel signals will be different from the original stereo sound, so it is necessary to correct the time difference between the channels.

A conventional example of a delay correction method for this purpose is shown in FIG. The figure shows correction between three channels, and the delay correction circuits 110 to 130 for each channel operate in synchronization with the clock CL and the octet clock (one clock for every eight clocks CL) QC. Input data Di from each channel. 1 to D1n3 and detect a frame synchronization signal indicating the beginning of the frame. Then, by mutually taking in the synchronization signals of other channels via the communication line 300, it is determined how much delay \fung is required for the own channel. At the same time, each of the seven delay correction circuits 110-130 receives input data D:n1-Di. 3 to memories 210 to 23 provided for each channel.
Output and write write command WR and address AD to 0. Then, the read command RD is output at a timing delayed by the above delay amount, and the data read from the memory is output data D. They are output as utl to Dout3, respectively.

[Problems to be Solved by the Invention] The conventional method described above has a problem in that the circuit becomes large because a buffer memory is arranged for each channel. (Recently, memory has become large in capacity, but each channel uses only that amount (some of it is wasted (
Become.

[Means for Solving the Problem] In order to achieve the above object, the present invention provides a correction circuit corresponding to input data whose input data is a plurality of pieces of digital data synchronized in units of bits, and the correction circuit. A shared memory to which an area for each correction circuit is allocated for common use, and an access assignment for outputting a control signal to allow each of the correction circuits to access the shared memory without conflict. In addition to providing a circuit,
Each of the above correction circuits detects a frame synchronization signal of input data to the circuit, communicates the detection signal to another correction circuit, and calculates the time difference between the frame synchronization signals of each input data obtained by the communication. Detection is performed, and then in each correction circuit, the input data is written to the corresponding area of the shared memory according to the control signal, and then read out, so that the input data is determined as permissible under the control signal. By providing a possible time difference delay in units of time, and further correcting the residual time difference that cannot be corrected by the delay in units of data bits, the frame synchronization signals of each input data are output from each correction circuit at the same time. I made it so that it would be done.

[Operation] The method of detecting the time difference between each channel and correcting this time difference using a memory is basically the same as the conventional method. In the present invention, since the memory of each channel is a single memory, accesses to it from each correction circuit can be performed in a time-sharing manner to avoid collisions. Control for this is performed using control signals from the access allocation circuit, and by sharing the memory, unnecessary memory usage is eliminated and economy is achieved.

[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of a delay correction system to which the method of the present invention is applied, and is a three-channel case as in FIG. 2. In this embodiment, delay correction is performed by sharing the shared memory 200 with each channel. For this purpose, a memory access allocation circuit 400 is provided, and under the control of the memory access allocation circuit 400, each delay correction circuit 101 to 103 uses the shared memory 200 in a time-sharing manner. use. Memory access allocation circuit 4
00 indicates each delay correction circuit 101 to 10 for the above control.
Enable signal El-E3 that permits access to the shared memory 200 of No. 3 and readout within the permitted time (R)
/A brake signal R/W specifying write (W) is output to each delay correction circuit 101-103.

FIG. 3 is a block diagram showing an example of the configuration of one of the delay correction circuits 101 to 103 (all having the same configuration). In this circuit, the frame synchronization detection circuit 700 detects the leading position (synchronization signal) of the input data D1° and generates the detection signal FDo,,lt.
Output. The delay amount calculation circuit 800 receives the detection signal F.
Detected by DO-t and other delay correction circuits and connected to the communication line 300
The amount of delay to be given to the input data D in is calculated based on the detection signal FDII+ sent via the input data D in. In this embodiment, data 8 is stored in the shared memory 200.
Assume that a bit is one word, and one address is accessed one word at a time. The above delay amount is a word + b bit (a: word delay L b
=Bit delay 11 Both are integers, a≧0.8>b≧0
) shall be calculated as a quantity of the form.

FIG. 4 shows the configuration of the data control circuit 500 in FIG. 3.

This circuit transfers input data to the shared memory and retrieves the data from the shared memory as output data. First, input data D:n (real data) is converted to parallel data by the S/P converter 501. Store in register 502. This stored data (L word) is passed through the bidirectional buffer 503 when the enable signal E is turned on, the control signal R/W specifies writing, and an address is specified from the address control circuit 600, which will be described later. and written to the specified address in the shared memory 200. Further, when the enable signal E is on and the control signal R/W instructs reading, one word of data at the address output from the address control circuit 600 is read from the shared memory 200 and sent to the register 500 via the bidirectional buffer 503.
04. This data is converted into real data by a P/S converter 505, and is given a delay equal to the number of bits corresponding to the bit delay iLb of the required delay amount calculated previously by a selector 506, and the output data D out is output as

FIG. 5 is a block diagram showing the configuration of the address control circuit 600 of FIG. 3, in which the data control circuit 500 performs control to give an address to data when accessing the shared memory 200. Further, FIG. 6 shows the data structure of the shared memory 200, and shows the data structure of the shared memory 200.
The channels corresponding to each channel 3 are called channels 1 to 3, and an area for each channel is reserved in the shared memory 200. Offset the start address of each area from OF81 to 0FS3, and set the size of each area to AR1-A.
R3, the register 601 in FIG. 5 has the corresponding size AR, and the register 604 has the corresponding offset O.
FS is stored.

The operation of address control circuit 600 is as follows. A counter 603 counts the octet clock OC. The count value X is compared with the channel size AR stored in the register 601 by a comparator 602, and X=A
When it becomes R, a clear signal is output and the counter 60
3 is reset and returns to x=0. Therefore, the counter 60
Offset O of register 604 to count value X of 3 outputs
The address xW obtained by adding FS by the adder 605 specifies the area in the shared memory allocated to the channel when clock oC is counted one after another, and when enable signal E is on (this is clock OC1 (given from memory access allocation circuit 400 so as not to overlap with other channels), is sent to shared memory 200 via selector 610 and three-state buffer 611. On the other hand, the subtracter 606 uses the word delay calculated by the delay amount calculation circuit 800 (FIG. 3) from the counter output X!
Subtract a, and if the result is positive or 0, “l”
, if it is negative, outputs a signal C which becomes "0". Subtractor 606
The output of is sent to the selector 608, and added to the value AR of the register 601 by the adder 607 and sent to the selector 608.

The selector 608 is the subtracter 80B when the signal C is “L”.
When the output is "0", the output of the adder 607 is selected. The counter output
="1") indicates that this output address is in the same area and is the relative address of a word written a octet clock before the word written to shared memory 200 at address XW. Furthermore, when the output of the subtractor 606 is negative (C="0"), since writing to the shared memory is performed cyclically in each area, the sum of the subtracter output and the size AR of the area is The output of device 607 again points to a word written a octet clock before the word written to address xW. However, it is assumed that the size of each area is set so that the word delay 1a is always smaller than the area size AR. Therefore, the selector 608 always indicates the relative address based on the offset of the word written in the area a octet clock before the word at address xW, so the adder 609 adds the offset OFS to this. Address XR is always the address of data written a word before the word at address Selector 610. It is applied to the shared memory 200 via the three-state buffer 611.

Therefore, this access control circuit can apply a delay of a word to the data of the channel by writing one word to address xW in a certain octet clock cycle and reading the word at address XR written a word before. .

The configuration of the embodiment shown in FIG. 1 and the operation of each circuit have been described above. Next, the overall operation of this embodiment will be explained using the time chart shown in FIG. 7. First, the enable signals E1 to E3 output from the memory access allocation circuit 400 in FIG.
As shown in the figure, this is a signal that divides one cycle of the octet clock OC into three equal parts and turns on (high level, the same applies hereafter) in sequence.When this signal turns on exclusively, each delay correction circuit 10
1 to 103 are eliminated. During one ON period of each enable signal, the control signal R/W from the memory access allocation circuit 400 is
Write Wl and read R are turned on once each. Therefore, each of the delay correction circuits 101 to 103 is controlled to write (W) and read (R) to the shared memory 200 once during one octet clock.

Next, it is assumed that the input data Di, 1 to D +, 3 of each channel are inputted with a time lag as shown in part in FIG. Here, 1 box of input data indicates 1 bit, and the number o1 ±1, .9 in the input data is a number indicating the relative bit position when the number at the beginning of the frame (frame synchronization signal) is O. be. In the example of FIG. 7, the input data D,. ■ is input data D: 2 words + 1 from n2
bit (=17 bits) late, input data D:n
It is 7 bits behind 3. The delay amount calculation circuit 800 shown in FIG. 3 takes in the synchronization signals detected in these three channels, and outputs a delay = 0 when its own channel is the most delayed, and a - number when it is not. Outputs the difference with the delayed channel as the delay amount. Therefore, in the case of FIG. 7, the correction circuit 101 has a word delay fit aq
Bit delay Wb is both 0, a=2 in correction circuit 102,
b=i, and in the correction circuit 103, a''-OSb=7 is calculated by the delay amount calculation circuit 800.At this time, in the correction circuit 1O11, that is, the address control circuit of channel l, word delay!a=O. At the same octet clock, write address X in Figure 5
W and read address XR are the same. The shared memory 200 is accessed using an address n-3 for each cycle of the octet clock OC, n-2 for each cycle, and so on. It goes without saying that these addresses are within the area of channel 1 in FIG. on the other hand,
In the correction circuit 102, that is, the access control circuit of channel 2, although the word delay amount a=2, the read address XR is always 2 smaller than the write address xw at the same octet clock. Address AD2 in FIG. 7 indicates this.

Looking at the operation of the data control circuit 500 when addresses are given as described above, we can see that the input data DIol input in the cycle 2 of the octet clock OC in FIG.
5th 8 bits (1 word including frame synchronization signal)
is set from the register 502 in FIG. 4 to the bidirectional buffer 503 (parallel data) at the rising edge of the octet clock cycle (2) immediately thereafter, and is transferred to address n of the shared memory 200 by the enable signal E1 and write signal W of the same cycle (2). written. Then, it is read out immediately by the read signal R immediately after the write and is set in the register 504. This word is read out from the register 504 by the octet clock of the next cycle (■), is converted into serial data by the P/S converter 505, and is converted into serial data at exactly the cycle V
Data J at the time within. Output as utl. Thereafter, a delay of bit delay 1b is performed by the selector 506, but since b=o in channel 1, the output D0utl of channel 1 is in the same phase as J6utl. On the other hand, the 1st to 6th 8 bits = 1 word including the frame synchronization signal input in period I of channel 2 are written to the address m of the shared memory 200 by the write signal W when the enable signal E2 in period 2 is on. written to. This is read out by the address control circuit at read address XR.
is delayed by 2 words, so that the read address XR becomes m in the cycle ■, and this appears as the output J0ut2 of the P/S converter 505 of the data control circuit in the next cycle ■ of the above read. It is. Then, this is delayed by bit delay 1b=1 bit by selector 506 and outputted from channel 2. It becomes ut2.

Thus, the output of channels 1.2. -tll 2 frame synchronization signals are output at the same clock timing. Although channel 3 is not shown in FIG. 7, its operation is exactly the same.

According to this embodiment, for example, when each channel of a multi-channel stereo signal is transmitted through different transmission paths and a time difference occurs, the time difference between the channels can be reliably corrected, and the memory used for this purpose is 1 for
Can be done individually.

FIG. 8 shows an example of the operation of the present invention in a so-called Nork mode, in which data strings of a plurality of channels are combined into one bit stream. In this example, 16 clocks CL are input during one octet period, and 16-bit input data D in is input. This input data D
in consists of two channels of data, one of each channel
It is a pit stream in which words (8 bits) are arranged alternately, and the bits of channel 1 are given relative numbers ±1, ±2, etc. with the frame synchronization signal being 0,
The bits of channel 2 are assigned relative numbers ±1-1±2-1, . . . with the frame synchronization signal set to 0. The system has the configuration shown in FIG. 1 except for the delay correction circuit 103, and the input data D1° is transmitted through the two correction circuits 101,
102, the input data D1゜1 and DIo2 are obtained.

The memory access allocation circuit 400 outputs two complementary enable signals El and E2 to each channel, and also outputs a write signal W1 and a read signal R alternately (eighth
(The control signal R/W is omitted in the figure). Each correction circuit +01.1
02 is an S/P converter 50 of the internal data control circuit in order to take in only one channel data into its own circuit.
1 (FIG. 4) is inputted only when the enable signal E1 or E2 to that channel is on. As a result, the data of channel 1 in the input data D in is taken into the register 502 of the correction circuit 101, and the data of channel 2 is taken into the register 502 of the correction circuit 102.

Also, the frame period detection circuit 700 similarly detects only the frame synchronization signal of the relevant channel. In the example of FIG. 8, since channel 1 is delayed by 27-words+3 bits compared to the data of channel 2, the delay amount calculation circuit 800 of channel 2 outputs word delay 1 a =2. As a result, the output address from each address control circuit of channel L2 is changed to channel 1 as in FIG.
In this case, write W and read R are the same within the same enable signal, and in channel 2, the read address is 2 smaller than that of write. In this way, the data of each channel is written to and read from the shared memory, and then outputted from the P/S converter 505. utl, Jout2. Here, as in the case of Fig. 7, if the bit delay amount of 3 bits is corrected in channel 2, when each channel is arranged alternately, the frame synchronization signal (
Since the number 0.0-) is not received, it is necessary to perform this correction as well. To achieve this, focus is placed on the fact that frame synchronization signal 0 of channel 1 is at the third position of one word in the memory access unit, and channel 1 is delayed by 6 bits so that it comes at the beginning of one word in the access unit. In other words, irrespective of the time difference between the two channels, in channel I, the bit delay amount=6 is applied to the selector 506 of the data control circuit. As a result, channel 2 requires a bit delay of 9 bits, including the 3 bits determined from the time difference between channels.
In the present case, since 1 octet contains 16 bits, as is clear from the figure, the delay increases by 1 word. So if we add a bit delay to channel 2 by 9-8 = 1 bit, the octet clock OC
Bits 0 to 7 of channel 1 are followed by bits 0 to 7' of channel 2, as shown in period (3).

[Effects of the Invention] According to the present invention, the time difference between multiple channels can be corrected by sharing one memory, and the correction device can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a correction system to which the method of the present invention is applied, FIG. 2 is a block diagram showing an example of a conventional correction system, and FIG. 3 is a configuration of the delay correction circuit shown in FIG. 1. The block diagrams shown in Figures 4 and 5 are respectively
FIG. 6 is a block diagram showing the configuration of the data control circuit and address control circuit in FIG. 6. FIG. 7 is an explanatory diagram of the area of the shared memory. FIG. The figure is a time chart showing the operation of a modified example of FIG. 1. 101-103--Delay correction circuit, 200--Shared memory, 300--Connection line, 400--Memory access! 'lThis circuit, 500...Data control circuit, 60
011...Address control circuit.

Claims (2)

[Claims] (1) A correction circuit corresponding to input data, each of which is input data of a plurality of bit-by-bit synchronized digital data;
Outputs a shared memory to which an area for each correction circuit is allocated for common use by the correction circuits, and a control signal so that each of the correction circuits accesses the shared memory without conflict. In addition, each of the correction circuits detects a frame synchronization signal of input data to the circuit, communicates the detection signal to another correction circuit, and detects each input data obtained by the communication. Detecting the time difference between the frame synchronization signals of By providing a possible time difference delay in the time unit allowed under the control signal, and further correcting the residual time difference that cannot be corrected by the delay in units of data bits, the frame synchronization signal of each input data is adjusted. A delay correction method for a plurality of channels, characterized in that outputs are output from each of the correction circuits at the same time. (2) When correcting the residual time difference in each of the correction circuits, the frame synchronization signal of the output data is transmitted at the beginning of one of the periodic time periods in which the control signal allows each correction circuit to access the shared memory. 2. The multi-channel delay correction method according to claim 1, wherein an extra bit delay is provided so that the delay occurs.