JPH04199914A - Variable length-decoding device - Google Patents

Abstract

PURPOSE:To minimize delay by means of a buffer memory by writing variable length-encoding data in a buffer memory part so as to start the reading of variable length-encoding data and permitting the operation of a variable length- decoding part to stop when the buffer memory part is detected to be empty. CONSTITUTION:The buffer memory part 1 which inputs variable length-encoding data and the variable length-decoding part 2 which decodes variable length- encoding data which is read out from the buffer memory part 1 are provided. A control part 3 starts the reading of variable length-encoding data in such a way that variable length-encoding data is written in the buffer memory part 1 and permits the operation of the variable length-decoding part 2 to stop when the buffer memory part 1 is detected to be empty. Therefore, the decoding of a noise component except for variable length-encoding data is prevented and decoding processing simultaneously starts with the reception of variable length-encoding data. Thus, delay time is minimized and the capacity of the buffer memory part 1 becomes small.

Description

[Detailed Description of the Invention] [Summary] Regarding a variable length decoding device that decodes variable length encoded data, the purpose is to minimize the delay caused by a buffer memory, and the variable length decoding device decodes variable length encoded data. The encoding device includes a buffer memory section into which the variable-length encoded data is input, a variable-length decoding section that decodes the variable-length encoded data read from the buffer memory section, and a buffer memory section that inputs the variable-length encoded data. When the variable length encoded data is written, reading of the variable length encoded data is started, and when it is detected that the buffer memory section is empty, the operation of the variable length decoding section is stopped. The controller is configured to include a control section.

[Industrial application field]

The present invention relates to a variable length decoding device that decodes variable length encoded data.

In order to compress and transmit image information, etc., processing such as inter-frame differences and discrete cosine transform is performed, and variable length coding is applied in which short codes are assigned to items with a high probability of occurrence. On the receiving side, the variable length encoded data must be stored in the Hanofa memory and then decoded, and efficient decoding processing is desired.

2. Prior Art] FIG. 5 is an explanatory diagram of a conventional example, in which the encoding unit 41 performs high-efficiency encoding processing such as inter-frame differential encoding of image information, discrete cosine transform, etc. The signal is subjected to variable length encoding in the encoding section 42 and sent out from the transmitting section 43 to the transmission path. On the receiving side, a clock signal is regenerated by the receiving section 44, and this clock signal is converted into a write clock signal WCK.
The buffer memory section 45 along with the variable length encoded data
will be added to and written to.

The variable length decoding section 46 applies a read clock signal RCK to the buffer memory section 45 every time decoding is completed, so that the variable length encoded data read from the buffer memory section 45 is added to the variable length decoding section 46. and decrypted,
The decoded data is applied to the decoding unit 49 and decoded by processing such as inter-frame difference decoding and inverse discrete cosine transform, and is restored to the original image information.

As mentioned above, variable length encoded data is written into the buffer memory section 45 by the write clock signal WCK corresponding to the transmission long signal, and by the read clock signal RCK which corresponds to the internal clock signal of the variable length decoding device. Variable length encoded data is read out from the buffer memory section 45 and processed.

Further, the buffer memory capacity calculation unit 47 calculates the amount of variable length encoded data stored in the buffer memory unit 45 using the write clock signal WCK and read clock signal RCK applied to the buffer memory unit 45. Yes, and when the decoding control unit 4 is notified from the buffer memory capacity calculation unit 47 that a predetermined amount of variable length encoded data has been accumulated in the buffer memory unit 45, it starts the variable length decoding unit 46, It also monitors its status. That is, at the start of reception, since the variable length decoding section 46 is not activated, the readout signal RC is stored in the buffer memory section 45.
K is not added, and the write clock signal WCK from the receiving section 44 upon receiving the variable length encoded data is added to the buffer memory section 45, and the received variable length encoded data is stored in the buffer memory section 45. written. Therefore,
Ba.

In the file memory capacity calculation unit 47, the write clock signal WC
By counting K, it is possible to easily detect that a predetermined amount of variable length encoded data has been written into the buffer memory unit 45.

The predetermined amount of variable-length encoded data to be stored in the buffer memory section 45 is set in consideration of the transmission speed, the decoding speed of the variable-length decoding section 48, etc., so that the buffer memory section 45 will not become empty until the end of communication. It is something that

[Problem to be solved by the invention]

When receiving variable length encoded data and restoring the original image information, etc., a delay time required for the decoding process occurs. Furthermore, since the decoding process is not started until a predetermined amount of variable-length encoded data that is set so that the buffer memory section 45 does not become empty is stored, a predetermined amount of received variable-length encoded data is stored in the buffer memory section 45. This method has the drawback of adding a time delay until the encoded data is stored.

The present invention aims to minimize the delay caused by the buffer memory.

(Means for Solving the Problems) The variable length decoding device of the present invention starts decoding upon receiving variable length encoded data, and will be described with reference to FIG.

a buffer memory section 1 into which variable length encoded data is input;
A variable length decoding section 2 decodes the variable length encoded data read from the buffer memory section 1, and a variable length encoded data is written to the buffer memory section 1, thereby reading out the variable length encoded data. The variable length decoding section 2 is provided with a control section 3 that starts the operation of the variable length decoding section 2 and stops the operation of the variable length decoding section 2 when it is detected that the buffer memory section 1 becomes empty.

The control unit 3 also includes a buffer memory capacity calculation unit that calculates the capacity of the buffer memory unit l based on the write clock signal and read clock signal applied to the buffer memory unit 1,
When the buffer memory capacity calculation unit detects that the buffer memory unit 1 is empty, the variable length decoding unit 2
This is to stop the operation of the

In addition, the buffer memory section 1 is constituted by a first-in first-out memory with a flag, variable-length encoded data is converted into parallel data and written into this buffer memory section 1, and parallel data is read from this buffer memory section 1. A rotating unit is provided to sequentially shift and arrange a predetermined number of bits from the beginning of the variable-length encoded data, and an empty flag output when the buffer memory unit 1 becomes empty is used to stop the operation of the variable-length decoding unit 2. The configuration is such that it is used as a control signal.

(Operation) In claim 1, by writing the variable-length encoded data into the buffer memory section 1, the control section 3 immediately controls its reading and starts the decoding process in addition to the variable-length decoding section 2. Therefore, the delay caused by the buffer memory section 1 is reduced to the reception time equal to the number of bits required for decoding processing.Also, when the buffer memory section 1 becomes empty, the operation of the variable length decoding section 2 is By stopping the decoding, noise components can be prevented from being decoded by the variable length decoding unit 2.

In claim 2, the control section 3 causes the buffer memory section 1 to be configured by a buffer memory capacity calculation section that calculates the capacity of the buffer memory section 1 based on the write clock signal and the read clock signal of the buffer memory section 1. When it is calculated that the space is empty, the operation of the variable length decoding unit 2 is stopped, thereby preventing noise components that are not variable length encoded data from being decoded.

In claim 3, the buffer memory section 1 is constituted by a first-in first-out memory with a flag, and the empty flag when empty is used as an operation stop control signal for the variable length decoding section 2, and the buffer memory section 1 is configured as a first-in first-out memory with a flag. Part I is configured to write and read parallel data, and the parallel data read from the Huff-Flash memory part I is shifted in the rotating part according to the code length information from the variable length decoding part 2, and is variable length encoded. 1. Set the first bit of the data to be the first position. This is added to the variable length decoding section 2.

? Embodiments] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a buffer memory section, 12 is a variable length decoding section, 13 is a control section, and 14 is an interface section between the transmission path and the variable length decoding device. 15 is a buffer memory capacity calculation section, 16 is a read clock control section, and 17 is a decoding control section.

The variable length encoded data from the transmitting side is received by the receiving section 14 which functions as an interface section, and the reproduced clock signal is added to the buffer memory section 11 as the write clock signal WCK, and the received variable length encoded data is DT is written.

20 The write clock signal WCK is applied to the sofa memory capacity calculation section 15 and the read clock control section I6, and the read clock control section 16 according to this write clock signal WCK.
A read clock signal RCK is outputted from the buffer memory section 11 and the buffer memory capacity calculation section 15.

Buffer memory section 11 according to read clock signal RCK
The variable-length encoded data DT read from
T is added and decoding processing is performed, and the decoded data DD is output and added to a decoding unit such as an interframe difference decoding unit and an inverse discrete cosine transform unit (not shown), and is converted to the original image information etc. will be restored. Also, state information SS of the variable length decoding section 12 is added to the decoding control section 17. Therefore, when variable length encoded data is received, decoding processing is started immediately.

The buffer memory capacity calculation unit 15 receives the write clock signal W.
Since it is possible to detect whether or not the buffer memory unit 11 is empty based on CK and read clock signal RCK, when the buffer memory unit 11 is empty, the stop control signal SP is sent to the variable length decoding unit 12 and the decoding control unit 17. In addition, the decryption process is stopped. As a result, output of the decoded data DD is stopped. Therefore, undefined data in the buffer memory section 11 can be prevented from being decoded.

FIG. 3 is a block diagram of another embodiment of the present invention, 21
2 is a buffer memory section, 22 is a variable length decoding section, 23 is a decoding control section, 24 is a receiving section, 25 is a serial/parallel converting section, 26
is the rotating part.

The variable length encoded data from the transmitting side is received by the receiving section 24, and the received variable length encoded data and the regenerated clock signal are applied to the serial/parallel converter 25, and the maximum code length of the variable length code is set to 20, for example. If it is a bit, it is converted into 20-pin parallel data and written into the buffer memory unit 21 together with the write clock signal WCK.

In this case, the buffer memory section 21 has a configuration in which 2o bit parallel data can be written and read in parallel, and can be a first-in first-out memory (FIF○) with a flag. This buffer memory section 2
When parallel data is written to 1, the buffer memory section 21
Since is not empty, the empty flag EPF becomes, for example, B which indicates that the buffer memory section 21 is not empty, and when the buffer memory section 21 becomes empty, the empty flag EPF becomes "
This empty flag EPF of "0" becomes an operation stop control signal for the rotating section 26 and the variable length decoding section 22.

When the empty flag EPF from the buffer memory section 21 becomes "1", the start signal ST is applied from the decoding control section 23 to the rotation section 26 and the variable length decoding section 22. Information SS is added to the decoding control section 23.

The read clock signal RCK' is applied to the buffer memory section 21 from the activated rotating section 26, the parallel data is read out, and the shift control is performed so that the first bit of the variable length code data becomes the first position, and then the variable length decoding section Added to 22,
The next shift operation is controlled by the code length information from the variable length decoding section 22.

Therefore, when parallel data is written into the buffer memory section 21, the decoding process by the variable length decoding section 22 is immediately started, and when the buffer memory section 21 becomes empty, the empty flag of "o" The operation of the variable length decoding section 22 is stopped by the EPF.

FIG. 4 is a block diagram of the main parts of the rotating part.
36 is a register, 33 is an upper shifter, 34 is a lower shifter, and 35 is an adder. Every time the upper shifter 33 finishes shifting, for example, 20 pint parallel data is read out from the buffer memory section 21 and set in the register 31, and the previously read parallel data is transferred to the register 32.

The output data of this register 32 is shifted by the upper shifter 33 and the output data of the register 31 is shifted by the lower shifter 34 according to the code length information from the variable length decoding section 22, and the upper and lower data are added by the adder 35. is set in the register 36, and added to the variable length decoding unit 22 as 20-bit parallel data. That is, in the register 36, data shifted by the upper shifter 33 so that the first bit of the variable-length encoded data becomes the first position, and data subsequently shifted by the lower shifter 34 are stored in a predetermined position. It is denominated as 20 bits.

Note that at the initial stage of startup, the 20-bit parallel data read from the buffer memory section 21 is stored in the registers 31 and 3.
2. Upper shifter 33. The adder 35 can be controlled to be immediately added to the variable length decoding section 22 via the register 36.

The present invention is not limited to the above-described embodiments, but can be modified in various ways.

(Effects of the Invention) As explained above, the present invention writes variable length encoded data to the buffer memory unit 1, reads out the variable length encoded data, and performs decoding processing by the variable length decoder 2. The operation of the variable length decoding unit 2 is stopped when the buffer memory unit 1 becomes empty, so that noise components other than variable length encoded data are not decoded, and the start of the decoding process is made variable. Since it can be performed almost simultaneously with the reception of long coded data, it has the advantage of minimizing delay time.It also allows the capacity of the buffer memory section 1 to be reduced, making it more economical. can be achieved.

Also, whether or not the buffer memory section 1 is empty can be easily detected by the buffer memory capacity calculation section based on the write clock signal and read clock signal of the buffer memory section 1. control becomes easier.

In addition, the buffer memory section 1 is configured to be a FIFO memory with a flag, and is configured to read and write data in parallel, so that it is easy to control the operation stop of the variable length decoding section 2 when the buffer memory section 1 becomes empty. In addition, the head of the parallel data to be added to the variable length decoding unit 2 is positioned by the rotation unit so that the head bit of the variable length encoded data is located, thereby facilitating the decoding process of the variable length encoded data. .

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of one embodiment of the present invention, Fig. 3 is a blower diagram of another embodiment of the present invention, and Fig. 4 is a main part of the rotating part. FIG. 5 is an explanatory diagram of a conventional example. 1 is a buffer memory section, 2 is a variable length decoding section, and 3 is a control section.

Claims (3)

[Claims] (1) In a variable length decoding device that decodes variable length encoded data, a buffer memory section (
1), a variable length decoding unit (2) for decoding the variable length encoded data read from the buffer memory unit (1), and a variable length decoding unit (2) for decoding the variable length encoded data read from the buffer memory unit (1); control for stopping the operation of the variable-length decoding section (2) when the variable-length decoding section (2) starts reading out the variable-length encoded data and detects that the buffer memory section (1) becomes empty; A variable length decoding device comprising a section (3). (2), the control unit (3) is configured to control the buffer memory unit (
The buffer memory capacity calculation unit calculates the capacity of the buffer memory unit (1) based on the write clock signal and read clock signal added to the buffer memory unit (1), and the buffer memory capacity calculation unit calculates the capacity of the buffer memory unit (1). 2. The variable length decoding device according to claim 1, further comprising a configuration for stopping the operation of said variable length decoding section (2) when detecting that said variable length decoding section (2) becomes empty. (3), the buffer memory section (1) is configured with a first-in first-out memory with a flag;
Converting the variable-length encoded data into parallel data and writing it into the buffer memory section (1), and reading out the parallel data from the buffer memory section (1) to read predetermined bits from the beginning of the variable-length encoded data. A rotating section that sequentially shifts and arranges the numbers is provided, and an empty flag output when the buffer memory section (1) becomes empty is used as an operation stop control signal for the variable length decoding section (2). The variable length decoding device according to claim 1, characterized in that: