JPH0419851Y2 - - Google Patents
Info
- Publication number
- JPH0419851Y2 JPH0419851Y2 JP4917885U JP4917885U JPH0419851Y2 JP H0419851 Y2 JPH0419851 Y2 JP H0419851Y2 JP 4917885 U JP4917885 U JP 4917885U JP 4917885 U JP4917885 U JP 4917885U JP H0419851 Y2 JPH0419851 Y2 JP H0419851Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- variable resistance
- attenuator
- circuit
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は伝送機器のレベル調整回路に関する。[Detailed explanation of the idea] [Industrial application field] The present invention relates to a level adjustment circuit for transmission equipment.
従来、この種のレベル調整回路としては、第４
図および第５図に示す構成の回路が知られてい
る。第４図に示す回路は、可変抵抗減衰器ATT
と増幅器を直列に構成したもので、増幅器の増幅
度は固定でレベル調整は抵抗減衰器ATTで行な
われている。一方、第５図に示す回路は、差動増
幅器による可変増幅器で帰還抵抗Rfを変化させ
ることによりレベル調整を行つている。
Conventionally, this type of level adjustment circuit has a fourth level adjustment circuit.
A circuit having the configuration shown in FIG. 5 and FIG. 5 is known. The circuit shown in Figure 4 is a variable resistance attenuator ATT.
and an amplifier in series, the amplification degree of the amplifier is fixed, and level adjustment is performed by a resistive attenuator ATT. On the other hand, the circuit shown in FIG. 5 adjusts the level by changing the feedback resistor R f using a variable amplifier using a differential amplifier.
上述した第４図記載のレベル調整器においては
増幅器の増幅度が固定されているため、出力レベ
ルのダイナミツクレンヂに相当する広範囲の可変
抵抗減衰器を必要とし、且つ、出力レベルを最少
にした場合でも増幅度は常に最大となつているた
め、信号レベル対雑音比を一定に保つことが困難
であるという欠点がある。
In the level adjuster shown in Fig. 4 above, since the amplification degree of the amplifier is fixed, a variable resistance attenuator with a wide range corresponding to the dynamic range of the output level is required, and the output level is minimized. Since the degree of amplification is always at the maximum even in the case of high-speed signal transmission, there is a drawback that it is difficult to maintain a constant signal level-to-noise ratio.
一方、第５図記載のレベル調整器においては、
広い出力レベルのダイナミツクレンヂを必要とす
る場合には、帰還抵抗変化量が極めて大きくな
り、また、出力レベルを均一のステツプ可変とす
る場合には、そのステツプ数に等しい数の抵抗と
これら抵抗を切替えるためのスイツチが必要とな
り回路規模が大きくなるという欠点がある。 On the other hand, in the level adjuster shown in FIG.
If a wide dynamic range of output level is required, the amount of change in feedback resistance will be extremely large, and if the output level is to be varied in uniform steps, the number of resistors equal to the number of steps and these resistors will be required. This has the disadvantage that a switch is required to change over the switch, which increases the circuit scale.
本考案のレベル調整器は上述の欠点を除去する
ために、可変抵抗減衰器の入出力に該可変抵抗器
のインピーダンスに等しい値の抵抗値を持つ抵抗
器を配したものと、該抵抗器の２倍の値を持つ抵
抗器を帰還型差動増幅器の入力回路又は帰還回路
にそれぞれ切替えが可能なスイツチとを備えてい
る。
In order to eliminate the above-mentioned drawbacks, the level adjuster of the present invention has a variable resistance attenuator with a resistor having a resistance value equal to the impedance of the variable resistor placed at the input and output, and a resistor with a resistance value equal to the impedance of the variable resistor. It is equipped with a switch capable of switching a resistor having a double value to the input circuit of the feedback differential amplifier or the feedback circuit, respectively.
次に、本考案を図面を参照して詳細に説明す
る。
Next, the present invention will be explained in detail with reference to the drawings.
第１図は本考案の一実施例を示す回路図であ
る。図において、本考案のレベル調整回路は、入
力端子１と、可変抵抗減衰器２のインピーダンス
マツチング用の抵抗値Ｒを有する抵抗５および６
と、抵抗値2Rを持つ抵抗７と、差動増幅器３と、
出力端子４と、増幅器又は減衰器として構成する
ための切替スイツチ８および９とから構成されて
いる。スイツチ８および９の接点が実線側にある
場合は、本回路は減衰器として動作し、一方スイ
ツチ８，９の接点が点線側にある時は増幅器とし
て動作する。これら２つの機能を分り易くするた
め、スイツチ８，９が実線側にある場合を第２図
に示し、スイツチ８，９が点線側にある場合を第
３図に示す。 FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the level adjustment circuit of the present invention includes an input terminal 1 and resistors 5 and 6 having a resistance value R for impedance matching of a variable resistance attenuator 2.
, a resistor 7 with a resistance value of 2R, a differential amplifier 3,
It consists of an output terminal 4 and changeover switches 8 and 9 for configuration as an amplifier or an attenuator. When the contacts of switches 8 and 9 are on the solid line side, the circuit operates as an attenuator, while when the contacts of switches 8 and 9 are on the dotted line side, the circuit operates as an amplifier. In order to make these two functions easier to understand, FIG. 2 shows the case where the switches 8 and 9 are on the solid line side, and FIG. 3 shows the case where the switches 8 and 9 are on the dotted line side.
第２図において、抵抗５，６は可変抵抗減衰器
２のインピーダンスマツチング用抵抗器でRΩの
値を持つ。この構成で入力端子１から差動増幅器
３の（−）入力端間の抵抗値は常に2Rとなる。
一方差動増幅器３の（−）入力端子と差動増幅器
３の出力間には2Rの抵抗値を持つ抵抗７が接続
されている。第２図の構成においては、増幅器３
はいわゆる帰還型差動増幅器となり、増幅度は１
以下で減衰器として動作する。一例として可変抵
抗減衰器２の減衰量をａ（dB）とし、入力端子１
から出力端子間の増幅度をＡ（dB）とすると
Ａ＝20log10（2R／Ｒ＋Ｒ）−ａ
で表わされ、Ａ＝−ａとなり、可変抵抗減衰器２
の値と同じ減衰器として動作する。 In FIG. 2, resistors 5 and 6 are impedance matching resistors of the variable resistance attenuator 2 and have a value of RΩ. With this configuration, the resistance value between the input terminal 1 and the (-) input terminal of the differential amplifier 3 is always 2R.
On the other hand, a resistor 7 having a resistance value of 2R is connected between the (-) input terminal of the differential amplifier 3 and the output of the differential amplifier 3. In the configuration of FIG. 2, the amplifier 3
is a so-called feedback type differential amplifier, and the amplification degree is 1.
It operates as an attenuator below. As an example, let the attenuation amount of the variable resistance attenuator 2 be a (dB), and input terminal 1
If the amplification degree between the output terminals is A (dB) from then, it is expressed as A=20log 10 (2R/R+R)-a, so A=-a, and the variable resistance attenuator 2
It acts as an attenuator with the same value as .
一方、第３図の構成においては、第２図の入力
回路である抵抗５、減衰器２、抵抗６が帰還回路
となり、帰還回路の抵抗７が入力回路に置換され
る。この構成における増幅度をA′（dB）とし、可
変抵抗減衰器２の減衰量をa′（dB）とすると、
A′＝20log10（Ｒ＋Ｒ／2R）＋a′
で表わされA′＝a′となり、可変抵抗減衰器の減衰
量の絶対値と等しい増幅器として動作する。 On the other hand, in the configuration of FIG. 3, the input circuit of FIG. 2, which is the resistor 5, attenuator 2, and resistor 6, becomes a feedback circuit, and the resistor 7 of the feedback circuit is replaced by the input circuit. If the amplification degree in this configuration is A' (dB) and the amount of attenuation of the variable resistance attenuator 2 is a' (dB), then it is expressed as A' = 20log 10 (R + R / 2R) + a', and A' = a ', and operates as an amplifier whose absolute value is equal to the attenuation of the variable resistance attenuator.
以上説明したように本考案においては、可変抵
抗減衰器をスイツチにより入力回路又は帰還回路
に切替挿入することにより、可変抵抗減衰器の減
衰量の絶対値に等しい増幅器又は減衰器を構成す
ることができるため、特にデータ伝送機器等にお
いて線路のレベルダイヤに合せて出力レベルを調
整する必要がある場合には極めて容易にレベル調
整ができる。
As explained above, in the present invention, by switching and inserting the variable resistance attenuator into the input circuit or the feedback circuit using a switch, it is possible to configure an amplifier or attenuator whose absolute value is equal to the attenuation amount of the variable resistance attenuator. Therefore, the level can be adjusted extremely easily, especially when it is necessary to adjust the output level according to the level diagram of the line in data transmission equipment or the like.
第１図は本考案の一実施例を示す回路図、第２
図および第３図は第１図のスイツチの動作位置に
よる構成を分解して示した回路図、および第４図
および第５図は従来例を示す回路図である。
第１図〜第３図において、１……入力端子、２
……可変抵抗減衰器、３……差動増幅器、５，６
……インピーダンスマツチング用抵抗器、７……
抵抗器、８，９……スイツチ。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
3 and 3 are circuit diagrams showing an exploded configuration of the switch shown in FIG. 1 depending on its operating position, and FIGS. 4 and 5 are circuit diagrams showing a conventional example. In Figures 1 to 3, 1...input terminal, 2
... Variable resistance attenuator, 3 ... Differential amplifier, 5, 6
... Impedance matching resistor, 7...
Resistor, 8, 9...switch.
Claims (1)
および出力端に前記可変抵抗減衰器のインピーダ
ンスに等しい値の抵抗器を接続した第１の調整部
と、前記可変抵抗減衰器のインピーダンスの２倍
の値の抵抗器である第２の調整部を有し、前記第
１の調整部と前記第２の調整部のそれぞれの一方
を接続して差動増幅器のマイナス極性入力とし、
前記第１の調整部の他方と前記第２の調整部の他
方を２個のトランスフアスイツチの１方の接点に
それぞれ接続し、前記２個のトランスフアスイツ
チの他方の接点は前記一方の接点とタスキ掛けと
なるように接続し、前記２個のトランスフアスイ
ツチの共通端子の一方は前記差動増幅器の出力と
接続し、前記共通端子の他方をレベル調整回路の
入力とするように構成したことを特徴としたレベ
ル調整回路。 a variable resistance attenuator; a first adjustment unit having a resistor connected to the input terminal and the output terminal of the variable resistance attenuator, the resistor having a value equal to the impedance of the variable resistance attenuator; a second adjustment section that is a resistor with a value of , and one of each of the first adjustment section and the second adjustment section is connected to serve as a negative polarity input of a differential amplifier;
The other of the first adjusting section and the other of the second adjusting section are respectively connected to one contact of two transfer switches, and the other contact of the two transfer switches is connected to the one contact of the two transfer switches. one of the common terminals of the two transfer switches was connected to the output of the differential amplifier, and the other of the common terminals was configured to be used as the input of the level adjustment circuit. A level adjustment circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4917885U JPH0419851Y2 (en) | 1985-04-02 | 1985-04-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4917885U JPH0419851Y2 (en) | 1985-04-02 | 1985-04-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61166620U JPS61166620U (en) | 1986-10-16 |
| JPH0419851Y2 true JPH0419851Y2 (en) | 1992-05-07 |
Family
ID=30566131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4917885U Expired JPH0419851Y2 (en) | 1985-04-02 | 1985-04-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419851Y2 (en) |
-
1985
- 1985-04-02 JP JP4917885U patent/JPH0419851Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61166620U (en) | 1986-10-16 |
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