JPH04196796A - Television receiver - Google Patents

Abstract

PURPOSE:To display a pattern with high picture quality by interfacing data as an inputted video signal or converting the data even when the inputted video signal is a non-standard signal. CONSTITUTION:A detection means 121 detects whether an inputted video signal is a standard signal or a non-standard signal, and when the signal is decided to be a standard signal, a 1st changeover means 102 is closed to synchronize a 2nd clock generating means 111 with a 1st clock generating means 110 and to connect a 2nd changeover means 104 to a burst lock clock, and it is outputted. When the signal is decided to be a non-standard signal, the 1st changeover means 102 is opened and the 2nd clock generating means 111 generates a clock independently. Moreover, when the inputted signal is a non-standard signal, an interface means 105 is used to connect the signal processed by a line lock clock and the signal processed by a burst lock clock. Thus, the effect of picture quality improvement is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides the following advantages: by doubling the number of scan lines and converting the scan line structure from incremental scanning to that of progressive scanning.
It relates to a television receiver that realizes a high-definition screen, and more specifically, for example, when a standard television signal according to the NTSC standard method is input, or when
Even when a non-standard television signal such as a playback video signal from a TR (video tape recorder) is input, the line lock clock signal locked to the horizontal synchronization signal and the hard lock clock signal locked to the color burst can be used. This invention relates to a television receiver that makes it possible to maintain a high-definition screen by performing signal processing in an optimal lock by using different types of signals.

[Prior Art] FIGS. 2(a) and 2(b) are block diagrams showing a conventional clock generating device in a television receiver, respectively.

In FIGS. 2(a) and 2(b), numeral 1 indicates a video signal input terminal, 2 a line lock clock generation circuit, 3 a line lock clock, 4 a Hurst clock clock generation circuit, and 5
is a burst lock clock, 9 is a synchronization signal generation circuit, 1
0 is a signal processing circuit, 11 is a synchronization signal output terminal, and 12 is a video signal output terminal.

First, the circuit shown in FIG. 2(a) will be explained.

The burst lock clock generation circuit 4 uses a crystal oscillator (not shown) to create a stable burst lock clock 5 that is synchronized with the color burst signal included in the video signal input from the video signal input terminal 1. Occur.

Here, the input video signal is a signal that complies with the standard television broadcasting system (hereinafter referred to as the standard signal), and the frequency (fsc) of the color burst signal included in this standard signal and the horizontal synchronization signal are The relationship with frequency (f h) is as follows.

Next, the synchronization signal generation circuit 9 inputs the hard-lock clock 5 from the hard-lock clock generation circuit 4, and
A synchronization signal created using the relationship in equation (1) above is generated.

The signal processing circuit 10 also processes a video signal input from the video signal input terminal 1 and a burst lock clock generation circuit 4.
Enter Burst Lock Kurotsuta 5 from above (1).
) is used to perform signal processing on the video signal to improve the image quality of the video signal. Examples of conventional circuits that perform signal processing to improve the image quality of video signals are as follows:
JP-A-60-18085 is mentioned.

Next, the circuit shown in FIG. 2(b) will be explained.

The line lock clock generation circuit 2 creates and generates a line lock clock 3 synchronized with a horizontal synchronization signal included in the video signal inputted from the video signal input terminal 1.

Next, the synchronization signal generation circuit 9 inputs the line lock clock 3 from the line lock clock generation circuit 2, and creates and generates a synchronization signal.

Further, the signal processing circuit 10 receives a video signal input from the video signal input terminal 1 and a line lock clock 3 from the line lock clock generation circuit 2, and performs signal processing on the video signal.

[Problems to be Solved by the Invention] In the above-mentioned prior art, first, in the circuit shown in FIG. Not only can synchronization signals be generated, but also signal processing can be performed to improve the image quality of video signals.

However, signals that do not strictly comply with the standard television broadcasting system (hereinafter referred to as non-standard signals), such as video signals played from a VTR (video tape recorder), etc. 1) If a non-standard signal is input that does not necessarily hold the relationship in the formula, the above (
Since the relationship in equation 1) does not necessarily hold, there is a problem that not only is it impossible to perform signal processing to improve image quality, but also that the entire circuit operation of the receiver cannot be synchronized.

On the other hand, in the circuit shown in Fig. 2(b), since the horizontal synchronization signal included in the video signal is used as a reference, sufficient synchronization can be achieved even when a non-standard signal is input. It is possible to handle video signals from devices such as

Regarding signal processing to improve image quality, if a non-standard signal is input, the non-standard signal will be processed as described above (
Since the relationship expressed by equation 1) is not maintained, signal processing for improving image quality is possible as long as the relationship is not utilized.

However, when a standard signal is input, the standard signal is
1) However, in the circuit of FIG. 2(b), the Q value of the oscillator (not shown) of the line lock clock generation circuit 2 is different from the burst of FIG. 2(a). Since it is not as high as that of the crystal oscillator (not shown) of the lock crotch generating circuit 4, and the stability of the generated crotch is also low, a signal for improving image quality is generated using the relationship in equation (1) above. When attempts were made to carry out the treatment, the improvement effect was low.

An object of the present invention is to provide a television receiver that can maintain the effect of improving image quality by performing signal processing with an optimal lock suitable for both standard and non-standard signal input. be.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides the following means as several methods.

In the first method, a first clock generating means generates and generates a hard-lock clock synchronized with a color burst signal included in a video signal, and a line-lock clock synchronized with a horizontal synchronization signal included in the video signal. a second clock generation means that generates and generates a second clock; and a detection means that detects whether the video signal is a standard signal that conforms to a predetermined standard (that is, whether it is a standard signal or a non-standard signal). and a first switching means that switches between connecting or not connecting the output of the first clock generating means to the second clock generating means, and switching between the first clock generating means and the second clock generating means. A second switching means, an interface means for interfacing between a signal operated by the line lock clock and a signal operated by the hard lock clock, and a synchronization signal created and generated by the output of the second clock generation means. A synchronizing signal generating means is provided.

In the second method, a first clock generating means generates and generates a burst lock clock synchronized with a color burst signal included in a video signal, and a line lock clock synchronized with a horizontal synchronization signal included in the video signal. a second clock generation means that generates and generates a second clock; and a detection means that detects whether the video signal is a standard signal that conforms to a predetermined standard (that is, whether it is a standard signal or a non-standard signal). and a first switching means for switching whether or not to connect the output of the first clock generating means to the second clock generating means, and between the first clock generating means and the second clock generating means. a second switching means for switching; a time axis correction means for correcting and outputting the time axis of an input signal; and a synchronization signal generation means for generating and generating a synchronization signal using the output of the first clock generation means; It has been established.

In the third method, a clock generating means generates and generates a hard-locked clock synchronized with a color burst signal included in a video signal, a synchronization separating means extracts a horizontal synchronization signal included in the video signal, and A detection means for detecting whether the signal is a standard signal that meets a predetermined standard (that is, whether it is a standard signal or a non-standard signal), and a detection means for correcting the time axis of the input signal and outputting it. The apparatus is provided with a time axis correction means and a synchronization signal generation means that generates and generates a synchronization signal using the output of the clock generation means.

A fourth method includes clock generation means for generating and generating a hard-lock clock synchronized with a color burst signal included in a video signal, synchronization separation means for extracting a horizontal synchronization signal included in the video signal, and a synchronization separation means for extracting a horizontal synchronization signal included in the video signal; detection means for detecting whether or not the signal is a standard signal that meets a predetermined standard (that is, whether it is a standard signal or a non-standard signal), and a detection means that corrects the time axis and frequency of the input signal and outputs it. and a synchronization signal generation means that generates and generates a synchronization signal using the output of the clock generation means.

A fifth method includes a first clock ordering means that generates and generates a burst lock clock synchronized with a color burst signal included in a video signal, and a line lock clock synchronized with a horizontal synchronization signal included in the video signal. a second clock generation means that generates and generates a second clock; and a detection means that detects whether the video signal is a standard signal that conforms to a predetermined standard (that is, whether it is a standard signal or a non-standard signal). and a first switching means that switches between connecting or not connecting the output of the first clock generating means to the second clock generating means, and switching between the first clock generating means and the second clock generating means. a second switching means, a time axis frequency correction means for correcting the time axis and frequency of the input signal and outputting the corrected signal, and a synchronization signal generation means for creating and generating a synchronization signal using the output of the first clock generation means. .

A sixth method includes clock generation means for generating and generating a hard-lock clock synchronized with a color burst signal included in a video signal, synchronization separation means for extracting a horizontal synchronization signal included in the video signal, and a synchronization separation means for extracting a horizontal synchronization signal included in the video signal; detection means for detecting whether or not the input signal is a standard signal that meets a predetermined standard (that is, whether it is a standard signal or a non-standard signal); The apparatus is provided with a time axis correction color demodulating means for demodulating and outputting the demodulated signal, and a synchronizing signal generating means for creating and generating a synchronizing signal using the output of the clock generating means.

A seventh method includes a first clock generating means that generates and generates a burst lock clock synchronized with a color burst signal included in a video signal, and a line lock clock synchronized with a horizontal synchronization signal included in the video signal. a second clock generation means that generates and generates a second clock; and a detection means that detects whether the video signal is a standard signal that conforms to a predetermined standard (that is, whether it is a standard signal or a non-standard signal). and a first switching means for switching whether or not to connect the output of the first clock generation means to the second clock generation means, and between the first clock generation means and the second clock generation means. A synchronization signal is created by the output of the second switching means, the time axis correction color demodulation means that corrects the time axis of the input signal and further demodulates and outputs the color signal, and the first clock generation means. synchronous signal generating means for generating a synchronizing signal.

[Operation] In the first method, the detection means detects whether the input video signal is a standard signal or a non-standard signal, and when it is determined that the input video signal is a standard signal, switches the first switching means. O
NL, synchronizes the second clock generation means with the first clock generation means. In addition, the second switching means is burst lock black.

Connect to the opposite side and output. If it is determined that the input video signal is a non-standard signal, the first switching means is turned off and the second clock generation means independently generates a clock, which is optimal for each circuit. A lock can be provided.

In addition, if the input signal is a non-standard signal, the interface means can connect the signal processed by the line port or clock clock to the signal processed by the hard lock clock, so the signal processing that is optimal for each can be achieved. can be applied.

In the second method, the interface means in the first method is replaced with a time axis correction means, and when the input signal is a non-standard signal, the time axis can be corrected so that it can be processed as a standard signal. , all circuits connected after that can perform standard signal processing.

In the third method, the interface means in the first method is replaced with a time axis correction means, and a synchronization separation means is provided in place of the second clock generation means,
Since the time axis can be corrected using the horizontal synchronization signal obtained from the synchronization separation means, all circuits connected thereafter can perform standard signal processing.

In the fourth method, the time axis correction means in the third method is replaced with a time axis frequency correction means,
Since both the time axis and frequency of the input signal can be corrected, color demodulation can be performed afterwards, and all connected circuits can perform standard processing.

In the fifth method, the synchronization separation means in the fourth method 22 is replaced with a second clock generation means that generates a line lock clock synchronized with the input video signal. Color demodulation is performed, and all connected circuits can perform standard processing.

In the sixth method, the time axis frequency correction means in the fourth method is replaced with time axis correction color demodulation means, and since the time axis correction and color demodulation of the input signal can be performed simultaneously, the The circuit can process all color demodulated signals as standard signals.

In the seventh method, the synchronization separation means in the sixth method is replaced with a second clock generation means that generates a line start, clock, and clock synchronized with the horizontal synchronization signal of the input video signal, As a result, time axis correction and color demodulation of the input signal can be performed simultaneously, so that subsequent circuits can process all the color demodulated signals as standard signals.

(Example] A first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing the configuration of a television receiver as a first embodiment of the present invention. In the same figure, 1
01 is an input terminal, 102 is a Y/C separation circuit, 103 is a color demodulation circuit, 104 is a frame comb circuit, 105 is an interface circuit, 106 is a double speed conversion circuit, 107 is a luminance signal output terminal, and 108 and 109 are color difference signals. It is an output terminal.

110 is a hard lock clock generation circuit, 111 is a line lock clock generation circuit, 112 is a synchronous separation circuit,
113 is a phase comparator, 114 is a low pass filter (LPF),
115 is an adder, 116 is a voltage controlled oscillator (VCO),
117 is a capacitor, 118 is a frequency divider, 119, 120
121 is a switch, and 121 is a standard/non-standard signal detection circuit.

Next, circuit operation will be explained.

The composite video signal input from the input terminal 101 is standard/
The signal is input to the non-standard signal detection circuit 121.

The standard/non-standard signal detection circuit 121 examines the frequency relationship between the horizontal synchronization signal and the color burst signal of the input signal, and converts the input signal into a standard signal if the relationship in equation (1) above holds. If the relationship in equation (1) above does not hold, the input signal is determined to be a non-standard signal and the result is output.

Incidentally, known examples of such standard/non-standard signal detection circuits are described in, for example, Japanese Patent Laid-Open No. 61-184082.
Publication No.

Further, the composite video signal input from the input terminal 101 is input to the line lock clock generation circuit 111. In the line lock clock generation circuit 111, the horizontal synchronization signal included in the video signal is separated by the synchronization separation circuit 112, and the line lock clock having a frequency 1820 times the frequency fh of the horizontal synchronization signal is sent to the phase comparator 113. ．． Low pass filter (LPF) 114. Adder 115. Voltage controlled oscillator (VCO) 116. A phase locked loop (PLL) circuit including a frequency divider 118 generates and outputs the signal.

Further, the composite video signal inputted from the input terminal 101 is inputted to the Hurst lock clock generation circuit 110. The burst lock clock generation circuit 110 extracts the color burst signal included in the input video signal,
A burst lock clock having a frequency eight times the frequency fsc is generated and output using a crystal oscillator (not shown). In this way, since the burst lock clock is generated by a crystal oscillator, very stable locking can be obtained.

Next, the switch 120 inputs the detection signal from the standard/non-standard signal detection circuit 121, and when the input video signal is a non-standard signal, it is sent to the line opening/tsukurotsuta side, and when the input video signal is a standard signal. Sometimes it closes to the burst lock clock side and outputs each clock.

Next, the operation of clock phase control will be explained.

Burst lock clock generation circuit 110 also outputs the burst lock clock to switch 119. The switch 119, like the switch 120, is controlled by a detection signal from the standard/non-standard signal detection circuit 121, and is opened when the input video signal is a standard signal. Therefore, switch 119 supplies the hard-lock clock to line-lock clock generation circuit 111 only when the signal is a standard signal.

The line lock clock generation circuit 111 includes a switch 11
When the burst lock clock is supplied from 9, it operates to match the phase of the output line lock clock with the phase of the burst lock clock.

Here, the operation of the line lock clock generation circuit 111 will be explained in more detail.

First, the synchronization separation circuit 112 separates the horizontal synchronization signal included in the video signal input from the input terminal 101 and inputs it to one input of the phase comparator 113 . Frequency divider 118 divides the line lock clock output from voltage controlled oscillator (VCO) 116 by 1820, and inputs the divided output to the other input of phase comparator 113 .

The phase comparator 113 compares the phases of the input horizontal synchronizing signal and the output signal from the frequency divider 118, and outputs a voltage according to the phase difference. And a low pass filter (LPF)
) 115 takes out only the low frequency component of the output voltage of the phase comparator 113 and inputs it to one input of the adder 115.

A voltage controlled oscillator (VCO) 116 receives the control voltage output from the adder 115, oscillates at a frequency corresponding to the control voltage, and outputs the oscillation output as a line lock clock.

Further, when the reverse lock clock is input to the switch 119, the capacitor 117 removes the DC component of the burst lock clock and inputs only the AC component to the other input of the adder 115.
When nothing is inputted to the adder 115, nothing is inputted to the adder 115.

When the AC component of the hard-locked clock is input from the capacitor 117, the adder 115 adds the output from the previously input low-pass filter (LPF) 114 to the output from the low-pass filter (LPF) 114.
Add (superimpose) the AC component of that hearth lock clock
A voltage controlled oscillator (VCO) is used as the aforementioned control voltage.
116.

Conversely, when nothing is input from the capacitor 117, the previously input output from the low pass filter (LPF) 114 is input as is to the voltage controlled oscillator (VCO) 116 as the aforementioned control voltage.

Therefore, when the video signal input to the input terminal 101 is a non-standard signal and nothing is input from the switch 119 to the capacitor 117, the voltage controlled oscillator (VCO)
) 116 is a clock synchronized with the horizontal synchronization signal.

Conversely, when the video signal input to the input terminal 101 is a standard signal and the hard-lock clock is input from the switch 119 to the capacitor 117, the line-lock clock output from the voltage controlled oscillator (VCO) 116 is The clock is phase-synchronized with the hard-lock clock. Regarding this kind of circuit operation, please refer to Masamichi Shimura's "Nonlinear Circuit Theory" (Electronic Circuits Course 3) p69-p7.
4 etc., so please refer to them if necessary.

Now, the composite video signal input from the input terminal 101 is
It is also input to the Y/C separation circuit 102.

The input composite video signal is separated into a composite video signal and a color signal band signal in the case of a standard signal by the detection signal output from the standard/non-standard signal detection circuit 121, and in the case of a non-standard signal, The signal is separated into a luminance signal and a color signal band signal and output. The color signal band signal is sent to the color demodulation circuit 103.
The signal is input into the , color demodulated, and output as a color difference signal.

Here, regarding the specific configuration of the Y/C separation circuit 102,
This will be explained in detail using FIG.

FIG. 3 shows a specific example of the Y/C separation circuit 102, in which 130 is an input terminal, 131.134 is a switch, and 13
3 is a line comb filter, 132 and 135 are output terminals, and 136 is a switching signal input terminal.

When the composite video signal is input from the input terminal 130, the line comb filter 133 separates the luminance signal and the carrier color signal, and outputs the luminance signal to the switch 131 and the carrier color signal to the switch 134.

The switching signal input terminal 136 is a standard/
It is connected to the non-standard detection circuit 121, and the detection signal output from the standard/non-standard detection circuit 121 is input.

Switches 131 and 134 are switching signal input terminal 1
Depending on the detection signal inputted from 36, in the case of a standard signal, the signal inputted from input terminal 130 is passed through as it is,
In the case of a non-standard signal, the output signal of the line comb filter 133 is passed.

Note that the line comb filter 133 used here may be of any type as long as it can separate the luminance signal and carrier color signal. Also, switches 131 and 134 may be removed so that line comb filter 133 is always in operation.

As a result, the composite video signal is outputted as is to the output terminal 132 in the case of a standard signal, and the luminance signal is outputted in the case of a non-standard signal. Further, to the output terminal 135, in the case of a standard signal, the composite video signal is outputted as is, and in the case of a non-standard signal, the carrier color signal is outputted.

Now, returning to FIG. 1, the signal output from the Y/C separation circuit 102, which is a composite video signal when it is standard, and the luminance signal when it is non-standard, and the color difference signal output from the color demodulation circuit 103 are frame The signal is input to the comb circuit 104, subjected to frame Y/C separation, and sent to the interface circuit 105 as a high-quality signal.

However, this frame comb circuit 104 performs frame Y/C separation when the signal is a standard signal, but when the signal is a non-standard signal, the relationship in equation (1) above is not maintained, so the frame Y/C separation is performed.
C. Separation is not performed. This is the standard/non-standard detection circuit 12
1 output.

The interface circuit 105 does nothing when the input signal is a standard signal, but performs data interfacing when it is a non-standard signal.

In other words, when the input signal is a non-standard signal, Y/
A hard lock clock is used for the C minute M (102), color demodulation (103), and frame (diamond filter (104)), and a line lock clock is used for the double speed conversion circuit 106, which will be described later. Data conversion is performed by the interface circuit 105 in order to establish the interface.Specifically, this is shown in FIG.

FIG. 4 shows a specific example of the interface circuit 105, in which 140.144.148 are input terminals, 141,
145, 149 are D/A converters, 142.146, 15
0 is the A/D converter, 143° 147.151 is the output terminal, 152 is the D/A clock input terminal 53 is the A/D
Quo clock input terminal for use.

Next, the circuit operation of FIG. 4 will be described in the case where the input signal is non-standard.

The luminance signal and two color difference signals input from the input terminals 140, 144, 148 are input to D/A converters 141, 145, 149 which operate with the Hurst lock clock input to the D/A clock input terminal 152. and converts the digital signal into an analog signal.

The signals converted to analog signals are further input to A/D converters 142, 146, and 150, and converted to digital signals by the line lock clock input to the A/D quad clock input terminal 153. And output terminal 143
, 147, 151.

In this way, a signal that is sampled using the burst rotor clock when input can be converted into a signal that is sampled using the line lock clock. However, if the signal input to the interface circuit 105 is an analog signal, the D/A converter 141.14
5,149 is not necessary.

If the input signal is a non-standard signal, data conversion as shown above is performed, but if it is a standard signal, the A/D
Since the clock input to the quake clock input terminal 153 is also a Hurst lock clock, the same clock is used for D/A.
Conversion and A/D conversion are performed, which is the same as not performing data conversion.

Returning to FIG. 1, the signal obtained from the interface circuit 105 is input to the double speed conversion circuit 106.

The double speed conversion circuit 106 converts the input interlaced scanning (interlaced scanning) signal into a non-interlaced scanning (also referred to as non-interlaced scanning or progressive scanning) signal, and outputs a luminance signal converted to non-interlaced scanning. and two color difference signals are obtained.

The luminance signal and two color difference signals converted to non-interlaced scanning are output from output terminals 107, 108 and 109.

In this way, a signal processed with the optimum clock for each process is obtained at the output.

A second specific example of the clock output circuit from the line lock clock generation circuit 111 in FIG. 1 will now be described with reference to FIG. 5.

FIG. 5 shows a second specific example of the clock output circuit from the line lock clock generation circuit 111.
is a burst lock clock input terminal, 156 is a signal input terminal, 157 is a standard/non-standard switching signal input terminal, 1
58a and 159b are line rotor cloth output terminals.

That is, in FIG. 5, the second switch 120 on the output side of the line lock clock generation circuit 111 shown in FIG. It is.

Even if the second switch 120 is removed in this way, when the line lock clock is a standard signal, the switch 119
Since it is synchronized with the burst lock clock through the route of the capacitor 117 and the adder 115, the double speed conversion circuit 106
works without any problems.

Note that either the circuit shown in FIG. 1 or FIG. 5 may be used as the output circuit of the line lock clock generation circuit 111 shown below.

Next, a second embodiment of the present invention will be described.

FIG. 6 is a block diagram showing a second embodiment of the present invention, in which the same parts as in FIG. 1 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIG. 1 operate in the same way, the explanation will be omitted.

The second embodiment shown in FIG. 6 is an embodiment in which the connection order of the interface circuit 105 and frame comb circuit 104 in FIG. 1 is reversed.

In FIG. 6, by placing the interface circuit 105 in front of the frame comb circuit 104, it is possible to sample the non-standard signal with the line-lock clock, although it is not as accurate as sampling the standard signal with the hard-lock clock. be able to. Therefore, the frame comb circuit 104 can be operated even in the case of non-standard signals.

Thereby, the frame comb circuit can be operated regardless of whether the input signal is standard or non-standard, so noise can be removed and a signal with higher image quality can be obtained.

Next, a third embodiment of the present invention will be described.

FIG. 7 is a diagram showing a third embodiment of the present invention.
201 is a TBC (time base collector) circuit (also called a time base correction circuit), and the same components as in FIG. 1 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIG. 1 operate in the same way, the explanation will be omitted.

In the third embodiment shown in FIG.
1 performs an operation to correct the time axis of an input signal, as is used in VTRs and the like.

Here, one specific example of the TBC circuit 201 will be explained using FIG. 8.

In FIG. 8, 371 is an input terminal, 372 is a waveform memory, 373 is an output terminal, 337 is a write clock input terminal, and 338 is a read clock input terminal.

The signal input from the input terminal 317 is written into the waveform memory 372 using the write clock input from the write clock input terminal 337.

At this time, the write clock uses a line lock clock that follows the time axis fluctuation of the input signal.

The signal written in this waveform memory 372 is
It is read out using the clock input from the read clock input terminal 338 in the next horizontal scanning period. This readout clock uses a very stable clock that is a predetermined multiple of the color subcarrier frequency generated by a crystal or the like.

As a result, a signal with time-axis fluctuations at the input is converted into a signal with the time-axis fluctuations corrected at the output, and is output. In this way, a signal whose time axis fluctuations have been corrected can be obtained at the output terminal 373.

Regarding the operation of the TBC circuit, please refer to "rNHK Home Video Technology" (Japan Broadcasting Corporation [) pH5] if necessary.

As explained above, in FIG.
The signal obtained by 1 is then transmitted to a frame comb circuit 104 which is operated by a burst rotor clock connected thereto.
and is processed by the double speed conversion circuit 106 and output. Also,
Since the synchronizing signal generating circuit 9 outputs a signal processed by a hard-lock clock, it is connected so that the input clock can be obtained from the hard-lock clock generating circuit 110.

In this embodiment, most of the signal processing circuit can be operated as a burst rotor, which has the advantage of realizing stable operation.

Next, a fourth embodiment of the present invention will be described.

FIG. 9 is a schematic diagram showing a fourth embodiment of the present invention, in which the same parts as in FIGS. 1 and 7 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 7 operate in the same way, the explanation will be omitted.

In the fourth embodiment, shown in FIG. 9, the connections between the frame comb circuit 104 and the interface circuit 201 in FIG. 7 are reversed. With this configuration as well, the same operation as in FIG. 7 can be realized.

However, in this case, the frame comb circuit 104 is controlled to turn off its operation when a non-standard signal is input.

Next, a fifth embodiment of the present invention will be described.

FIG. 10 is a block diagram showing a fifth embodiment of the present invention, in which 202 is a data conversion circuit, and the same parts as in FIG. 1 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 7 operate in the same way, the explanation will be omitted.

FIG. 10, which is the fifth embodiment, shows the TBC in FIG.
In place of the circuit 201, a data conversion circuit 202 is provided as an interface circuit.

Data conversion circuit 202 as this interface circuit
A clock is input from the hard-lock clock generation circuit 110, and an output signal from the frequency divider 118 of the line-lock clock generation circuit 111 is input.

The data conversion circuit 202 will now be explained in detail.

Here, we will explain the case where an NTSC signal is input and the standard clock is 910 times the horizontal frequency and 4 times the color subcarrier frequency, but a clock with any other multiple may be used, and the input signal is 910 times the horizontal frequency and 4 times the color subcarrier frequency. Not limited to NTSC signals
It operates similarly for signals such as AL and SECAM.

FIG. 11 is a diagram showing a specific example of the data conversion circuit 202 in FIG.
62,168.174 is 1.163,169.
175 is 2 for the coefficient unit.

164.170, 176 are adders, 165, 171.1
77 is an output terminal, 178 is a clock input terminal, 179 is a synchronization signal input terminal, 180 is a length counter, 181 is 9
10 clock counter, 182 is an arithmetic circuit.

In FIG. 11, signals input from input terminals 160, 166, and 172 are input to memories 161, 167, and 173. The memories 161, 167, and 173 write the input signals using the clock of the Hurst stroker input from the clock input terminal 178. This memory 16L
167 and 173 can store input signals for one scanning line or more.

On the other hand, the length counter 180 is connected to the synchronization signal input terminal 179.
The length of one horizontal scanning period of the horizontal synchronizing signal inputted from the input terminal is counted in terms of the number of burst clocks. Then, the result is output to the arithmetic circuit 182.

Further, the 910 clock counter 181 counts and outputs the burst rotor clock every l horizontal scanning amount period.

The length of one horizontal scanning period of the input signal and a signal obtained by counting the Hurst Stroke clock every one horizontal scanning amount period are inputted to the arithmetic circuit 182.

The arithmetic circuit 182 calculates how far the input signal deviates from the correct signal length based on the input signal, and further adjusts the input signal to the correct length according to the amount of deviation. The information for converting the flag is output.The operation will be explained using FIG.

FIG. 12 is a block diagram for realizing the arithmetic circuit 182 in FIG. 11 with a circuit. In the same figure, 30
1 is an input terminal for the length information (L) from the length counter 180, 302 is an input terminal for the count signal (N) from the 910 counter 181, 303 is a constant (1/910) generator, and 304 and 305 are multiplication terminals. 306 is the input signal (LN/
910), 307 and 310 are subtracters, 308 is a memory read signal output terminal, 314 is a constant 1 generator, 312
is an output terminal with 1 for the coefficient, and 315 is an output terminal of 2 for the coefficient.

The length information input from the length information input terminal 301 is
It is input to the multiplier 304 and multiplied by a constant (1/910) input from the other terminal. The multiplied output is further input to a multiplier 305Q, and is multiplied by the count signal N input from the 910 count signal input terminal 302.

The output of the multiplier 305 is input to the integer part extractor 306, and the integer part of (LN/910) (this is assumed to be A)
Take out only. The extracted integer part information (A) is
It is output from the output terminal 308 and is sent to the memory 161 in FIG.
, 167.173 is used as an address when reading data.

Also, information output from the multiplier 305 (LN/910
), the output information (A) of the integer part extractor 306 is subtracted by the subtracter 307, and the decimal part information (B=(LN/910)-A) in (LN/910) is extracted.

The decimal part information output from the subtracter 307 has a coefficient of 1.
It is output to the output terminal 312. The information of the decimal part output from the subtracter 307 is subtracted from the constant 1 by the subtracter 310 and outputted to the 2 output terminal 315 as a coefficient. The coefficients 1 and 2 output here are used as coefficients indicating the ratio when mixing signals in FIG. 11.

The memory read address and coefficient Kl obtained in this manner are outputted from the arithmetic circuit 182 in FIG.

Returning to FIG. 11, first, the read address output from the arithmetic circuit 182 is the memory 161°167.173.
, and the data at that address is input to each 1 coefficient unit 1.
62, 168, 174, and the data of the next address is input to 2 coefficient multipliers 163, 169, 175.

The input data is multiplied by a coefficient of 1 and 2 to a predetermined mixing ratio, and is input to adders 164, 170.degree. 176. Adders 164, 170, 176 add input data, and the added data is output to output terminals 165, 1.
71,177.

In this way, data is mixed, and the mixed data is
This is output as corrected data after conversion, and the manner in which this correction is performed will be specifically explained using actual data.

FIG. 13 is a waveform diagram for explaining the operation of data conversion circuit 202 shown in FIG. 11.

In FIG. 13, (a) shows a horizontal synchronization signal obtained from an input video signal, and (b) shows a 4fsc clock locked to burst.

Assuming that the data sampled at clock (b) is at the point of the arrow shown in (C), the video signal input at this time is 912 clocks at clock (b) (910 clocks for standard), which is non-standard. This is the signal.

Therefore, data obtained by sampling the input video signal (c
) to the standard horizontal period length (d), the sample clock (b
) is the data located in between.

This occurs because the input video signal is sampled with a 4 fsc clock synchronized with the burst regardless of the input video signal, so it is necessary to convert the data.

If the sampled data is as shown in (e), then the final data to be obtained is set as (f). The length (L) of the input data is 912 in the length counter 180.
It is counted as a clock and input to the arithmetic circuit 182.

The arithmetic circuit 182 calculates length information (
L) is multiplied by 1/910 in the multiplier 304, so the result is (912/910).

Since the sample phase of the output sample X(0) matches that of the input sample D(0), it becomes X(0) as it is.
= D (0).

The output sample X(1) is the first sample, so
Multiplier 305 multiplies (912/910) by 1, giving (
912/910) are obtained. The integer part of the obtained value is extracted by the integer extractor 306, and the address 1 is
is output as

Also, in the subtracter 307, the integer part of 1 is subtracted from (912/9 t O) to obtain (2/910), and 1 is added to the coefficient.
is output as Furthermore, if the coefficient is 1, the subtracter 301
is subtracted from 1 to obtain (908/910), which is output as 2 as a coefficient.

Therefore, the desired output sample X(1) is X(1)=
(980/910)D (1)÷(2/910)D
(2) becomes.

Next, in order to find the X (n)th largest sample,
■ is defined as follows. That is, I = integer part (n91
2/910) From this, X (n) is X (n) - (n912/910-1)D (1) ± (
-1(n912/910-1)D (T+1).

As described above, even if the input video signal deviates from the standard horizontal period length, by converting the data, it can be converted into a standard signal having the standard horizontal period length.

Next, the arithmetic circuit 18 of the data conversion circuit 202 in FIG.
2 (FIG. 12) using a CPU (Central Processing Unit) or the like will be described.

FIG. 14 shows a flowchart of operations performed by the CPtJ when the arithmetic circuit 182 of FIG. 12 is performed by a CPU. In the figure, when the length information (L) from the length counter 180 and the count value (N) from the 910 counter 181 are input, the CPU first calculates (L/910).
Calculate. Next, (L/910) is multiplied by the count value N.

Then, the integer part A and the decimal part B of (LN/910) are calculated. The integer part A obtained here becomes the memory read address. The decimal part B is 1 for the coefficient and 2 for the coefficient.
is obtained from (1-B).

As described above, the reading address of the input signal and the coefficient Kl, which indicates the mixing ratio, can also be set using the CPU. However, this processing must be done within one clock after input, or if it cannot be processed within one clock, it must be a vibe line process that is always delayed by several clocks.

Next, a sixth embodiment of the present invention will be described.

FIG. 15 is a block diagram showing a sixth embodiment of the present invention, in which the same parts as in FIG. 1 and FIG. 1O are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 10 operate in the same way, the explanation will be omitted.

FIG. 15 differs from the embodiment in FIG. 10 in that a data conversion circuit 202 is placed in front of the frame comb circuit 104, and its operation is almost the same as that in the embodiment shown in FIG. , even if the data input to the data conversion circuit 202 is a non-standard signal, it is converted to the length of the standard signal.
There is an advantage that the frame comb circuit 104 can be operated at all times.

Next, a seventh embodiment of the present invention will be described.

FIG. 16 is a block diagram showing a seventh embodiment of the present invention.
1, a synchronous separation circuit 112 is arranged,
The same parts as in FIGS. 1 and 15 are given the same reference numerals.

Next, the circuit operation will be explained, but since the same parts as in FIGS. 1 and 15 operate in the same way, the explanation will be omitted.

In this embodiment (FIG. 16), the horizontal synchronization signal input to the data conversion circuit 202 is directly input from the synchronization separation circuit 112. The input horizontal synchronization signal is separated from the input signal regardless of whether it is standard or non-standard.
As in FIG. 10, correct data conversion can always be performed.

Here, a specific example of the synchronization separation circuit 112 will be explained using FIG. 17.

FIG. 17 shows a specific example of a synchronous separation circuit.
0 is an input terminal, 203 is a noise removal circuit, 321 is an output terminal, and the same parts as in FIG. 1 are given the same reference numerals.

Next, circuit operation will be explained.

In FIG. 17, the video signal input to the input terminal 320 is separated into horizontal synchronization signals by the synchronization separation circuit 112. The horizontal synchronization signals separated by five are input to the noise removal circuit 203.

The noise removal circuit 203 includes a phase comparator 11 similar to that shown in the line lock clock generation circuit 111 of FIG.
3. Low pass filter (LPF) 114, voltage controlled oscillator (V
CO) 116.

This noise removal circuit performs PLL operation and only passes frequencies around the frequency of the input horizontal synchronization signal, so
Noise components included in other bands are removed. In this way, a horizontal synchronization signal from which noise has been removed is obtained at the output terminal 321.

Note that the synchronization separation circuit 112 described below may be provided with a noise removal function as in this specific example.

Next, an eighth embodiment of the present invention will be described.

FIG. 18 shows an eighth embodiment of the present invention.
The data conversion circuit 202 in FIG. 6 is arranged after the frame (rectangular circuit 104), and the same parts as in FIGS. 1 and 16 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 16 operate in the same way, the explanation will be omitted.

In the eighth embodiment (Fig. 18), the seventh embodiment (Fig. 16)
Similarly to FIG. 1, data conversion can be realized by the horizontal synchronization signal output from the synchronization separation circuit 112.

However, when a non-standard signal is used, control is required to turn off the operation of the frame comb circuit 104.

Next, a ninth embodiment of the present invention will be described.

FIG. 19 shows a ninth embodiment of the present invention.
The data conversion circuit 202 in FIG. 6 is removed and a new data modulation circuit 204 is placed after the Y/C separation circuit 102, and the same components as in FIG. 1 and FIG. It is attached.

Next, the operation of the circuit will be explained. Since the same parts as in FIG. 1 and FIG. 16 operate in the same way, the explanation will be omitted.

In FIG. 19, the luminance signal and carrier color signal output from the Y/C separation circuit 102 are input to a data modulation circuit 204.

The signal input to the data modulation circuit 204 is converted in the same manner as the data conversion circuit so that the length of one horizontal period matches the standard length, but the time axis is corrected for the carrier color signal. If this happens, the frequency of the color subcarrier fsc will fluctuate.

Therefore, after the time axis of the data is corrected, frequency conversion is performed so that the frequency of the carrier color signal matches the reference frequency.

As a result, the time axis of the luminance signal is corrected, and the carrier color signal is output as a signal with the time axis and frequency corrected.
The subsequent processing can be performed in the same way as for standard signals.

Next, a specific example of the data modulation circuit 204 will be described.

FIG. 20 shows a specific circuit example of the data modulation circuit 204 in FIG. 19, and shows two types of circuits (a
), (b).

In FIG. 20(a), 401a is a data conversion unit;
02 is a frequency conversion unit, 335 is a frequency conversion circuit, 339
1 is a voltage controlled oscillator (VCO), 360 is a carrier color signal input terminal, 361 is an output terminal, and the same parts as in FIG. 11 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIG. 11 operate in the same way, the explanation will be omitted.

The carrier color signal inputted from the carrier color signal input terminal 360 is outputted after the time axis is corrected by the data converter 401a, and is inputted to the frequency converter 402.

The frequency converter 402 includes a frequency converter circuit 335 and a voltage controlled oscillator (VCO) 339, and the data converter 4
The signal output from 01a is input to the frequency conversion circuit 335.

Since the time axis of the signal input to the frequency conversion circuit 335 has been corrected by the data conversion unit 401a, the frequency of the color subcarrier wave has deviated from the standard value.

Therefore, the time axis correction signal obtained from the arithmetic circuit 182 is input to the voltage controlled oscillator (VCO) 339.

The voltage controlled oscillator (VCO) 339 determines a frequency for correction using the input time axis correction signal. The correction frequency signal is input to a frequency conversion circuit 335 to compensate for the frequency deviation of the carrier color signal.

In this way, as outputs, a luminance signal whose time axis is corrected and a carrier color signal whose time axis and frequency are corrected are obtained.

Next, a second specific example of the data modulation circuit 204 in FIG. 19 will be described.

In FIG. 20(b), 403 is a frequency converter, 34
0 is a burst sampling circuit, 341 is a comparator, and 342 is a reference oscillator, and the same parts as in FIG. 11 and FIG. 20(a) are given the same reference numerals.

Next, the circuit operation will be explained.
The same parts as in FIG. 0 (a) operate in the same way, so their explanation will be omitted.

The frequency converter 402 in FIG. 20(a) is a system that performs correction based on the time axis correction information output from the arithmetic circuit 182 of the data converter 401a, but the frequency converter 402 in FIG. 20(b)
In this specific example, the data is output from the data conversion unit 401a,
The carrier color signal that has passed through the frequency conversion circuit 335 is input to the burst sampling circuit 340.

The input burst signal of the carrier color signal is sent to the comparator 341.
sent to. A reference oscillator 342 is connected to the other input of the comparator 341 and oscillates a color subcarrier signal fsc, which is input to the comparator 341 .

The comparator 341 detects and outputs how much the extracted burst signal differs from the reference color subcarrier frequency. Its output is input to a voltage controlled oscillator (VCO) 339,
Frequency conversion circuit 3 oscillates a frequency corresponding to the frequency deviation
Output to 35. As a result, a luminance signal whose time axis has been corrected and a carrier color signal whose time axis and frequency have been corrected are obtained as outputs.

In the specific example shown in FIG. 20(b), feedback control is applied so that the output frequency is equal to the reference color subcarrier frequency, so that the output frequency deviates from the reference color subcarrier frequency. Nothing happens.

Next, a tenth embodiment of the present invention will be described.

FIG. 21 shows a 10th embodiment of the present invention, in which the TBC circuit 201 in FIG. 9 is removed and Y
A conversion TBC circuit 205 is arranged after the /C separation circuit 102, and the same parts as in FIGS. 1 and 9 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 9 operate in the same way, the explanation will be omitted.

In FIG. 21, the luminance signal and carrier color signal output from the Y/C separation circuit 102 are input to a conversion TBC circuit 205.

Regarding the input signals, the luminance signal is subjected to time axis correction, and the carrier color signal is subjected to time axis and frequency correction. This operation will be explained in detail using FIG. 22.

FIG. 22(a) shows a specific example of the conversion TBC circuit 205, in which 404a is a TBC section, 330 is a luminance signal input terminal, 333 is a carrier color signal input terminal, 331.334
is the waveform memory.

332 is a luminance signal output terminal, 336 is a carrier color signal output terminal, 337 is a write clock input terminal, and 338 is a read clock input terminal.
The same parts as in a) are given the same reference numerals.

Next, the circuit operation will be explained, but since the same parts as in FIG. 8 and FIG. 20(a) operate in the same way,
The explanation will be omitted.

In FIG. 22(a), the luminance signal input from the luminance signal input terminal 330 is input to the TBC section 404a,
The same operation as explained in FIG. 8 is performed, and a signal whose time axis has been corrected is obtained at the luminance signal output terminal 332.

The carrier color signal inputted from the carrier color signal input terminal 333 is inputted to the TBC section 404a, and the time axis is corrected and outputted like the luminance signal, and then inputted to the frequency conversion section 402.

The frequency converter 402 uses the waveform memory 331 or 334
The voltage controlled oscillator (VC○
) 339 is controlled, and its output unit produces the output shown in FIG.
The same operation as in a) is performed to convert the frequency that fluctuates due to the time axis correction of the input signal to the original frequency.

As a result, a carrier color signal whose time axis and frequency have been corrected is obtained at the carrier color signal output terminal 336.

In this way, the time axis and frequency of the input signal can be corrected.

FIG. 22(b) shows a second specific example of the conversion TBC circuit 205, and the same parts as in FIG. 8, FIG. 20(b), and FIG. 22(a) have the same reference numerals. It is attached.

The circuit operation is performed using the TBC section 404a and the second TBC section in FIG. 22(a).
This is the same as the combination of the frequency converter 403 in FIG. 0(b).

This also allows the time axis and frequency of the input signal to be corrected. Further, as in FIG. 20(b), since the output signal burst frequency is operated to match the reference color subcarrier frequency, there is no frequency deviation.

Next, an eleventh embodiment of the present invention will be described.

FIG. 23 shows an eleventh embodiment of the present invention, in which the data conversion circuit 202 and color demodulation circuit 10 in FIG.
3 is removed, and instead a demodulation data conversion circuit 206 is placed after the Y/C separation circuit 102, and the same parts as in FIGS. 1 and 16 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 16 operate in the same way, the explanation will be omitted.

In FIG. 23, the luminance signal and carrier color signal output from the Y/C separation circuit 102 are transferred to the demodulation data conversion circuit 206.
is input. The input luminance signal operates in the same manner as the data conversion circuit 202 described in FIG. 11, and a luminance signal whose time axis has been corrected is obtained.

On the other hand, the carrier color signal is subjected to time axis correction and color demodulation.
The time axis is corrected by operating in the same manner as the data conversion circuit 202 described in FIG. 1, and color demodulation is performed using the color subcarrier whose time axis has been converted, thereby obtaining a color difference signal.

A specific example of the demodulation data conversion circuit 206 in FIG. 23 will now be described.

FIG. 24(a) shows a specific example of the demodulation data conversion circuit 206, in which 406 is a color demodulation section, 350 is a color subcarrier input terminal for color demodulation, and FIGS.
The same parts as in FIG. 0 (a) are given the same reference numerals.

Next, we will explain the circuit operation.
The same parts as in Figure (a) operate in the same way, so the explanation will be omitted.

In FIG. 24(a), the color subcarrier signal inputted from the color demodulation color subcarrier input terminal 350 is transmitted to the color demodulation section 4.
The signal is input to the frequency conversion circuit 335 of 06.

The frequency of the input color subcarrier signal is modulated according to the time axis correction information obtained from the data converter 401a. The modulated color subcarrier signal is input to the color demodulation circuit 103, which demodulates the carrier color signal input from the other side.

At this time, the carrier color signal input from the input terminal 350 is
Since demodulation is performed using a color subcarrier that has undergone frequency correction similar to the frequency shift changed by time axis correction, correct color demodulation can be performed.

As a result, color difference signals whose time bases have been corrected and whose color has been correctly demodulated are obtained at the output terminals 336 and 337.

Next, a second specific example of the demodulated data conversion circuit 206 in FIG. 23 will be described.

FIG. 24(b) shows a second specific example of the demodulation data conversion circuit 206, in which 401b is a data conversion section provided with three systems of data conversion memories, 407 is a color demodulation section,
The same parts 22 as in FIG. 11, FIG. 20(b) and FIG. 24(a) are given the same reference numerals.

Next, the circuit operation will be explained with reference to FIG.

The same parts as those in FIG. 20(b) and FIG. 24(a) operate in the same way, so the explanation will be omitted.

In FIG. 24(b), the color subcarrier input from the color demodulation color subcarrier input terminal 350 is transmitted to the data converter 40.
The time axis is corrected in the same way as the luminance signal and carrier color signal input in step 1b.

The color subcarrier whose time axis has been corrected is input to the color demodulation circuit 103 of the color demodulation section 4o7. The color demodulation circuit 103 includes
A carrier color signal whose time axis has been corrected is input as an input, and color demodulation is performed.

At this time, since time axis correction has been performed on both the carrier color signal and the color subcarrier, color demodulation is performed correctly.

In this way, the output terminals 336 and 337 receive color difference signals whose time bases have been corrected and whose color has been correctly demodulated.

Next, a twelfth embodiment of the present invention will be described.

FIG. 25 shows a twelfth embodiment of the present invention, in which the conversion TBC circuit 205 and color demodulation circuit 10 in FIG.
3 is removed and a demodulation TBC circuit 207 is newly placed after the Y/C separation circuit 102, and the same parts as in FIGS. 1 and 21 are given the same reference numerals.

Next, the operation of the circuit will be explained, but since the same parts as in FIGS. 1 and 21 operate in the same way, the explanation will be omitted.

In FIG. 25, the luminance signal and carrier color signal output from the Y/C separation circuit 102 are input to the mTBc circuit 207. The luminance signal is subjected to time axis correction by the circuit described in FIG. 8 and output.

Regarding the carrier color signal, time axis correction is performed in the circuit described in FIG. 8, and color demodulation is further performed to output a color difference signal. This operation will be explained in detail using FIG. 26.

FIG. 26(a) shows a specific example of the TBc circuit 207, and the same parts as in FIGS. 8, 22(a), and 24(a) are denoted by the same reference numerals. is attached.

Next, the circuit operation will be explained, and FIGS. 8 and 22 (
The same parts as in a) and FIG. 24(a) operate in the same way, so their explanation will be omitted.

In this specific example (Fig. 26a), the luminance signal is as shown in Fig. 22(a).
In the same manner as above, the time axis is corrected in the TBC unit 404a.

First, the time axis of the carrier color signal is corrected in the TBC section 404a as in FIG. 22(a). After that, color demodulation section 4
The signal is input to the color demodulation circuit 103 of No. 06, and the same operation as the color demodulation shown in FIG. 24(a) is performed. As a result, the time axis is corrected, and a color difference signal whose color is demodulated is obtained.

FIG. 26(b) shows a second specific example of the demodulating TBC circuit 207, and 404b is a TBC section provided with three systems of TBC memories. The same parts as in FIG. 24(b) are given the same reference numerals.

Next, the circuit operation will be explained, and FIGS. 8 and 22 (
The same parts as those in b) and FIG. 24(b) operate in the same way, so their explanation will be omitted.

In this specific example (FIG. 25b), the color subcarrier signal for color demodulation is subjected to time axis correction in the TBC unit 404b in the same way as the carrier color signal is processed in the TBC unit 404b. As a result, color demodulation is performed in the same manner as in FIG. 24(b), the time axis is corrected in the output, and a correctly demodulated color difference signal is obtained.

(Effects of the Invention) According to the present invention, in a television receiver, data as an input video signal is processed not only when the input video signal is a standard signal but also when the input video signal is a non-standard signal. By interfacing and data conversion, signal processing can be performed in an optimal manner, and as a result, the advantage is that high-quality screen display is possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional example of a clock generator in a television receiver, and Fig. 3 is the Y/C separation in Fig. 1. FIG. 4 is a circuit diagram showing a specific example of the interface circuit in FIG. 1; FIG. 5 is a circuit diagram showing another output circuit example of the line lock clock generation circuit in FIG. 1. Figures 6 and 7 are block diagrams showing circuit configurations of other embodiments of the present invention, respectively.
FIG. 8 is a circuit diagram showing a specific example of the TBC circuit in FIG. 7, FIGS. 9 and 10 are block diagrams showing circuit configurations of other embodiments of the present invention, and FIG. A circuit diagram showing a specific example of a data conversion circuit, FIG. 12 is a circuit diagram showing a specific example of an arithmetic circuit in 1111F, FIG. 13 is a waveform diagram for explaining the operation of the data conversion circuit, and FIG. 14 is a data conversion circuit. A flowchart in the case where the arithmetic circuit of the conversion circuit is realized by an arithmetic processing device, FIGS. 15 and 16 are block diagrams showing circuit configurations of further embodiments of the present invention, and FIG. 17 shows noise in the synchronization separation circuit. Block diagram showing a specific example when equipped with a removal function, Fig. 18, 3rd 1
9 is a block diagram showing a circuit configuration of still another embodiment of the present invention, FIG. 20 is a circuit diagram showing a specific example of the data modulation circuit in FIG. 19, and FIG. 21 is a block diagram showing a circuit configuration of still another embodiment of the present invention. 22 is a circuit diagram showing a specific example of the conversion TBC circuit in FIG. 21; FIG. 23 is a block diagram showing the circuit structure of still another embodiment of the present invention; 24 is a circuit diagram showing a specific example of the demodulation data conversion circuit in FIG. 23, FIG. 25 is a block diagram showing a circuit configuration of still another embodiment of the present invention, and FIG.
FIG. 6 is a circuit diagram showing a specific example of the first JITBc circuit in FIG. 25. Explanation of symbols 101...Input terminal, 102...Y/C separation circuit,
103... Color demodulation circuit, 104... Frame comb circuit, 105... Interface circuit, 106...
Double speed conversion circuit, 110... Hurst clock clock generation circuit, 111... Line lock clock generation circuit,
121...Standard/non-standard signal detection circuit, 9...Synchronization signal generation circuit, 201...TBC circuit, 202...
Data conversion circuit, 204...Data modulation circuit, 205
. . . conversion TBC circuit, 206 . . . demodulation data circuit,
207...Demodulation TBC circuit. Agent Patent Attorney Akio Namiki Φ nI'3 in Figure 2, Figure 3, Figure 4 = Figure 8 0 ■ a ■ O○ Figure 11 202 (Data'l$!Circuit-) 2 ．． -INNO--! 1st
7 Figure 1-, , , ”
ω G') o. Fig. 20 (a) Data modulation rotation 204 Fig. 20 (b) Puku Henrou U mouth signature - 204 Fig. 22 Collect TBC[] RakufiTBcOl Fig. 26 1 Inquiry ITBc [] Takumi 207

Claims (1)

[Claims] 1. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, it is output as the video signal. a first luminance signal/chrominance signal separation means (102) that separates the first luminance signal and a color signal;
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
When a video signal is output from the first separation means (102), this is input and subjected to luminance signal and color signal separation processing in the time axis direction and two-dimensionally, and then output. a second luminance signal/chrominance signal separation means (104) that outputs without performing such processing; and a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple, which is inputted with the output from the second separation means (104). double-speed converting means (106) for converting the input video signal into a color burst signal and outputting the same; Demodulation means (103) and second
a first clock generating means (110) for supplying the luminance signal and color signal separating means (104) of the input video signal; and a second clock generating means (110) for generating a second clock synchronized with a synchronization signal included in the input video signal. 111)
and a synchronization signal generation means (9) which receives the second clock from the second clock generation means (111) and generates and outputs a synchronization signal, and the input video signal is a standard signal conforming to a predetermined standard. detection means (121) for detecting whether the signal is a non-standard signal, which is not necessarily true; (102) and a second luminance signal/chrominance signal separation means (104) as described above, and when the detection result is a standard signal, the first clock switching means (120) for supplying a clock and for supplying the second clock to the double speed conversion means (106) when the input video signal is a non-standard signal; 2
In the circuit system up to the luminance signal/chrominance signal separation means (104), the signal processed by the first clock is adapted to be processed by the second clock in the double speed conversion means (106). interface means (105) for performing data conversion on the output signal of the second luminance signal color signal separation means (104) and inputting the data to the double speed conversion means (106); television receiver. 2. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal is output as the video signal. a color signal separation means (102), and the first separation means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
and a second luminance signal/color signal separation means (104) that performs luminance signal/color signal separation processing on the input signal in the time axis direction and two-dimensional direction and outputs the resultant signal, and from the second separation means (104). double speed converting means (106) for converting the output of the input into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; and generating a first clock synchronized with the color burst signal included in the input video signal. a first clock generating means (110) for supplying the first luminance signal/color signal separating means (102) and the color demodulating means (103); a second clock generating means (111) which generates a clock and supplies it to the second luminance signal/chrominance signal separating means (104) and the double speed converting means (106); ); and a synchronization signal generating means (9) for generating and outputting a synchronization signal by receiving a second clock from the input video signal; The detection means (121) for detecting whether the detection result is a standard signal and the operation of the first luminance signal/color signal separation means (102) are controlled as described above depending on whether the detection result is a standard signal or a non-standard signal. an operation control means; when the detection result is a standard signal, the first clock is supplied to the double speed converting means (106); when the detection result is a non-standard signal, the double speed converting means (106);
clock switching means (1) for supplying the second clock to
20) and when the input video signal is a non-standard signal,
The signal processed by the first clock in the circuit system up to the color demodulating means (103) is compatible with the processing by the second clock after the second luminance signal/color signal separating means (104). After performing data conversion of the signal, the second luminance signal/chrominance signal separating means (104)
and the second luminance signal color signal separation means (104
) interface means (105) for performing luminance signal and color signal separation processing in the time axis direction and two-dimensionally. 3. The television receiver according to claim 1 or 2, wherein the second clock generation means (111) includes a synchronization separation circuit (112) that separates and outputs a horizontal synchronization signal from the input video signal; a phase comparator (113) that compares the phases of the output of the synchronization separation circuit (112) and the output of the frequency division circuit (118) described later and outputs the difference;
a low-pass filter (114) that extracts and outputs a low-frequency component from the output of 3), and a clock output from the first clock generating means (110) and the low-pass filter (114) when the input video signal is a standard signal. ), an adder (115) that adds the outputs of the adder (115)
), the voltage controlled oscillator (116) oscillates at a frequency corresponding to the added output as a control voltage, and uses the oscillation output as the second clock, and the voltage controlled oscillator (116)
The oscillation output from the phase comparator (1
13). A television receiver comprising: the frequency dividing circuit (118). 4. The television receiver according to claim 1 or 2, wherein the interface means (105) is a digital signal that converts a digital signal, which is an input signal thereof, into an analog signal in synchronization with the first clock and outputs the analog signal. /analog converter (141, 145, 149), and an analog/digital converter (142, 146, 150) that converts the analog signal into a digital signal in synchronization with the second clock and outputs it as an output signal. A television receiver comprising: 5. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal is output as the video signal. a color signal separation means (102), and the first separation means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
and a second luminance signal/color signal separation means (104) that performs luminance signal/color signal separation processing on the input signal in the time axis direction and two-dimensional direction and outputs the resultant signal, and from the second separation means (104). double speed converting means (106) for converting the output of the input into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; and generating a first clock synchronized with the color burst signal included in the input video signal. The first luminance signal color signal separation means (102), color demodulation means (103), second luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110)
and second clock generation means (111) that generates a second clock synchronized with the synchronization signal included in the input video signal.
a synchronization signal generating means (9) that receives the first clock and generates and outputs a synchronization signal, and determines whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that does not necessarily conform to such a standard. The detection means (121) for detecting whether the detection result is a standard signal and the operation of the first luminance signal/color signal separation means (102) are controlled as described above depending on whether the detection result is a standard signal or a non-standard signal. an operation control means; when the input video signal is a non-standard signal, the first
interface means (20) as a time axis correction means for correcting the time axis of the signal processed by the clock of
1) A television receiver comprising: 6. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and outputted, but when it is a standard signal, the first luminance signal is outputted as the video signal. a color signal separation means (102), and the first separation means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
When a video signal that is a standard signal is input, it is output after performing luminance signal and color signal separation processing in the time axis direction and two-dimensionally, but otherwise it is output without performing such processing. a second luminance signal/chrominance signal separation means (104) that converts the output from the second separation means (104) into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple, and outputs the signal. means (106); generating a first clock synchronized with a color burst signal included in the input video signal to separate the first luminance signal and color signal from the first luminance signal and color signal separating means (102), color demodulating means (103), and second clock signal; luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110)
and second clock generation means (111) that generates a second clock synchronized with the synchronization signal included in the input video signal.
a synchronization signal generating means (9) that receives the first clock and generates and outputs a synchronization signal, and determines whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that does not necessarily conform to such a standard. The detection means (121) for detecting whether the detection result is a standard signal and the operation of the first luminance signal/color signal separation means (102) are controlled as described above depending on whether the detection result is a standard signal or a non-standard signal. an operation control means; and when the input video signal is a non-standard signal, a time axis of a signal processed by the first clock in a circuit system up to the second luminance signal/chrominance signal separation means (104); A television receiver comprising: interface means (201) serving as a time axis correction means for performing correction and supplying the corrected information to the speed converting means (106) and thereafter. 7. In the television receiver according to claim 5 or 6, the interface means as time axis correction means is written with a video signal according to the second clock and read out the video signal according to the first clock. A television receiver comprising a storage device (372). 8. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal is output as the video signal. a color signal separation means (102), and the first separation means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
When a video signal that is a standard signal is input, it is output after performing luminance signal and color signal separation processing in the time axis direction and two-dimensionally, but otherwise it is output without performing such processing. a second luminance signal/chrominance signal separation means (104) that converts the output from the second separation means (104) into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple, and outputs the signal. means (106); generating a first clock synchronized with a color burst signal included in the input video signal to separate the first luminance signal and color signal from the first luminance signal and color signal separating means (102), color demodulating means (103), and second clock signal; luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110)
second clock generation means (111) for generating a second clock synchronized with a synchronization signal included in the input video signal;
a synchronization signal generating means (9) that receives the first clock and generates and outputs a synchronization signal, and determines whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that does not necessarily conform to such a standard. a detection means (121) for detecting whether the detection result is a standard signal or a non-standard signal, and the first and second luminance signal/chrominance signal separation means (
102, 104) as described above; and when the input video signal is a non-standard signal, the circuit system up to the second luminance signal/chrominance signal separation means (104) comprises: Data conversion of the signal processed by the first clock into correct data is performed, and the double speed conversion means (
106) Interface means (202) as data conversion means for supplying data thereafter; A television receiver comprising: 9. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal is output as the video signal. a color signal separation means (102), and the first separation means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
and a second luminance signal/chrominance signal separation means (104) that performs luminance signal/color signal separation processing on the input signal in the time axis direction and two dimensions and outputs the resultant signal, and from the second separation means (104). a double-speed converting means (106) for converting the input output into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; and generating a first clock synchronized with the color burst signal included in the input video signal. The first luminance signal color signal separation means (102), the color demodulation means (103), the second luminance signal color signal separation means (104) and the double speed conversion means (
106) first clock generation means (110)
and second clock generation means (111) that generates a second clock synchronized with the synchronization signal included in the input video signal.
a synchronization signal generating means (9) that receives the first clock and generates and outputs a synchronization signal, and determines whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that does not necessarily conform to such a standard. The detection means (121) for detecting whether the detection result is a standard signal and the operation of the first luminance signal/color signal separation means (102) are controlled as described above depending on whether the detection result is a standard signal or a non-standard signal. an operation control means; when the input video signal is a non-standard signal, the first
The second luminance signal/chrominance signal separating means (1) converts the signal processed by the clock into correct data.
04) A television receiver comprising: interface means (202) as a data conversion means for supplying data thereafter; 10. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal color is output as the video signal. a signal separating means (102); and the first separating means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
and a second luminance signal/color signal separation means (104) that performs luminance signal/color signal separation processing on the input signal in the time axis direction and two-dimensional direction and outputs the resultant signal, and from the second separation means (104). double speed converting means (106) for converting the output of the input into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; and generating a first clock synchronized with the color burst signal included in the input video signal. The first luminance signal color signal separation means (102), color demodulation means (103), second luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110);
a synchronization separating means (112) for separating and outputting a synchronizing signal included in the input video signal; and a synchronizing signal generating means (9) for receiving the first clock and generating and outputting a synchronizing signal; detection means (121) for detecting whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that is not necessarily such; and when the detection result is a standard signal and when the detection result is a non-standard signal. and an operation control means for controlling the operation in the first luminance signal color signal separation means (102) as described above, and when the input video signal is a non-standard signal, up to the color demodulation means (103). In the circuit system of
The second luminance signal/chrominance signal separating means (1) converts the signal processed by the clock into correct data.
04) A television receiver comprising: interface means (202) as a data conversion means for supplying data thereafter; 11. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal color is output as the video signal. a signal separating means (102); and the first separating means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
When a video signal that is a standard signal is input, it is output after performing luminance signal and color signal separation processing in the time axis direction and two-dimensionally, but otherwise it is output without performing such processing. a second luminance signal/chrominance signal separation means (104) that converts the output from the second separation means (104) into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple, and outputs the signal. means (106); generating a first clock synchronized with a color burst signal included in the input video signal to separate the first luminance signal and color signal from the first luminance signal and color signal separating means (102), color demodulating means (103), and second clock signal; luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110);
a synchronization separating means (112) for separating and outputting a synchronizing signal included in the input video signal; and a synchronizing signal generating means (9) for receiving the first clock and generating and outputting a synchronizing signal; detection means (121) for detecting whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that is not necessarily such; and when the detection result is a standard signal and when the detection result is a non-standard signal. and an operation control means for controlling the operations in the first luminance signal color signal separation means (102) and the second luminance signal color signal separation means (104) as described above, and the input video signal is a non-standard signal. At some point, data conversion of the signal processed by the first clock into correct data is performed in the circuit system up to the second luminance signal/chrominance signal separation means (104), and the double speed conversion means (104)
106) Interface means (202) as data conversion means for supplying data thereafter; A television receiver comprising: 12. The television receiver according to claim 8, 9, 10 or 11, wherein the interface means as the data conversion means includes a storage device (161, 16) that stores the input signal as data.
7, 173), and a mixing and adding circuit (7, 173) that creates and outputs correct data by mixing at least two pieces of time-series data read from the storage device at a given mixing ratio.
162, 163, 168, 169, 174, 175, 1
64, 170, 176), and a mixing ratio calculation circuit (180, 181, 182) which calculates the mixing ratio from the horizontal synchronization signal included in the input video signal and the first clock and supplies it to the mixing and adding circuit. ) A television receiver characterized by comprising: 13. In the television receiver according to claim 12, the mixing ratio calculation circuit counts the number of the first clocks in one cycle of the horizontal synchronization signal included in the input video signal as length information L. First counter (18
0), a second counter (181) that counts which clock in one cycle of the horizontal synchronization signal the input first clock is, and a first clock in one cycle of the correct horizontal synchronization signal. A television receiver comprising: an arithmetic circuit (182) that calculates the mixing ratio given a constant that is the number of clocks and count values of the first and second counters. 14. The television receiver according to claim 13, wherein the arithmetic operation circuit receives the length information L from the first counter (180), multiplies it by one of the constant, and outputs the result. a second multiplier (305) that performs multiplication between the output of the first multiplier (304) and the count value of the second counter (181); an integer part extractor (306) that extracts the integer part from the output of the multiplier (305) and outputs it; and an integer part extractor (306) that subtracts the integer part from the output of the second multiplier (305), extracts and outputs the decimal part. and a second subtracter (310) that subtracts the output of the first subtracter (307) from a numerical value of 1 and outputs the result. John receiver. 15. The television receiver according to claim 13, wherein the arithmetic circuit is given the length information L from the first counter (180), multiplies the length information L by the constant, and outputs the result as a first value. a step of multiplying the first value by the count value of the second counter (181) and outputting the result as a second value; a step of extracting and outputting an integer part; a step of subtracting the integer part from the second value to output a decimal part; and a step of subtracting the decimal part from 1 of the numerical value and outputting it as a third value. 1. A television receiver comprising an arithmetic processing unit that executes. 16. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal color is output as the video signal. a signal separating means (102); and the first separating means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
and a second luminance signal/color signal separation means (104) that performs luminance signal/color signal separation processing on the input signal in the time axis direction and two-dimensional direction and outputs the resultant signal, and from the second separation means (104). double speed converting means (106) for converting the output of the input into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; and generating a first clock synchronized with the color burst signal included in the input video signal. The first luminance signal color signal separation means (102), color demodulation means (103), second luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110);
a synchronization separating means (112) for separating and outputting a synchronizing signal included in the input video signal; and a synchronizing signal generating means (9) for receiving the first clock and generating and outputting a synchronizing signal; detection means (121) for detecting whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that is not necessarily such; and when the detection result is a standard signal and when the detection result is a non-standard signal. and, when the input video signal is a non-standard signal, the first luminance signal/color signal separation means (102) controls the operation of the first luminance/color signal separation means (102) as described above. An interface means (204) as a data modulation means that performs data conversion and frequency conversion of the signal processed by the first clock in (102) to correct data and frequency, and supplies the converted data to the color demodulation means (103) and thereafter. ); A television receiver comprising: 17. The television receiver according to claim 16, wherein the interface means as the data modulation means includes a storage device (161, 16) that stores the input signal as data.
7), and a mixing and adding circuit (162,
163, 168, 169, 164, 170), and a mixing ratio calculation circuit (163, 168, 169, 164, 170) that calculates the mixing ratio from the horizontal synchronization signal included in the input video signal signal and the first clock and supplies it to the mixing and adding circuit. 180, 181, 182
), a frequency converter (335) that receives the output of the mixing and adding circuit, converts the frequency, and outputs the frequency converter (335), and the mixing ratio calculation circuit receives the mixing ratio data obtained by calculation, and uses it as a control voltage to convert the frequency to the frequency converter (335). a voltage controlled oscillator (339) for controlling the converter (335) so that its output frequency is the color subcarrier frequency. 18. The television receiver according to claim 16, wherein the interface means as the data modulation means includes a storage device (161, 16) that stores the input signal as data.
7), and a mixing and adding circuit (162,
163, 168, 169, 164, 170), and a mixing ratio calculation circuit (180) that calculates the mixing ratio from the horizontal synchronizing signal included in the input video signal and the first clock and supplies it to the mixing and adding circuit. , 181, 182), a frequency converter (335) that receives the output of the mixing and adding circuit, converts the frequency, and outputs the frequency converter (335);
a burst extractor (340) for extracting a burst signal from the output of the color subcarrier frequency oscillator (34);
2), and a voltage for comparing the color subcarrier frequency from the oscillator (342) and the output from the burst extractor (340) and controlling the output frequency of the frequency converter (335) so that they match. A television receiver comprising a controlled oscillator (339). 19. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal color is output as the video signal. a signal separating means (102); and the first separating means (
When a carrier color signal is output from 102), color demodulation means (103) receives and demodulates the carrier color signal and outputs a color difference signal.
and a second luminance signal/color signal separation means (104) that performs luminance signal/color signal separation processing on the input signal in the time axis direction and two-dimensional direction and outputs the resultant signal, and from the second separation means (104). double speed converting means (106) for converting the output of the input into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; and generating a first clock synchronized with the color burst signal included in the input video signal. The first luminance signal color signal separation means (102), color demodulation means (103), second luminance signal color signal separation means (104) and double speed conversion means (
106) first clock generation means (110);
and second clock generation means (111) that generates a second clock synchronized with the synchronization signal included in the input video signal.
a synchronization signal generating means (9) that receives the first clock and generates and outputs a synchronization signal, and determines whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that does not necessarily conform to such a standard. The detection means (121) for detecting whether the detection result is a standard signal and the operation of the first luminance signal/color signal separation means (102) are controlled as described above depending on whether the detection result is a standard signal or a non-standard signal. operation control means; when the input video signal is a non-standard signal, correct data and time axis data of the signal processed by the first clock in the first luminance signal/chrominance signal separation means (102); A television receiver comprising: interface means (205) as a data conversion and time axis correction means that performs conversion and time axis correction and supplies the data to the color demodulation means (103) and thereafter. . 20. The television receiver according to claim 19, wherein the interface means serving as data conversion and time axis correction means writes a video signal according to the second clock and reads out the video signal according to the first clock. storage devices (331, 334); a frequency converter (335) that receives the readout output of the storage device, converts the frequency, and outputs it; and a frequency converter (335) that receives control data from the storage device and uses it as a control voltage to convert the frequency converter(
a voltage controlled oscillator (339) for controlling the output frequency of the oscillator (335) to be at the color subcarrier frequency. 21. The television receiver according to claim 19, wherein the interface means as data conversion and time axis correction means is written with a video signal according to the second clock and reads out the video signal according to the first clock. storage devices (331, 334), a frequency converter (335) that receives the readout output of the storage device, converts the frequency and outputs it, and a burst extractor that extracts a burst signal from the output of the frequency converter (335). (
340) and a color subcarrier frequency oscillator (342);
a voltage controlled oscillator (339) that compares the color subcarrier frequency from the oscillator (342) with the output from the burst extractor (340) and controls the output frequency of the frequency converter (335) so that the two match; ) A television receiver characterized by comprising: 22. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal color is output as the video signal. a signal separating means (102); a second luminance signal/chrominance signal separating means (104) that performs luminance signal/chrominance signal separation processing on the input signal in the time axis direction and two-dimensionally and outputs the resultant signal; double speed converting means (106) for converting the input output from the separating means (104) into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; A first clock that generates a first clock and supplies it to the first luminance signal/color signal separation means (102), the second luminance signal/color signal separation means (104), and the double speed conversion means (106).
a clock generating means (110); a synchronization separation means (112) for separating and outputting a synchronization signal included in the input video signal; and a synchronization signal for generating and outputting a synchronization signal by receiving the first clock. generating means (9); detecting means (121) for detecting whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that is not necessarily such; and when the detection result is a standard signal; and an operation control means for controlling the operation in the first luminance signal/chrominance signal separation means (102) as described above when the signal is a non-standard signal; Interface means (206) as a demodulated data conversion means that receives the signal processed by the first clock, converts it into correct data, demodulates the color, and supplies it to the second luminance signal/color signal separation means (104). A television receiver comprising: 23. The television receiver according to claim 22, wherein the interface means as the demodulation data conversion means includes a storage device (161,
167) and at least 2 read from the storage device.
Mixing and adding circuit (16
2, 163, 168, 169, 164, 170), and a mixing ratio calculation circuit that calculates the mixing ratio from the horizontal synchronizing signal included in the input video signal and the first clock and supplies it to the mixing and adding circuit. (180, 181, 182
), and a color demodulation circuit (10
3) and a frequency converter (335) which receives the color subcarrier for color demodulation and converts the frequency of the color subcarrier using the mixing ratio data calculated by the mixing ratio calculation circuit and outputs the result.
) and the color demodulation circuit (1) that performs color demodulation using the frequency-converted color subcarrier from the frequency converter (335).
03) A television receiver comprising: 24. The television receiver according to claim 22, wherein the interface means as the demodulation data conversion means includes a first storage device (1) that stores the input signal as data.
61, 167), a second storage device (173) that receives the color subcarrier signal and stores it as data, and at least two pieces of time-series data read out from each of the first and second storage devices. A mixing and adding circuit (162,
163, 168, 169, 174, 175, 164, 1
70, 176), and a mixing ratio calculation circuit (1) which calculates the mixing ratio from the horizontal synchronization signal included in the input video signal and the first clock and supplies it to the mixing and adding circuit.
80, 181, 182), and a color demodulation circuit (103) which receives the carrier color signal which is the output of the mixing and adding circuit (168, 169, 170) corresponding to the first storage device, demodulates the color, and outputs it as a color difference signal. ), and the color demodulation circuit (103) that performs color demodulation using the frequency-converted color subcarrier signal that is the output of the mixing and adding circuit (174, 175, 176) corresponding to the second storage device; A television receiver comprising: 25. When the input video signal is a non-standard signal, it is separated into a luminance signal and a carrier color signal and output, but when it is a standard signal, the first luminance signal color is output as the video signal. a signal separating means (102); a second luminance signal/chrominance signal separating means (104) that performs luminance signal/chrominance signal separation processing on the input signal in the time axis direction and two-dimensionally and outputs the resultant signal; double speed converting means (106) for converting the input output from the separating means (104) into a progressive scanning signal having a horizontal frequency of an arbitrary desired multiple and outputting the same; A first clock that generates a first clock and supplies it to the first luminance signal/color signal separation means (102), the second luminance signal/color signal separation means (104), and the double speed conversion means (106).
clock generation means (110); and second clock generation means (111) for generating a second clock synchronized with a synchronization signal included in the input video signal.
a synchronization signal generating means (9) that receives the first clock and generates and outputs a synchronization signal, and determines whether the input video signal is a standard signal that conforms to a predetermined standard or a non-standard signal that does not necessarily conform to such a standard. The detection means (121) for detecting whether the detection result is a standard signal and the operation of the first luminance signal/color signal separation means (102) are controlled as described above depending on whether the detection result is a standard signal or a non-standard signal. an operation control means, and performs time axis correction of the signal processed by the first clock in the first luminance signal color signal separation means (102) and color demodulation from the signal to generate the second luminance signal. A television receiver comprising: interface means (207) serving as demodulation and time axis correction means for supplying a color signal after the color signal separation means (104). 26. In the television receiver according to claim 25, the interface means as demodulation and time axis correction means is written with a video signal according to the second clock and read out the video signal according to the first clock. storage devices (331, 334); a color demodulation circuit (103) that receives a carrier color signal, which is the readout output of the storage device, demodulates the color and outputs it as a color difference signal; and a color demodulation circuit (103) that receives a color subcarrier signal from the storage device. Color demodulation is performed using a frequency converter (335) that converts the frequency of the color subcarrier signal using the given correction data and outputs it, and the frequency-converted color subcarrier signal from the frequency converter (335). A television receiver comprising: the color demodulation circuit (103). 27. The television receiver according to claim 25, wherein the interface means as the demodulation and time axis correction means writes the video signal as data according to the second clock and reads out the data according to the first clock. a second storage device (351) into which the color subcarrier signal is written as data according to the second clock and the data is read out according to the first clock; A color demodulation circuit (103) inputs a carrier color signal read out from the first storage device, demodulates the color, and outputs it as a color difference signal, and a color subcarrier signal read out from the second storage device. A television receiver comprising: the color demodulation circuit (103) that performs color demodulation. 28. In the television receiver according to claim 10, 11, 16 or 22, the synchronous separation means (112) is attached with a noise removal means (203) for removing noise contained in the synchronous separation output. A television receiver characterized by: 29. The television receiver according to claim 28, wherein the noise removal means includes the synchronous separation means (112).
a phase comparator (113) which receives an output signal of the output signal and an oscillation output of a voltage controlled oscillation circuit (116) described later, compares the phases of the two, and outputs a difference signal; and the phase comparator (113).
a low-pass filter (114) that receives a difference signal from the input signal and outputs a low-frequency component;
the voltage controlled oscillation circuit (116) whose oscillation frequency is controlled using the output of the voltage controlled oscillation circuit (116) as a control voltage, and outputs the output of the voltage controlled oscillation circuit (116) as a synchronous separated output from which noise is removed. A distinctive television receiver. 30. The television receiver according to any one of claims 1 to 29, wherein the first luminance signal/chrominance signal separation means (102) separates the input video signal into a luminance signal and a carrier chrominance signal. A comb filter (1
33), when the input video signal is a standard signal, the input video signal is output as it is instead of the separated luminance signal, and only when the input video signal is a non-standard signal, the separated luminance signal is output. a changeover switch (131), when the input video signal is a standard signal, outputs the input video signal as it is instead of the separated carrier color signal, and only when it is a non-standard signal, outputs the separated carrier color signal. A television receiver comprising: a second changeover switch (134) that outputs a signal.