JPH04196693A - Video signal recording device - Google Patents

Abstract

PURPOSE:To correctly perform mutual adjustments between plural channel and to correctly adjust distortion of the recording system by providing a gradation reference signal insertion circuit. CONSTITUTION:A reference signal generation circuit 8 generates a synchronizing signal SYNC, a burst signal BURST and an identifying signal ID as well as a gradation reference signal REF at a prescribed timing and inputs them to signal adding circuits 9 and 15. As it can be seen from the above, a use if made of the reference signal which varies gradually and continues the same level signal. Therefore, even though there be a deviation in a sampling timing, the same level reference signals prior to or right after the sampling timing are recorded and reproduced. Thus, even though a jitter is generated, mutual adjustments between plural channel are correctly performed and the adjustment at the reproduction system against the recording system is correctly done as well.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a high-definition video tape recorder (HDV).
TR) device and other video signal recording and reproducing devices, and in particular, it is not affected by jitter in multi-channel video signal processing, improves variations in signal processing between channels, and improves distortion adjustment between FM modulation and FM demodulation. The present invention relates to a video signal recording device for recording video signals.

[Conventional technology]

HDVTR devices, etc., record video signals with FM modulation.
In a device that reproduces a video signal by performing M demodulation, a linearity shift (distortion) may occur between FM modulation on the recording side and FM demodulation on the reproduction side, and the reproduced image may deteriorate. When dubbing is repeated, distortion accumulates and the reproduced image deteriorates further.

In HDVTR devices, video signals are recorded and reproduced by dividing them into a plurality of channels, and therefore, due to variations in characteristics between the channels, recorded video signals between channels vary, resulting in large variations in reproduced image quality.

As one way to solve such problems.

A method has been proposed in which a ramp-shaped reference signal is inserted into the vertical blanking period of a video signal, and this ramp reference signal is referenced to adjust the reproduced image between channels and the reproduced image with respect to the recorded image ( For example, JP-A-61-
46681, see).

[Problem to be solved by the invention]

In the above method of applying a ramp reference signal, variations occur in the values of the sampled reference signal due to the deviation (jitter) of the sampling clock. Therefore, the recording reference signal fluctuates on the recording side and does not become a perfect ramp signal, and also cannot be sampled as a perfect ramp signal on the reproduction side. As a result, a problem has been encountered in that accurate adjustment (correction) cannot be performed even if correction is performed with reference to the reproduction lamp reference signal.

In view of the above circumstances, an object of the present invention is to provide a video signal recording device that is free from jitter dependence and can accurately adjust not only between channels but also the recording system and the reproduction system even if jitter occurs.

[Means to solve the problem]

In order to solve the above problem, the video signal recording device according to the present invention, which divides a video signal into multiple channels of video signals and records them on a recording medium, has a video signal recording device that divides a video signal into multiple channels of video signals and records them on a recording medium. Circuit means is provided for inserting a reference signal whose level signal is continuous and whose level signal changes stepwise.

(Function) By using a reference signal that changes in 9 steps and has successive signals of the same level instead of a predetermined video signal, even if there is a difference in sampling timing, the same level reference before and after the sampling timing is used. Signals are recorded and played back.

(Embodiment) An HDVTR device will be described as an embodiment of the video signal recording device of the present invention.

FIG. 1 shows a recording system REC that records video signals on a magnetic tape (not shown) via a rotating drum 25 of an HDVTR device.
The circuit configuration of the regenerated yarn PB for reproducing video signals from the magnetic tape via the one-rotation drum 25 is shown.

In the recording system REC, a baseband recording luminance signal Y is filtered by a low-pass filter (LPF) 1, converted from an analog signal to a digital signal by an analog/digital converter (ADC) 2, and applied to a digital signal processing circuit 7. Ru. Similarly, the baseband first and second recording color difference signals Pg and P are also as follows:
LPF3.5. The signal is then applied to the digital signal processing circuit 7 via the ADCs 4 and 6. The digital signal processing circuit 7 expands the recording luminance signal Y from the ADC 2 on the time axis, digitally filters the recording color difference signals Ps and P* from the ADCs 4 and 6, and divides them into two channel signals, A and B. Compress the divided channel signals in time. Furthermore, the digital signal processing circuit 7 converts the recording luminance signal Y and the recording color difference signals PI and PR into time-domain compression/expansion (TCI) signals of channels A and B, and further records them on a magnetic tape via the rotating drum 25. A predetermined shuffling operation is performed to format the signal. Channel A
The TCI signal is converted to an analog signal by the DAC 10 via the signal addition circuit 9.

Filtered by LPF II, analog signal processed by analog signal processing circuit 12, and F
M-modulated, amplified by the amplifier circuit 14, and rotated once by the drum 25.
recorded on magnetic tape via Channel B TCI
Similarly, the signal is also sent to the signal addition circuit 15. DAC16, LPF1
7. Analog signal processing circuit 18. FM modulation circuit 19. The signal is recorded on a magnetic tape via an amplifier circuit 20 and a rotating drum 25.

As shown in FIG. 2, the reference signal generation circuit 8 normally generates a synchronization signal 5YNC before the plurality of color difference signals C in the form of TCI signals and the plurality of luminance signals Y from the digital signal processing circuit 7.
Then, a burst signal BUR3T and an identification signal ID are inserted as necessary to complete an IH signal for one recording/reproduction.

The reference signal generation circuit 8 also generates the above-mentioned synchronization signals 5YNC,
In addition to the burst signal BUR3T and identification signal ID,
At a predetermined timing, a reference signal REF shown in FIG. 3 is generated instead of the color difference signal C and luminance signal Y in the TCI signal format shown in FIG. 2, and is applied to the signal addition circuits 9 and 15. The reference signal REF is a stepwise reference signal a0~ of n levels.
It consists of a++-1. Note that the signal addition circuits 9 and 15
Since the TCI signal from the digital signal processing circuit 7 is applied to the reference signal generating circuit 8, the reference signal R is applied from the reference signal generating circuit 8.
When EF is generated, the digital signal processing circuit 7 does not output the color difference signal C and the luminance signal Y in the TCI signal format. In order to adjust the timing of the digital signal processing circuit 7 and the reference signal generation circuit 8, the digital signal processing circuit 7 notifies the reference signal generation circuit 8 of the timing at which the color difference signal C and the luminance signal Y are not outputted using a signal S7. Therefore, when the reference signal generating circuit 8 does not receive the signal S7, the signal adding circuit 9.15 outputs the synchronizing signal 5YNC, the burst signal BUR3T, and the identification signal ID.
When the signal S7 is input, the reference signal REF is output in addition to the synchronization signal 5YNC, the burst signal BURST, and the identification signal ID.

In the embodiment of the present invention, there are two timings for outputting the signal S7 from the digital signal processing circuit 7, and the signal timing corresponds to the first image signal of the reproduction display device.

FIG. 4 shows two reference signal REF generation circuits of the reference signal generation circuit 8 excluding the circuits that generate the synchronization signal 5YNC, the burst signal BUR3T, and the identification signal ID.

This reference signal generation circuit 8 uses a sampling clock CLK.
A frequency divider circuit 811 which divides the frequency of . n reference signals a0
ROM 83.~an-1 are continuously stored, inputting the output from the address increment circuit 82 as the address signal ADR, and outputting the corresponding recorded reference signals a0~an-1. A latch circuit (register) 84 that holds the reference signal (any one of aO to a7-1) from this ROM 83. A gate circuit 85 is also connected as shown.

Reference signal a. -a2 is address increment circuit 82
In this embodiment, as shown in FIGS. 5(a) to 5(C), the reference signal a is sequentially output from the ROM 83 in response to the address signal ADR from the ROM 83.

~a2 remains the same level 5.4. Or it continues for 3 sampling clock CLKs. Therefore, the frequency division ratio 1/N of the 1 frequency divider circuit 81 is 115.1/4 or 1/N.
3, and the 9 frequency divider circuit 81 outputs the address increment signal ADINC every five, four, or three sampling clocks CLK. The address increment circuit accumulates the address increment signal ADINC and outputs the address signal ADR to the ROM 82. As a result, the reference signals a0 to a, -1 are sequentially outputted from the ROM 82 every 5, 4 or 3 sampling clocks CLK.

The reference signals a0 to a, -1 outputted from the ROM 83 are held in the latch circuit 84 and outputted to the gate circuit 85. When the signal S7 from the digital signal processing circuit 7 is at the "on" level, the gate circuit 85 outputs the reference signal (a) from the latch circuit 84 in response to each sampling clock CLK.
o to aR-1) to the signal adding circuits 9 and 15. That is, as shown in FIG. 5(a), in the case of data with 5 samplings of rubels, when the sampling clock CLK is 1 to 5, the reference signal a0 of the rubel is applied to the signal addition circuits 9 and 15, and the three color differences are applied. Instead of the signal C and the luminance signal Y, it is applied to the circuits after DAC Io, 16. Similarly, the sampling clock CLK is 6
~10. At the time of 11 to 15, the reference signals a1 and a2 of the 2.3rd level are sequentially applied to the signal addition circuits 9 and 15,
Similarly, the reference signal a. -3, the reference signal a replaces the color difference signal C and the luminance signal Y. -an-1 is output and recorded on the magnetic tape. In this way, the same reference signal REF is recorded on channels A and B. Figure 5 (b
), (c) when the number of data per rubel is 4 or 3 sampling data, the operation is the same as that for 5 sampling data described above.

The regenerated yarn PB shown in FIG. 1 reproduces signals from a magnetic tape on which one or more video signals (a color difference signal and a luminance signal) and a reference signal REF are recorded.

That is, the signal to the channel read by the two-rotation drum 25 is amplified by the amplifier circuit 31, FM demodulated by the FM demodulation circuit 32, and analog signal processing opposite to that of the analog signal processing circuit 12 is performed by the analog signal processing circuit 33. LPF3
4, and converted into a digital signal by ADC35.

It is applied to the digital signal processing circuit 42 as a channel A TCI signal. Similarly, the channel B signal is also sent to the amplifier circuit 36. FM demodulation circuit 37. Analog signal processing circuit 38
．． LPF39. Channel B TCI via ADC 40
The signal is applied to the digital signal processing circuit 42 as a signal.

The digital signal processing circuit 42 performs the reverse operation of the digital signal processing circuit 7, that is, deshuffling, time base compression,
Performs decompression processing, etc. Furthermore, DAC43 and LP
F44. DAC45 and LPF46. A recording luminance signal Y1 and a color difference signal P are applied to the recording system REC via the DAC 47 and LPF 48.

A baseband reproduced luminance signal Y corresponding to Pa.

The reproduced color difference signals PB and PR are reproduced.

A reference signal extraction circuit 41 corresponding to the reference signal generation circuit 8 extracts two normally synchronizing signals 5YNC, a burst signal BUR3T, and an identification signal ID from the TCI signals of channels A and B output from the ADC 35 and ADC 40. Also, a timing signal 343 is sent from the digital signal processing circuit 42.
When is applied, synchronization signal 5YNC, burst signal BU
R3T, in addition to the identification signal ID, there is also a reproduction reference signal RE.
F" is extracted, and the extracted reference signal REF" is output to the digital signal processing circuit 42.

In addition to the above-described digital signal processing, the digital signal processing circuit 42 refers to the extracted reference signal REF' to adjust the level of the reproduced video signal and the level between channel signals. Therefore, the digital signal processing circuit 42
A reference signal REF having a pattern shown in any of FIG. 3 and FIGS. 5(a) to (C) is recorded in advance,
Reproduction reference signal R for this recorded reference signal REF
EF'' is compared to determine the distortion state and deterioration state, and the determination result is used to adjust the subsequent video reproduction signal and signal adjustment between channels.

Both channels A and B use the same reference signal REF, and this reference signal REF is used by the digital signal processing circuit 42.
Since this is known in the art, adjustment of the reproducing system with respect to the recording system and adjustment between channels can be performed accurately.

In particular, in the present invention, FIGS. 3 and 5 (a) to (
As shown in C), since the same level uses a continuous stepwise reference signal REF over multiple sampling clocks, sample data at the same level can be obtained even if there is a difference in sampling timing (even if jitter occurs). It has the advantage of being obtained.

For example, in FIG. 5(C), when the sampling clock CLK is 2, the sampling timing is 1.
Or even if it shifts in the direction of 3, the same 1st rubel signal a
. is obtained. Therefore, even if the sampling timing shifts by one clock CLK back and forth, the adjustment based on the reference signal will not be disrupted. By configuring at least three samples per rubel in this way, the influence of jitter can be reduced.

Furthermore, as described above, ringing may occur in sample data whose level changes step by step. In this case, if it is configured with 4 samples or 3 samples per Luher as shown in Figure 5(b) and (C),
If the sampling timing is shifted due to
There is a possibility that data with ringing may be sampled. Therefore, it is desirable to configure each rubel with five or more samples as shown in FIG. 5(a). In this way, when configuring 5 or more samples per rubel, even if the sampling timing is shifted by one clock before or after and ringing occurs in the data at both ends, the sampled data level is the same, and the above adjustment does not apply. It has no effect.

In the case of Fig. 5(a), the number of samples to configure the two reference signals increases, but the high-definition baseband signal is sampled at 44.55MHz and the nine color difference signals are reduced to 1/4.
Taking compressed line sequential processing as an example, the number of effective samples for the luminance signal is 1152, and the number of effective samples for the color difference signal is 2.
It becomes 88.

The video signal portion of the TCI signal recorded is 14 per IH.
There are about 40 samples. If the video signal data is 8 bits and all levels of data are prepared, n=
It will be 256 Lehels. Therefore, if the reference signal is composed of Luher 5 sample data, the number of samples is 5 x 256 = 128.
The number of samples is 0, which is sufficiently within the range of the number of 1440 samples mentioned above, and it is possible to record the reference signal in the same period as the IH of the video signal.

Since the reference signals a0 to all-1 are set with one bit difference in each step, the achromatic level AL is also included, and the reference can be clearly adjusted.

In the above example, the reference signal REF (or reference signals a0 to an-1) is generated in the reference signal generation circuit 8, but the reference signal REF may be generated from the digital signal processing circuit 7. Similarly, instead of the above example in which the reproduction reference signal REF' is extracted by the reference signal extraction circuit 41, it may be extracted by the digital signal processing circuit 42.

The case where the present invention is applied to an HDVTR apparatus has been described above, but the above-mentioned values, the number of reference signals REFO, the number of levels, etc. are merely examples, and can be set to appropriate values according to the apparatus conditions.

〔Effect of the invention〕

As described above, according to the video signal recording device having the stepwise reference signal insertion circuit of the present invention, adjustments in the playback system are not affected by 1 jitter or sampling timing deviation, and between multiple channels. Adjustment and adjustment of distortion in the recording system are performed accurately.

[Brief explanation of the drawing]

Figure 1 shows a high-definition VTR as an embodiment of the present invention.
FIG. 3 is a diagram showing the configuration of the device. Figure 2 shows the IH in the high-definition VTR device shown in Figure 1.
FIG. 3 is a diagram showing a normal video signal format. FIG. 3 is a diagram showing reference signals in the high-definition VTR device of FIG. 1. FIG. 4 is a circuit configuration diagram of the reference signal generation circuit of FIG. 1. 5(a) to 5(c) are detailed partial waveform diagrams of the reference signal generated by the reference signal generating circuit of FIG. 4. (Explanation of symbols) 7. Digital signal processing circuit. 8...Reference signal generation circuit. 9.15...Signal addition circuit. 12.18...Analog signal processing circuit. 19...FM modulation circuit, 25...Rotating drum 32.37
...FM demodulation circuit. 33.38...Analog signal processing circuit. 41...Reference signal extraction circuit. 42...Digital signal processing circuit. 81... Frequency divider circuit. 82...Address increment circuit. 83...ROM, 84...Latch circuit. 85...Gate circuit. 85: Gate circuit Figure 4 a29・00・0・0 a1ー〇・0・0−8 a□ o−o−o−o−j CLK I 2345678910tl1213
1415 Figure 5 (a) a21;)-G-0-O al <)-◇-o-6 ao o-o-o-zuCLK 123456789101112a2
I>0-O al 1>-o-kun a□ o-o-g cLK 123456789 Figure 5 (C)

Claims (1)

[Claims] 1. In a video signal recording device that divides a video signal into video signals of multiple channels and records them on a recording medium, instead of a predetermined video signal of each channel, a plurality of consecutive signals of the same level are used. A video signal recording device characterized by comprising circuit means for inserting a reference signal that changes stepwise.