JPH04196619A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction of an output load circuit and to reduce power consumption by selecting a gate width of a pull-down transistor(TR) larger than a gate width of a pull-up TR. CONSTITUTION:A gate width of a pull-down TR 54 is set larger than a gate width of a pull-up TR 53. When an H level input signal Vi is inputted to an input terminal 50a, the TR 53 is turned off and the TR 54 is turned on and a level of an output terminal 60 is set to an L level. In this case, a sink current flows to a ground GND through the output terminal 60 and the TR 54 from a TTL integrated circuit 70. Since the gate width of the TR 54 is set larger, the resistance is low to act like suppressing the increase in the level of the output terminal 60. Thus, malfunction of an output load circuit is eliminated and power consumption is reduced.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a Schottky gate field effect transistor (
TT as an output buffer circuit in a logic integrated circuit using MESFET (hereinafter referred to as MESFET), especially as an output load circuit.
L (Trans i 5torTransistor
Even if an integrated circuit such as Logic) is connected,
This relates to an output buffer circuit that can normally receive and pass signals.

(Prior Art) In recent years, logic integrated circuits using GaAs (gallium arsenide) MESFETs have been used as logic circuits that operate at high speed.Output buffers of integrated circuits with large capacitive loads in such logic integrated circuits The circuit is a so-called super buffer circuit (Super Buffer circuit).
FET LogtC) is used.

Conventionally, the basic circuit format of this type of integrated circuit was ``Proceedings of the IE Customized Circuits Conference'' (PROCEEDINGS OF TH).
E EEE CUSTOM INT, EGRA
TED CIRCUITS CONFERENCE)J
(1985-5) P.

There was one described in 425-428. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional super buffer circuit, in which the super buffer circuit is used as an internal logic circuit of an integrated circuit.

In this figure, cascaded superbuffer circuits 10.20 are provided. Super buffer circuit 1
0 has an input terminal 11 for inputting an input signal Vi, and a normally-off transistor 12 is connected to the input terminal 11. Furthermore, transistor 12 has input node N
1 and ground GND, and its input node N1
Normally-on transistor 13 between
A constant current load consisting of is connected.

On the other hand, input node N1 is normally-off transistor 1
Connected to 4. Further, the transistor 14 is connected between the power supply potential VDD and the output node N2, and the normally-off transistor 15 is connected between the output node 2 and the ground GND. The transistor 15 is connected to the input terminal 11.

The super buffer circuit 20 is the super buffer circuit 1
It has the same configuration as 0, and has transistors 21°, 22.23.
It is equipped with 24. Furthermore, an output terminal 25 for outputting an output signal Vo is connected between the transistors 23 and 24.

Next, the operation will be explained.

When the input signal Vi of "L" level (+O, lv) is input to the input terminal 11, the transistor 12 is turned off, and the input node N1 becomes "H" level. This input node N1 is grounded through the transistor 14 and the next stage transistors 21 and 24, so its potential is 1
．． It will be about 4v.

At this time, the gate voltage of the transistor 14 is about 1°4V, and the gate voltage of the transistor 15 is O.lv. As a result, the transistor 14 is turned on, the transistor 15 is turned off, and the output node N2 becomes high.
°” level.

This "Hg+ level" is approximately 0 because the output node N2 is grounded through the gates of the transistors 21 and 24.
．． It becomes 7■.

Next, when an input signal Vi of +0.7v "HT+ level" is input to the input terminal 11, the transistor 12 is turned on, and the potential of the input node N1 is 0.1v to 0.2v.
becomes the “L” level. Therefore, transistor 14 is turned off and transistor 15 is turned on. As a result, the potential of the output node N2 drops to about 0.1V and becomes "L" level. The above input characteristics are shown in FIG.

Further, the super buffer circuit 20 performs the same operation as the super buffer circuit #110, and outputs an inverted signal of the signal at the output node N2 from the output terminal 25 as the output signal Vo.

In FIG. 2, the rise time of the signal on the output node N2 is determined by
22 is determined by the current flowing through the transistor 14 and the output node N2 from the power supply potential VDD. Further, the fall time of the signal on the output node N2 is determined by the current flowing to the ground GND via the transistor 21.23, the output node N2, and the transistor 15 in order to extract the charge from the transistor 21.23.

In logic level circuits, it is preferable to equalize the rise time and fall time of the signal, so transistor 2
1.23 It is necessary to equalize the charging and discharging currents. Therefore, the gate widths of transistors 14 and 15 are set to be equal.

By the way, such a super buffer circuit has a higher load driving ability than a direct coupled logic circuit (DCFL), so it was effective even when used as an output buffer circuit with the largest load capacity in a logic integrated circuit. .

(Problems to be Solved by the Invention) However, when the super buffer circuit 10 having the above configuration is used as an output buffer circuit, when a TTL integrated circuit is connected to the output node N2 as an output load circuit,
There was a risk that normal digital signals could not be received or transferred.

The rise time and fall time of output node N2 are Ion
In order to make the width approximately s, it was necessary to set the gate widths of transistors 12 and 13 to 20 μm and 60 μm, respectively, and similarly, to set the gate widths of transistors 14 and 15 to 90 μm.

However, when a signal at °°H level is input to the input terminal 11 and the signal level at the output node N2 is set to the "t L t" level, the signal from the TTL integrated circuit passes through the output node N2 and the transistor 15 to the ground GND. A sink current flows into it.

At this time, the gate voltage of the transistor 15 is 0.7V at the ``H°'' level, and the potential of the output node N2 would normally be about 0.degree. 1V if this sink current did not flow. However, when this sink current flows at a maximum of about 2 mA, as shown in FIG.
0.6v that is 0.4v or more of the maximum voltage of the signal “L” level
As a result, the TTL integrated circuit may malfunction.

As a solution to the above problem, it is possible to lower the "L" level of the signal by doubling the gate width of transistors 14 and 15 to 180 μm, but in that case, the current when transistor 14 is on increases. In order to
This results in a significant increase in current consumption.

The present invention provides an output buffer circuit that solves the problems of the prior art in that when an output load circuit is connected, the output load circuit causes malfunction and increases power consumption.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an input transistor connected to an input node and turned on/off based on an input signal, and a connection between the input node and a power supply potential. a pull-up transistor with a predetermined gate width that is connected between the connected load means and the power supply potential and the output node and is turned on and off based on the potential of the input node;
In an output buffer circuit comprising a pull-down transistor connected to the output node and turned on and off in a complementary manner to the pull-up transistor based on the input signal, the gate width of the pull-down transistor is The gate width is set to be larger than the predetermined gate width of the pull-up transistor.

(Function) Since the present invention configures the output buffer circuit as described above, the resistance value of the pull-down transistor becomes smaller as the gate width of the pull-down transistor is expanded. As a result, when an output load circuit such as a TTL integrated circuit is connected to the output node, the potential of the output node "°L'°
Even if a sink current flows through the output node and the pull-down transistor at the level, the pull-down transistor works to prevent the potential of the output node from rising above a predetermined value.

Furthermore, since the resistance value of the pull-up transistor does not change, the current when the pull-up transistor is on does not increase. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of an output buffer circuit showing an embodiment of the present invention.

The output buffer circuit 50 is constituted by a super buffer circuit, and has an input terminal 50a for inputting the input signal Vi, and the gate of a normally-off transistor 51, which is an input transistor, is connected to the input terminal 50a. Further, the drain of the transistor 51 is connected to the input node NIO, and the source is connected to the ground GND.

The input node NIO is commonly connected to the source and gate of a normally-on transistor 52, which is a load means, and the drain of the transistor 52 is connected to the power supply potential VDD. Here, the gate width of the transistor 51 is 60 μm.
The gate width of the transistor 52 is set to 20 μm, and the transistors 51 and 52 are made of GaAs ME.
It is composed of SFET.

On the other hand, the input node NIO is connected to the gate of a normally-off transistor 53, which is a pull-up transistor. The drain of the transistor 53 is connected to the power supply potential VDD, and the source is connected to the train of a normally-off transistor 54, which is a pull-down transistor.

Moreover, the source of the transistor 54 is connected to the ground GND, and the gate is connected to the input terminal 50a.

The source and drain of the transistor 53 are connected to the TTL integrated circuit 70 via an output terminal (output node) 60 for outputting an output signal (2).

Here, the gate width of the transistor 53 is set to 90 μm. Furthermore, the gate width of the transistor 54 is set to 180 μm, which is larger than the gate width of the transistor 53, and the transistors 53 and 54 are both made of GaAs ME.
SFET'''C'' is configured. In addition, the output terminal 60
The power supply potential VDD is set to 5 V in order to set the "H" level of the TTL to 2.4 V or higher, which is the minimum standard of the TTL "°H'° level."

The output buffer circuit configured as described above operates as follows.

When the "L" level input signal Vi is input to the input terminal 50a, the transistor 51 is turned off, and the potential of the input node N10 becomes "H" level. At this time, the transistor 53 is turned on, the transistor 54 is turned off, and as a result, the potential of the output terminal 6o is "H++".
level.

Next, an input signal Vi at the ILH'' level is applied to the input terminal 50a.
When input, the transistor 51 turns on,
The potential of input node NIO becomes If L II level. Therefore, transistor 53 is turned off and transistor 54 is turned on.

As a result, the potential of the output terminal 60 becomes "L" level.

In this way, when the "H" level (0.7v) is input to the gate of the transistor 54, the transistor 54 is turned on and the potential of the output terminal 60 is set to the "L" level. At this time, TTL integration times fi'! When a sink current of 2 [mA] flows from the output terminal 70 to the ground GND via the output terminal 60 and the transistor 15, the transistor 54 has a large gate width of 180 μm, so the resistance value decreases accordingly, and the drain It works to suppress the rise in potential on the side. Its input/output characteristics are shown in FIG.

In FIG. 5, the input voltage Vi applied to the input terminal 50a is plotted on the X-axis, and the output voltage Vo output to the output terminal 60 is plotted on the Y-axis. When the input voltage Vi is at a low "L" level, the output voltage 0 becomes "H" level, and conversely, when the input voltage Vi is at a high "H" level, the output voltage Vo becomes "L" level.
°゛ level.

This "L" level output voltage 0 is suppressed to 0.3v, which is less than 0.4v, which is the maximum voltage of the "°L" level.

This embodiment has the following advantages.

(1) Change the gate width of transistor 54 to transistor 53
Since the gate width is set larger than the gate width, the potential of the output terminal 60 does not rise even if a sink current flows as described above. Therefore, normal digital signals can be received and delivered to the TTL integrated circuit 70.

(2) Instead of expanding the gate widths of the transistors 53 and 54 so that the gate widths are equal, as in the conventional case,
Since the gate width of the transistor 54 is increased, the current does not increase when the transistor 53 is turned on. Therefore, an increase in power consumption can be prevented.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following variations.

(I) In the above embodiment, the pull-up transistor 53
Although a normally-off transistor is used as the pull-down transistor 54, the present invention is not limited to this, and a normally-on transistor may also be used.

(II> Although the sources of the transistors 51 and 54 are connected to the ground GND, they may be connected to, for example, a negative potential.

(■) Transistors 51, 52, 53, 54 are GaA
Although it is constructed using a MES of 100 kHz, it may also be constructed using silicon transistors.

(1v) Although the normally-on transistor 52 is used as the load means, for example, a resistor or the like may be used.

(Effects of the Invention) As described in detail above, according to the present invention, the gate width of the pull-down transistor is set larger than the gate width of the pull-up transistor, so that the gate width of the pull-down transistor is The resistance value of the pull-down transistor becomes smaller by the enlargement. As a result, when an output load circuit such as a TTL integrated circuit is connected to the output node, even if a sink current flows when the potential of the output node is at "L'° level, the potential of the output node will not rise above a predetermined value. Therefore, Malfunctions of the output load circuit can be prevented.

Furthermore, since only the gate width of the pull-down transistor is increased, the current when the pull-up transistor is turned on does not increase. This can prevent an increase in power consumption.

[Brief explanation of the drawing]

゛ Figure 1 is a circuit diagram of an output buffer circuit showing an embodiment of the present invention, Figure 2 is a circuit diagram of a conventional super buffer circuit, Figure 3 is an input/output characteristic diagram of Figure 2, and Figure 4 is a sink circuit diagram. FIG. 5 is an input/output characteristic diagram when current flows in. FIG. 5 is an input/output characteristic diagram in FIG. 1. 50... Output buffer circuit, 51...
Input transistor, 52...Load means, 53
...Pull-up transistor, 54...
...Pull-down transistor, 60...Output node, 70...TTL integrated circuit, NIO...
...Input node. Output Soh Circuit of Embodiment of the Invention Figure 1 Conventional Super Buffer Circuit Figure 2 Procedural Amendment (Radio) March 2-7, 1991 1 Case Description 1990 Patent Application No. 321525 2 Name of the invention output buffer circuit 3 Relationship with the case of the person making the amendment Patent applicant address 1-7-12 Toranomon, Minato-ku, Tokyo Name (02
9) Oki Electric Industry Co., Ltd. Representative Nobumitsu Kosugi 4th Representative (Postal Code 101) 2-9-3 Sotokanda, Chiyoda-ku, Tokyo February 25, 1991 7. Engraving of the detailed statement of the amendments (in the details) No change) 111゛＼ノ゛

Claims (1)

[Claims] An input transistor connected to an input node and turned on and off based on an input signal, a load means connected between the input node and a power supply potential, and a connection between the power supply potential and an output node. a pull-up transistor with a predetermined gate width that is connected between the pull-up transistor and turns on and off based on the potential of the input node; and a pull-up transistor that is connected to the output node and is complementary to the pull-up transistor based on the input signal. and a pull-down transistor that turns on and off.
An output buffer circuit comprising: a gate width of the pull-down transistor is set to be larger than the predetermined gate width of the pull-up transistor.