JPH04192791A - Telephone exchange - Google Patents

Abstract

PURPOSE:To reduce the influence of phase fluctution at the time of changing over a digital line and to reduce a buffer or a circuit by providing a phase control oscillation means synchronizing with receiving data and generating a second clock synchronizing with a first clock with higher frequency than the frame frequency of the receiving data. CONSTITUTION:In a network synchronization part 7 at the position of a telephone exchange, a 64KHz clock 30 outputted from a digital communication line interface part is inputted to a selector 32 and a communication detection signal 31 is inputted to a priority encoder 33. A clock with higher priority from among the clocks synchronized with the lines on which the communication is being executed is selected and inputted to a PLL35. The VCO of the PLL extension is designed to have a center frequency of 8.192MHz, and the obtained clock at 8.192MHz is used as a reference clock actuating a changeover switch. Since the frequency at 65Khz which is eight times the frame frequency is used as the clock to be inputted to the network synchronization part 7, the phase fluctuation amount can be half as much as the cycle of the frequency at 64KHz at the maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of Jv: Industry 1-] The present invention relates to a telephone exchange apparatus having means for generating a clock synchronized with a network.

[Prior Art] Conventionally, in telephone switching equipment that accommodates digital communication lines, clocks are extracted from signals received from the network in order to prevent data deviation due to differences in operating frequencies between the network and the switching equipment. However, it is well known that a dependent synchronization method is used in which the exchange switch is operated in synchronization with the extracted clock.

A phase controlled oscillator (PLL) or the like is used to generate a clock from a signal received from the network. In this way, the clocks extracted from each line are input to the network synchronization section, and a clock synchronized with the input clock is generated. One of the clocks extracted from a plurality of lines is selected in the network synchronization section.

However, conventionally, a clock having a frequency equal to the communication frame frequency has been used as the clock manually input to the network synchronization unit.

[Problem to be Solved by the Invention] However, in the above-mentioned example, the frequency of the clock input to the network synchronization unit coincided with the frame frequency, which caused the following problems.

Some digital lines do not receive data unless they believe that the communication will be terminated. When accommodating such lines, the clock input to the network synchronization unit should be the one extracted from the line during communication. Is it necessary to use it? For this purpose, it is necessary to switch the clock input to the network synchronization unit depending on the communication state of the line. When switching the clock,
The phase of the clock manually input to the phase controlled oscillator in the network synchronizer changes. Therefore, the phase of the clock that operates the exchange switch also changes. In other words, the phase of the reception timing clock with respect to the reception data changes.

In order to prevent data errors from occurring due to this phase change, F
Is it necessary to provide a buffer such as IFO in the data transmission section?

Here 1: As in the past, when the frequency of the clock input to the network synchronization section matches the frame frequency, it is very susceptible to the effects of phase changes, so the capacity of the buffer provided in the data transmission section must be increased. There was a drawback to that.

Another disadvantage is that in order to reduce the buffer capacity, it is necessary to provide a circuit for delaying the clock input to the network synchronization section, as shown in Figure M6.

"Means for Solving the Problem" According to the present invention, in a telephone switching device having a function of connecting to a common line, a first clock synchronized with received data and having a frequency higher than the frame frequency of the received data. By providing a first phase-controlled oscillation means that generates the first clock and a second phase-controlled oscillation means that generates the first clock that is synchronized with the first clock, it is possible to eliminate the effects of phase fluctuations when switching over the digital line. There is a method C that aims to reduce the size and reduce the number of buffers or circuits.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to one drawing.

FIG. 1 is a block diagram of the telephone exchange device of this embodiment,
In the same figure, ■ indicates a digital communication line (for example, 15DN
), 2 is the main device, 3 is the digital line interface, 4
is a highway, 5 is a 64KHz clock, 6 is a communication hub between CPUs, 7 is ;if2] synchronization section, 9 is an exchange processing section, 1
0 is 1: a control device (CPU), 11 is a memory, 12 is an address bus/data bus, 13 is a highway, 14 is an extension interface, and 15 is a telephone set.

Further, FIG. 2 is a block diagram of the digital line interface section of the telephone exchange equipment of this embodiment, and in the same figure, 1
6 is 1 to lance, 17 is layer layer 2 control unit, 18
is a digital PLL, 19 is a DMAC520 is a communication detection signal, 21 is a 64KHz clock, 22 is an 8KHz clock, 23 is a serial/parallel conversion circuit, and 24 is a FIF.
O(1'i+°St I n F 1r9t 0ut
), 25 is 2MHz clock, 26 is A1~Res.
Data bus, 27 is RAM, 28 is ROM, 29 is CP
It is U.

FIG. 3 is a block diagram of the network synchronization unit, in which C13o is a 64KHz'70 clock, 31 is a communication detection background, 32 is a selector, 33 is a priority encoder,
34 is selector control A, No. 4, 35 is analog PLL,
36 is a frequency divider.

Further, FIG. 4 is a block diagram of the network synchronization unit of the second embodiment, and the numbers are the same as in FIG. 3.

Further, FIG. 5 is a diagram showing the state of phase change when cutting the clock input to the network synchronization section.

FIG. 6 is a block diagram of a network synchronization section in a conventional telephone exchange. In the figure, 37 is a phase comparator;
Reference numeral 8 denotes a delay generating section, and other parts are the same as in FIG.

First, before explaining this embodiment, a conventional telephone exchange device will be explained.

Conventionally, the network synchronization unit was manually supplied with an 8KHz clock equal to the frame frequency. When changing the clock input to the network synchronization unit, a phase change occurs as shown in FIG. 5, depending on the relationship between the phase of the clock before switching and the phase of the clock after switching. According to this, at most
A phase change of L/2 cycles of 8 kHz will occur. The phase controlled oscillator in the network synchronization unit increases or decreases the frequency of the output 8.192 MHz clock in accordance with the phase change. For example, when the phase changes as shown in FIG. 5(a), the frequency of the 8.192 Mllz clock temporarily becomes slightly higher, which means that the operating clock of the exchange switch also becomes faster. As a result, the timing of reading data to the highway (exchange switch) becomes faster than the timing of turf reception from the line, leading to the possibility of overflow. Further, when the phase changes as shown in 5th+>] (b), the frequency of the 8.192 MHz clock becomes temporarily slower, which means that the operating clock of the exchange switch also becomes slower. As a result, the timing of data transmission to one highway (exchange switch) is delayed compared to the turf reception timing of the line, and there is a risk of underflow. So 1. However, as mentioned above, the turf from the prearranged line is stored in a FIFO buffer to prevent data errors from occurring even if the exchange switch operation clock changes.

Here, conventionally, as mentioned above, the maximum frequency was 17/2 of 8KHz.
Since there is a possibility that a period shift may occur, in order to prevent the occurrence of data errors, a large-capacity buffer, such as a capacity for 28 stages of 8H1-*, is required to be frozen.

In addition, the FIFO in the digital communication line interface section
To reduce the buffer capacity.

Is it necessary to reduce the number of phase change stars when switching clocks?

Therefore, as shown in Figure 6 [; 21], the phase difference between the clock extracted from each line and the clock being used by the phase control oscillator in the network synchronization section is measured, and the delay of the countermeasure corresponding to the phase difference is calculated. The phase change of all the clocks is made equal to the phase change of the clock, so that the phase change shown in FIG. 5 does not occur even when the clock is turned off. In the case of this method, it is not possible to reduce the capacity of the FIFO buffer, and the disadvantage is that the structure of the network synchronization section becomes complicated.

Next, the operation of the telephone exchange apparatus of this embodiment will be explained, focusing on the operation when a digital communication line is accommodated.

As shown in FIG. 1, the telephone exchange equipment includes a digital communication line interface section, a network synchronization section, and a switching
S), a central control unit, memory, an extension interface unit, an extension telephone, etc. The central control unit, memory, and exchange switches are connected via a data bus and address bus. Further, the digital communication line interface section and the extension line interface section are connected by a highway (communication path) via an exchange switch.

Furthermore, the digital communication line interface section and the extension line interface section each have a central control unit (CPU) and memory, and each communicates with the central IJI control section via the CPU communication hub. Ru.

The digital communication line interface section is configured as shown in FIG. In this example, 6 is used as a digital communication line.
4Kl) I) S communication channel (B channel) 2 channels, l 6 Kbps control channel (D channel) ■
The following explanation will be made assuming that an ISDN line composed of channels is used. The layer layer 2 control section 17 is connected to the network 1 via the 1herance 16, and the layer layer 2 control section that performs frame assembly/disassembly, competition control 1 layer 2 (LAPD) control, etc. has a DMAC 19 inside. DMA transfer of D channel data is performed with the memory (RAM) 27. In addition, the layer layer 2 control section has an internal phase control oscillator (digital PLL).
) 18, and generates 64KHz and 8KHz clocks synchronized with data received from the line. The 64 kHz clock generated here is manually input to a network synchronization unit, which will be described later.

A communication detection signal 20 is also sent to the network synchronization unit. When the layer layer 2 control unit detects that synchronization has been established with the digital communication line, it sets this communication detection value to active and notifies the network synchronization unit whether the clock of the line can be used.

B channel data is sent to the serial/parallel converter circuit 23
, F I F O (First, I n F 1rs
tOut) buffer 24. It is connected to Highway 4 via a parallel-to-serial conversion circuit. For example, Ukei 3
In the case of the data, the B channel data decomposed by the layer 2 control section is converted into 8 hit data by the serial/parallel conversion circuit. Converted 8 hits 1
The hetator is synchronized with the 8KHz clock mentioned earlier and the FI
The FIF is written in the FO buffer and synchronized with the 2MHz clock 25, which is synchronized with the operating clock of the exchange switch.
Read from the O buffer. The read data is converted into serial data by a parallel-to-serial conversion circuit and sent to an assigned time slot on highway 1-. For data to be sent 4g, reverse -T-
Depending on the order, the information is transmitted from the highway to the Rayani Sea Ear 2 control unit.

The configuration of the network synchronization unit is as shown in No. 31A.

The 1v4 synchronization section has a priority encoder, selector,
It is composed of a PLL and a frequency divider (counter). A clock 30 output from the digital communication line interface section is input to the selector 32, and a communication detection signal 31 is input to the Brioliday encoder 33. The digital communication line InterAce section is given a priority order depending on where it is installed in the device, and the above-mentioned Brioliday encoder and selector determine the priority order of the clocks synchronized with the communication line. A crystal clock is selected and inputted to the PLL 35. V inside PLL
The center frequency of CO is set at 8.192 MHz. The output clock of 8,192 MHz is divided by the counter 36 and the clock obtained is
I hacked it and made a phase comparison with the manual clock. The 8,192 MHz clock thus obtained is used as a reference clock for operating the exchange switch.

Is it the line or communication that inputs the clock to the PLL? P:'r
If the priority encoder is activated, the clock synchronized with the next highest priority line is selected.

During this switching, the phase of the clock input to the PLL changes as shown in FIG. 5, and this effect is absorbed by the FIF buffer in the digital communication 48 line interface.

The exchange switch 9 is connected to the highway 13, and receives the B channel data and sends it to the time slot assigned to the extension, as described above, or conversely receives data from the extension and assigns it to the digital communication line. It performs an exchange operation such as transmitting data to a designated time slot. The control of the exchange switch is carried out by a control device 10.

As described above, by synchronizing the digital communication line and the switching operation clock with respect to B channel data, it is possible to perform communication without data errors.

- On the other hand, data on the D channel is transferred to the RAM 27 by the DMACl 9 built in the layer 2 control unit 17. The CPU 33 decodes the transferred data and performs communication control.

Also in the network synchronization section of this embodiment, the clock input to the PLL is selected by a selector. Similar to Juto, it is necessary to change the clock depending on the communication situation.

However, in this embodiment ζJ-, a clock of 64 KHz 7g, which is 8 times the frame frequency, is used as the clock input manually to the network synchronization section. According to this, even if the phase change is large, the phase change 1? is 64.
KH: 1,72 cycles. Therefore, in order to prevent the buffer from overflowing or underflowing even if tX' is multiplied by 1-· the same number of times as in the example and the maximum phase change occurs in the same direction continuously, it will take more time than the conventional example to prevent the buffer from overflowing or underflowing. The buffer capacity of - is 1 - minute. In other words, in order to obtain the same effect as the conventional example, it takes 8 hits*16 stage buffers for 1 minute.

How to use the FIFO buffer: While digital communication is not being performed, the FIFO buffer is set to a zero position, and after digital communication starts, it remains at half the buffer capacity until C data is accumulated. Make sure to only write data. In other words, control is performed so that reading is not performed until the number of writes reaches 8 times. As a result, no shifter flow or overflow occurs regardless of the direction of the phase change.

In the case of this embodiment, no overflow or underflow occurs unless the maximum phase change occurs in the direction of rotation 64 times in a row. Knead is a sufficient buffer for practical use.

As described above, by implementing the present invention, data 1i' can be generated using a buffer with a small capacity and a simple circuit configuration.
- It is possible to configure a network synchronization system without any network synchronization system.

The second embodiment will now be described.

FIG. 4 shows the block +51 of the network synchronization unit in the telephone exchange device of the second embodiment. In the same figure, 64KHz
The clock selection is not based on the priority encoder.
=1-This is done by line selection borrowing from the control unit.

The communication status information between the digital communication line interface section and the 1-piece control section is notified to the control section, and based on that information, a selection signal is generated to either the L control section or the 3-piece 1 control section.

By adopting this force D;, it is possible to reduce the number of parts and to perform flexible control. In other words, it is possible to reduce the frequency of cutting and deleting the clock, and it is possible to further reduce the capacity of the FIFO buffer provided in the digital communication line interface.

Specifically, without setting priorities for communication lines, ・Clock switching is not performed unless one communication is completed. Roughly speaking, after disconnection, select the clock that is synchronized with the line that has been communicating for the longest time. By incorporating the algorithm described above into firmware, it is possible to reduce the number of times the C1 hook is cut and to perform flexible control.

[Effects of the Invention] As explained above, in a telephone switching device having the function of connecting to a digital communication line, the first clock is synchronized with received data and has a frequency higher than the frame frequency of the received data. By adding 8 stages to the first phase controlled oscillation means which generates the first phase controlled oscillation means and the second clock which is rotated to the first clock, This has the effect of significantly reducing the number of buffers installed in the digital communication interface section.

[Brief explanation of the drawing]

FIG. 281 is a block diagram of the telephone exchange device of this embodiment, FIG. 2 is a block diagram of the digital line interface section of the telephone exchange device of this embodiment, and FIG. 3 is a block diagram of the network synchronization section of the telephone exchange device of this embodiment. Fig. 4 is a block diagram of the network synchronization unit of the second embodiment; Fig. 5 is a diagram showing the phase change when the clock input to the network synchronization unit is switched; and Fig. 6 is a block diagram of the network synchronization unit of the second embodiment. FIG. 2 is a block diagram of a network synchronization unit in a conventional telephone switching device. 3 is a digital communication line interface, 7 is a network synchronization unit,
9 is an exchange processing section, 10 is a main control section, 24 is a FIFO buffer, 33 is a priority encoder, and 35 is an analog PL.

Claims (5)

[Claims] (1) In a telephone exchange having a function of connecting to a digital communication line, a first phase-controlled oscillation means that generates a first clock that is synchronized with received data and has a frequency higher than the frame frequency of the received data; , a telephone exchange device comprising second phase-controlled oscillation means for generating a second clock synchronized with the first clock. (2) In claim 1, means for connecting a plurality of digital communication lines, a selector for inputting a plurality of first clocks, means for generating data indicating a line in communication, and control of the data. A telephone exchange apparatus comprising: means for switching the selector; and means for inputting the selector to the second phase-controlled oscillation means. (3) Means for converting serial data received from a digital communication line into parallel data according to claim 1, means for writing to and reading from a FIFO buffer in synchronization with a frame clock, and the second phase-controlled oscillation. The FIFO is synchronized with a clock obtained by dividing the output of the means.
1. A telephone exchange device, characterized in that it has means for reading and writing to. (4) The telephone exchange apparatus according to claim 3, further comprising means for prohibiting access to the FIFO buffer while digital communication is not being performed. (5) In claim 3, after the start of digital communication,
1. A telephone exchange apparatus comprising: means for counting the number of times of writing to a FIFO buffer; and means for prohibiting reading from the FIFO buffer until the counted number reaches one-half of the buffer capacity.