JPH04192550A - Ic package - Google Patents

Ic package

Info

Publication number
JPH04192550A
JPH04192550A JP2326274A JP32627490A JPH04192550A JP H04192550 A JPH04192550 A JP H04192550A JP 2326274 A JP2326274 A JP 2326274A JP 32627490 A JP32627490 A JP 32627490A JP H04192550 A JPH04192550 A JP H04192550A
Authority
JP
Japan
Prior art keywords
dielectric substrate
package
metal base
thickness
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2326274A
Other languages
Japanese (ja)
Inventor
Tomoji Goto
後藤　智司
Akira Otsuka
昭 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2326274A priority Critical patent/JPH04192550A/en
Publication of JPH04192550A publication Critical patent/JPH04192550A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To enhance a heat-dissipating property and to perform a surface mounting operation by providing the following: a metal base; and a member, for intermediate use, which is formed so as to be sandwiched between the other face of a dielectric substrate and an electrode for external extraction use and whose thickness is the same as the thickness of the metal base. CONSTITUTION:At a package 40 for IC use, a metal base 30 used to dissipate heat generated from a semiconductor element is formed, on the other face 20c of a dielectric substrate 20, so as to close a through opening 20a. A member 31, for intermediate use, whose thickness is the same as that of the metal base 30 is formed between the other face 20c of the dielectric substrate 20 and electrodes 1 for external extraction use. The member 31 for intermediate use is formed collectively with the dielectric substrate 207; the thickness of the member 31 for intermediate use is made to be the same as the thickness of the metal base 30. Thereby, it is possible to obtain a package whose surface mounting operation can be performed and whose heat-dissipating property is good.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、一般に、ＩＣパッケージに関するものであ
り、より特定的には、良好な放熱性を有し、かつ表面実
装が可能になるように改良されたＩＣパッケージに関す
るものである。[Detailed Description of the Invention] [Industrial Application Field] This invention generally relates to IC packages, and more specifically, IC packages that have good heat dissipation properties and can be surface mounted. This invention relates to an improved IC package.

［従来の技術］ 近年、ＧａＡｓおよびＳｌを用いたトランジスタや分周
器、増幅器等のＩＣか、実用化されている。このような
ＩＣを搭載するＩＣＣ用パラケーンして、特開平１−１
２５９５９号公報は、アルミナ単板を用いた簡単な構造
のパッケージを提案している。[Prior Art] In recent years, ICs such as transistors, frequency dividers, and amplifiers using GaAs and Sl have been put into practical use. As a paracane for ICC equipped with such an IC, JP-A-1-1
Publication No. 25959 proposes a package with a simple structure using an alumina veneer.

第３Ａ図は、特開平１−１２５９５９号公報に開示され
ている高周波パッケージの、裏面図であり、第３Ｂ図は
表面図であり、第４図は第３Ａ図におけるｒＶ−ｒＶ線
に沿う断面図である。FIG. 3A is a back view, FIG. 3B is a front view, and FIG. 4 is a cross section taken along the rV-rV line in FIG. 3A, of the high frequency package disclosed in JP-A-1-125959. It is a diagram.

これらの図を参照して、誘電体基板２０の裏面には、外
部取り出し用電極２を接続するためのＲＦリード取付は
メタライズ３か設けられている。Referring to these figures, on the back surface of the dielectric substrate 20, metallization 3 is provided to attach an RF lead for connecting the electrode 2 for external extraction.

ＲＦリード取付はメタライズ３を間隔をおいて取囲むよ
うに、裏面のグランドメタライズ４ａが設けられている
。裏面のグランドメタライズ４ａには、グランドリード
１か接続されている。誘電体基板２０の表面には、ホン
ディングバッド６が設けられており、ポンディングパッ
ド６を取囲むように、表面全面に、表面のグランドメタ
ライズ４ｂが形成されている。For RF lead attachment, ground metallization 4a on the back surface is provided so as to surround metallization 3 at intervals. A ground lead 1 is connected to the ground metallization 4a on the back surface. A bonding pad 6 is provided on the surface of the dielectric substrate 20, and a surface ground metallization 4b is formed over the entire surface so as to surround the bonding pad 6.

このように構成される高周波パッケージは、第５図に示
すように使用される。The high frequency package constructed in this way is used as shown in FIG.

すなわち、第５図を参照して、誘電体基板２０の表面側
にＩＣｌ３を搭載する。そして、外部取り圧し用電極２
をスルーホール１９（第３Ｂ図をも参照）およびワイヤ
ー２１を介してＩＣｌ３に接続する。その後、金属キャ
ップ２２を表面側に接着し、ＩＣｌ３を保護する。上述
のように構成されるパッケージは、現在量も安価なパッ
ケージであり、かつ表面実装も可能な物である。That is, referring to FIG. 5, ICl3 is mounted on the front side of dielectric substrate 20. And external pressure electrode 2
is connected to ICl3 via through hole 19 (see also FIG. 3B) and wire 21. Thereafter, a metal cap 22 is adhered to the front side to protect the ICl3. The package configured as described above is currently available at low cost and can be surface mounted.

しかしなから、このＩＣ用パッケージは、放熱性か必要
なデイバイスを搭載することかできないという問題点か
あった。However, this IC package had problems with heat dissipation and the inability to mount necessary devices.

ところで、ＩＣの高出力化、高周波化に伴い、ＩＣの発
熱量は増大しており、放熱性を考慮したＩＣパッケージ
の需要がますます高まっている。Incidentally, with the increase in the output power and frequency of ICs, the amount of heat generated by ICs is increasing, and the demand for IC packages that take heat dissipation into consideration is increasing.

そこで、第６図に示すような誘電体基板２０のＩＣが搭
載される部分に、上下に貫通する貫通口２０ａを形成し
、裏面側からその貫通口２０ａを塞ぐように、Ｃｕ−Ｗ
等の放熱性の良好な金属ベースを張付ける構造の、ＩＣ
用パッケージが提案されている。Therefore, a through hole 20a penetrating vertically is formed in the part of the dielectric substrate 20 on which the IC is mounted as shown in FIG. 6, and the Cu-W
ICs with a structure attached to a metal base with good heat dissipation such as
A package has been proposed for

［発明が解決しようとする課題］ しかしながら、第６図に示すようなＩＣ用パッケージで
は、金属ベース３０の厚みに起因する段差が生じる。そ
のため、金属ベース３０の凸部か邪魔となり、表面実装
ができない。そのため、実装される基板に、上記凸部を
受入れるための穴を開けるか、あるいはグランドリード
１を折り曲げなければならないという問題点があった。[Problems to be Solved by the Invention] However, in the IC package shown in FIG. 6, a step occurs due to the thickness of the metal base 30. Therefore, the convex portion of the metal base 30 gets in the way, making surface mounting impossible. Therefore, there was a problem in that it was necessary to make a hole in the board to be mounted to receive the convex portion, or to bend the ground lead 1.

この発明は、上記のような問題点を解決するために成さ
れたもので、良好な放熱性を有し、かつ表面実装が可能
になるように改良されたＩＣ用パッケージを提供するこ
とを目的とする。This invention was made in order to solve the above-mentioned problems, and the purpose is to provide an improved IC package that has good heat dissipation properties and can be surface mounted. shall be.

［課題を解決するための手段］ この発明に係るＩＣ用パッケージは、半導体素子が搭載
される側の一方の面と、外部取り出し用電極が取付けら
れる側の他方の面と、を有する誘電体基板と、上記誘電
体基板の他方の面側に設けられた外部取り８し用電極と
、を備えている。上記誘電体基板には、上記半導体素子
が搭載される部分に、上記一方の面から上記他方の面に
向けて貫通する貫通口が設けられている。当該パッケー
ジは、上記誘電体基板の他方の面に上記貫通口を塞ぐよ
うに設けられ、上記半導体素子から発する熱を放散させ
るための金属ベースを備えている。[Means for Solving the Problems] An IC package according to the present invention includes a dielectric substrate having one surface on which a semiconductor element is mounted and the other surface on which an external extraction electrode is attached. and an electrode for external connection 8 provided on the other side of the dielectric substrate. The dielectric substrate is provided with a through hole penetrating from the one surface toward the other surface in a portion where the semiconductor element is mounted. The package is provided on the other surface of the dielectric substrate so as to close the through hole, and includes a metal base for dissipating heat generated from the semiconductor element.

上記誘電体基板の上記他方の面と上記外部取り出し用電
極との間には、その厚みが上記金属ベースの厚みと同じ
である介在用部材が、挟まれて設けられている。An intervening member having the same thickness as the metal base is sandwiched between the other surface of the dielectric substrate and the external extraction electrode.

この発明の好ましい実施対応によれば、上記誘電体基板
と上記介在用部材は一体的に形成される。According to a preferred embodiment of the present invention, the dielectric substrate and the intervening member are integrally formed.

［作用］ この発明に係るＩＣ用パッケージによれば、誘電体基板
の他方の面と外部取り出し用電極との間に、その厚みが
金属ベースの厚みと同じである介在用部材が挟まれて設
けられているので、表面実装の邪魔になる、凸部はなく
なる。[Function] According to the IC package according to the present invention, an intervening member having the same thickness as the metal base is sandwiched between the other surface of the dielectric substrate and the external extraction electrode. There are no protrusions that would interfere with surface mounting.

［実施例］ 以下、この発明の一実施例を図について説明する。[Example] An embodiment of the present invention will be described below with reference to the drawings.

第１図は、本発明の一実施例に係るＩＣ用パッケージの
平面図であり、第２図は側面図である。FIG. 1 is a plan view of an IC package according to an embodiment of the present invention, and FIG. 2 is a side view.

これらの図を参照して、実施例に係るＩＣ用パッケージ
４０は、半導体素子が搭載される側の一方の面２０ｂと
、外部取り出し用電極１が取付けられる側の他方の面２
０ｃと、を有する誘電体基板２０を備える。誘電体基板
２０には、半導体素子が搭載される部分に、一方の面２
０ｂから他方の面２０ｃに向けて貫通する貫通口２０ａ
が設けられている。ＩＣ用パッケージ４０は、誘電体基
板２０の他方の面２０ｃに、貫通口２０ａを塞ぐように
、半導体素子から発する熱を放散させるための金属ベー
ス３０が設けられている。誘電体基板２０の他方の面２
０ｃと外部取り出し用電極１との間には、その厚みが金
属ベース３０と同じ介在用部材３１が設けられている。Referring to these figures, the IC package 40 according to the embodiment has one surface 20b on which a semiconductor element is mounted, and the other surface 20b on which an external extraction electrode 1 is attached.
A dielectric substrate 20 having 0c and 0c is provided. The dielectric substrate 20 has one surface 2 on the part where the semiconductor element is mounted.
A through hole 20a penetrating from 0b to the other surface 20c
is provided. In the IC package 40, a metal base 30 is provided on the other surface 20c of the dielectric substrate 20 so as to close the through hole 20a and dissipate heat generated from the semiconductor element. The other surface 2 of the dielectric substrate 20
An intervening member 31 having the same thickness as the metal base 30 is provided between 0c and the external extraction electrode 1.

介在用部材３１は誘電体基板２０と一体的に形成される
。The intervening member 31 is formed integrally with the dielectric substrate 20.

実施例に係るＩＣ用パッケージによれば、介在用部材３
１の厚みを金属ベース３０の厚みと同じにしているので
、表面実装の邪魔になる凸部はなくなる。その結果、こ
のＩＣ用パッケージは、表面実装が可能であり、かつ、
良好な熱放射性を有するパッケージとなる。According to the IC package according to the embodiment, the intervening member 3
Since the thickness of the metal base 30 is the same as that of the metal base 30, there are no protrusions that would interfere with surface mounting. As a result, this IC package can be surface mounted, and
This results in a package with good heat radiation.

次に、具体例を挙げながら、実施例に係るＩＣ用パッケ
ージをさらに詳細に説明する。Next, the IC package according to the embodiment will be described in more detail by giving a specific example.

パッケージの外径サイズは１５ｍｍ四角である。The outer diameter size of the package is 15 mm square.

誘電体基板２０は、厚さ０．５ｍｍのアルミナである。The dielectric substrate 20 is made of alumina with a thickness of 0.5 mm.

誘電体基板２０の表面２０ｂには、信号伝送用等のメタ
ライズ配線パターン４１が形成される。金属ベース３０
にはＣｕ−Ｗ合金を用いた。On the surface 20b of the dielectric substrate 20, a metallized wiring pattern 41 for signal transmission, etc. is formed. metal base 30
A Cu-W alloy was used.

金属ベース３０の厚みは０．５ｍｍである。介在用部材
３１は厚さ０．５ｍｍのアルミナであり、誘電体基板２
０と、一体的に焼成形成される。誘電体基板２０の裏面
には金属ベース３０を取付けるための金属ベース取付は
用パターンが形成される。通常、金属ベース取付は用パ
ターンは、グランドパターンと接続される場合が多い。The thickness of the metal base 30 is 0.5 mm. The intervening member 31 is made of alumina with a thickness of 0.5 mm, and the dielectric substrate 2
0 and is integrally formed by firing. A metal base attachment pattern for attaching the metal base 30 is formed on the back surface of the dielectric substrate 20. Usually, the metal base mounting pattern is often connected to the ground pattern.

介在用部材３１の裏面には、外部取り出し用電極１およ
び信号用リード４２を取付けるための外部リード取付は
パターンが形成されている。パッケージの作成は、通常
のセラミックパッケージの組立て工程により行なった。On the back surface of the intervening member 31, an external lead attachment pattern for attaching the external extraction electrode 1 and the signal lead 42 is formed. The package was created using a normal ceramic package assembly process.

得られたＩＣ用パッケージは、表面実装可能で、放熱性
も良好なパッケージであった。The obtained IC package was a package that could be surface mounted and had good heat dissipation properties.

なお、上記実施例では、介在用部材３１の厚みを金属ベ
ース３０の厚みと同じにした場合を例示したが、この発
明はこれに限られるものでなく、介在用部材３１の厚み
を金属ベース３０の厚みよりも厚くしてもよい。In the above embodiment, the thickness of the intervening member 31 is the same as the thickness of the metal base 30, but the present invention is not limited to this. It may be thicker than the thickness of .

［発明の効果コ 以上説明したとおり、この発明に係るＩＣ用パッケージ
によれば、誘電体基板の他方の面と外部取り出し用電極
との間に、その厚みが金属ベースの厚みと同じである介
在用部材を設けたので、表面実装の邪魔になる、凸部は
なくなる。その結果、当該ＩＣ用パッケージは、表面実
装可能で、かつ良好な放熱性を有するパッケージとなる
。[Effects of the Invention] As explained above, according to the IC package according to the present invention, there is an intervening material whose thickness is the same as that of the metal base between the other surface of the dielectric substrate and the external lead-out electrode. Since the mounting member is provided, there are no protrusions that would interfere with surface mounting. As a result, the IC package becomes a package that can be surface mounted and has good heat dissipation properties.

【図面の簡単な説明】 第１図は、この発明の一実施例に係るＩＣ用パッケージ
の平面図であり、第２図は、その側面図である。 第３Ａ図は、従来の高周波用パッケージの裏面図であり
、第３Ｂ図は平面図である。 第４図は、第３Ａ図におけるＩＶ−ＩＶ線に沿う断面図
である。 第５図は、従来の高周波用パッケージにＩＣチップを搭
載し、金属キャップで封止している半導体装置の断面図
である。 第６図は、放熱用金属ベースを備えた、従来のＩＣ用パ
ッケージの側面図である。 図において、１は外部取り出し用電極、２０は誘電体基
板、２０ａは貫通口、３ｏは金属ベース、３１は介在用
部材である。 なお、各図中、同一符号は同一または相当部分を示す。 特許出願人　住友電気工業株式会社BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of an IC package according to an embodiment of the present invention, and FIG. 2 is a side view thereof. FIG. 3A is a back view of a conventional high frequency package, and FIG. 3B is a plan view. FIG. 4 is a sectional view taken along line IV-IV in FIG. 3A. FIG. 5 is a cross-sectional view of a semiconductor device in which an IC chip is mounted in a conventional high-frequency package and sealed with a metal cap. FIG. 6 is a side view of a conventional IC package including a metal base for heat dissipation. In the figure, 1 is an electrode for external extraction, 20 is a dielectric substrate, 20a is a through hole, 3o is a metal base, and 31 is an intervening member. In each figure, the same reference numerals indicate the same or corresponding parts. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

【特許請求の範囲】 半導体素子が搭載される側の一方の面と、外部取り出し
用電極が取付けられる側の他方の面と、を有する誘電体
基板と、 前記誘電体基板の他方の面側に設けられた外部取り出し
用電極と、を備え、 前記誘電体基板には、前記半導体素子が搭載される部分
に、前記一方の面から前記他方の面に向けて貫通する貫
通口が設けられており、さらに当該パッケージは、前記
誘電体基板の他方の面に前記貫通口を塞ぐように設けら
れ、前記半導体素子から発する熱を放散させるための金
属ベースと、 前記誘電体基板の前記他方の面と前記外部取り出し用電
極との間に挟まれて設けられ、その厚みが前記金属ベー
スの厚みと同じである介在用部材と、 を備えるＩＣパッケージ。[Scope of Claims] A dielectric substrate having one surface on which a semiconductor element is mounted and the other surface on which an external lead-out electrode is attached; and the other surface of the dielectric substrate. an electrode for taking out externally, and the dielectric substrate is provided with a through hole penetrating from the one surface toward the other surface in a portion where the semiconductor element is mounted. , the package further includes: a metal base provided on the other surface of the dielectric substrate so as to close the through hole and for dissipating heat generated from the semiconductor element; and the other surface of the dielectric substrate. An IC package comprising: an intervening member that is provided between the external extraction electrode and has the same thickness as the metal base.
JP2326274A 1990-11-27 1990-11-27 Ic package Pending JPH04192550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2326274A JPH04192550A (en) 1990-11-27 1990-11-27 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2326274A JPH04192550A (en) 1990-11-27 1990-11-27 Ic package

Publications (1)

Publication Number Publication Date
JPH04192550A true JPH04192550A (en) 1992-07-10

Family

ID=18185937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2326274A Pending JPH04192550A (en) 1990-11-27 1990-11-27 Ic package

Country Status (1)

Country Link
JP (1) JPH04192550A (en)

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