JPH04192179A - Personal computer - Google Patents

Abstract

PURPOSE:To assure the operation of expanded equipment without degrading the operating performance over the entire part of a system by outputting a refresh signal onto a system bus only when an extension unit is connected. CONSTITUTION:The refresh signal is outputted to the system bus 10A and the operation control using this refresh signal is executed in the extension memory board, communication board, etc., of the extension unit 41 when the extension unit 41 is connected to an extension bus connector (EBC) 20. On the other hand, the refresh signal is outputted to an internal bus 10B and is not outputted to the system bus 10A when the unit 41 is not connected to the EBC 20. The refresh operation of a RAM 13 and a package increasing RAM 41 are controlled by the refresh signal on the internal bus 10B.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention has the following features: 1. The present invention relates to a personal computer having an expansion unit interface mechanism for connecting an expansion unit to an expansion bus connector and connecting expansion devices mounted on the expansion unit to a personal computer main body via a bus to expand system functions.

(Prior Art) In recent years, various laptop-type personal computers have been developed that are easy to carry and can be operated on batteries. In this type of personal computer,
In order to expand functionality, in addition to the various standard equipment built into the personal computer itself, the personal computer is configured so that expansion equipment can be added as needed.

As this expansion device, an expansion memory board, a communication board, and an interface board for performing various interfaces between the personal computer main body and external devices are connected.

Usually, such expansion equipment is connected to a system bus of a personal computer via an expansion bus connector, and control of the expansion equipment is performed using upstream signals on the system bus.

This refresh signal on the system bus is originally used to refresh the built-in RAM etc. connected to the system bus, but it can also be used to control expansion devices as follows. There is.

For example, regarding the expansion memory board on the expansion equipment side,
The refresh signal on the system bus is used to perform refresh control, and the communication board on the extended equipment side uses the refresh signal on the system bus to execute timeout processing and the like. The reason why the expansion device side uses the refresh signal on the system bus in this way is to synchronize its operations with the main body side.

Therefore, the CPU of the personal computer is
In order to guarantee the operation of expansion equipment, a refresh signal was output on the system bus.

However, outputting a refresh signal on the system bus increases the load on the CPU, and monopolizes the system bus with the refresh signal, which limits the use of the bus by built-in devices connected to the system bus. cause problems. In particular, in relatively high-performance personal computers in which many devices are connected to the system bus, the operation of those devices is often restricted by monopolizing the system bus by refresh signals, which reduces the overall system performance. A problem arises in that the value is lowered.

(Problems to be Solved by the Invention) As mentioned above, in the past, refresh signals were output on the system bus to guarantee the operation of expansion equipment, and for this reason, the monopoly of the system bus by the refresh signal caused the system There was a problem that the overall operating performance was degraded.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a personal computer computer equipped with a mechanism that can guarantee the operation of expansion equipment without causing a decrease in the operating performance of the entire system.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a personal computer comprising an expansion bus connector connected to a system bus and a memory that requires refreshing connected to an internal bus. means for determining whether an expansion unit is connected to the expansion bus connector; and means for outputting a refresh signal on the system bus when an expansion unit is connected to the expansion bus connector; and a means for outputting a refresh signal on the internal bus when no expansion unit is connected to the bus connector.This allows the system to operate only when an expansion unit is connected to the expansion bus connector. A refresh signal can be output on the bus, making it possible to guarantee the operation of extended equipment without degrading the operating performance of the entire system.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. - FIG. 1 is a block diagram showing the configuration of a personal computer according to an embodiment of the present invention.

In Figure 1, lO^ is the system bus, 10B
is an internal bus. 11 to 30 are components connected to the system bus IOA, respectively. Among these components, 11 is a CPU (main CPU) that controls the entire system, and here it is a bus that accesses the BIOS-ROM 12 when the power is turned on and outputs a memory refresh signal as shown in Figure 3. (System bus IOA or internal bus 10B
) executes startup processing including an initialization routine to determine the

12 is B I 05-R where fixed programs etc. are stored.
The OM includes a processing routine for executing the processing shown in FIG. 3 in the initialization processing program.

A RAM 13 constitutes a main memory in which programs, data, etc. to be processed are stored, and is composed of a plurality of dynamic RAMs. This RAM 13 is connected not only to the system bus lO^ but also to the internal bus IOH. 14 is a DMA controller (DMA controller) that performs direct memory access control.
t Mea+ory Access Control
er).

15 is a refresh signal generation circuit (R2O) that generates a refresh signal for memory refresh;
According to the contents of the control bit (C) of the refresh control register (RFR) 15a, the system bus lOA,
Alternatively, the configuration is such that a memory refresh signal is selectively output to the internal bus 10B. The details of the configuration of this refresh signal generation circuit (R2O) 15 will be described later with reference to FIG.

16 is an interval tie 7 that can be set by the program.
(PIT; Program IIable I
Interval Tiger ), here we use a programmable interrupt controller (PI
C; Prograsg+ableInterrupt
Controller). 17 is a clock module (RTC; Rea) with its own operating battery.
l-Time C1ock), and stores information that needs to be kept at all times, such as system control information, in addition to date and time information.

18 is an additional RA installed in the dedicated card slot of the main unit.
Determine the read/write cycle time according to the type of M40 (here, it is assumed that the old type low-speed memory card is configured with IMB or 2MB, and the new type high-speed memory card is configured with 4MB or 8MB). A wait controller (WA) switches the wait time and controls access to the additional RAM (memory card) 41.
IT-CONT). This wait controller (WAIT-CONT) 18, like the RAM 13, is connected not only to the system bus IOA but also to the internal bus JO.
It is also connected to B.

19 is a backup RAM that serves as a data storage area to realize the resume function, and a backup power supply (
V BK) is supplied.

Reference numeral 20 denotes an expansion bus connector (EBC) for functional expansion, to which various expansion optional devices mounted on the expansion unit 41, such as an expansion memory board, a communication board, etc., are connected.

21 connects the main body of the personal computer to the hard disk (
HDD) This is a hard disk controller (HDC) for connecting the hard disk back stored in the main body as an interface when upgrading the system to a mounting type (one HDD and one FDD installed). The hard disk back 4 is connected via the built-in connector 42 provided in the hard disk storage section in the main body.
3 are interfaced.

22 is a floppy disk controller (FCC), which in this case is a floppy disk drive (FD).
D) 35 is the controlled object.

23 is a printer controller (PRT, -CONT
), and, for example, a 5-inch external floppy disk drive 44 or a printer 45 is selectively connected via a connector. 24 is input/output interface 7 ace (
U A RT ; Universal＾5ynchr
onousReceiver/Transaitter
), and an R8-232G interface device 46 or the like is connected as necessary.

25 is a keyboard controller (KBC);
Here, input from a keyboard 36 provided integrally with the main body of the device on which the CPU board is mounted is controlled. 26 is a display controller (DISP-CONT'), which is an LCD 3 with a backlight (or sidelight) mounted on a display housing rotatably attached to the main body of the device.
Although only CR7 is targeted for display drive, it is also possible to control the display drive of CR7 display section 47 as an external display. 27 is backup power supply (V BK)
bidet, tRAM (VRAM), 2g is Kanji RO which obtains Kanji character pattern from fi character coat.
M, 29 is a dictionary ROM that realizes a kana/kanji conversion dictionary, etc.
It is.

30 is power supply circuit (intelligent power supply) 3
2 to the CPU II via the system bus IOA, and here, the power control CPU of the power supply circuit 32
It has a serial-to-parallel conversion function for data transfer between PC and CPU via a serial interface. Reference numeral 31 denotes a power adapter (hereinafter referred to as AC adapter) which rectifies and smoothes a commercial alternating current power source (AC) to obtain a DC working power source of a predetermined potential, and is plug-in connected to the main body of the personal computer. 32 is a power supply circuit (intelligent power supply) equipped with a power control CPU (PC-CPU); 33 is a power switch that turns on/off the power of the personal computer;
4L and 34R are main battery packs (M-BATA, M-BATB) that are removable from the main body of the device (PC main body), each consisting of a rechargeable battery.
), where ゛ is selected under the control of the power supply circuit 30 during driving as one of the batteries to be used (power supply target), and when that battery is discharged to its usage limit, the battery to be used is selected. switched,
The other battery will be used. 34S is a built-in sub-battery (S-BAT) composed of the same rechargeable battery, and has a RAM of 13° expansion R.
A M 40. A backup power supply (VBK) is supplied to memories that require backup, such as the video RAM 27.

Reference numeral 40 denotes an additional RAM that can be inserted into and removed from a dedicated card slot in the main body of the personal computer;
4MB to the existing (old type) memory card of MB,
4 with a new 8MB memory card (new type)
Any one of the various memory cards is implemented. At this time, the existing (old type) memory card (IMB, 2MB
) and new (new type) memory cards (4MB, 8MB)
have different read/write access times,
Old type memory cards (IMB, 2MB) require twice as much wait time (2 waits) as new type memory cards (4MB, 8MB).

Therefore, in order to realize a memory card interface that is shared by the old and new memory card, the weight controller 18 controls the weight value (
1 weight/2 weight). This weight value is set in the I10 port register of the weight controller 18 under the control of cPUll in the initial setting process, and thereafter, each time the mounted expansion RAM 41 is accessed, the weight controller 18 uses the weight set in the register. Access to the mounted additional RAM (memory card) 41 is controlled by read/write cycles according to the value (1 wait/2 wait).

41 is an expansion unit selectively connected to the expansion bus connector (EBC) 20, such as an expansion memory board,
Various optional equipment for expansion, such as communication boards, will be installed.

This expansion unit 41 is an expansion bus connector (EBC) 2
0, the refresh signal is output to the system bus IOA, and the operation of the expansion memory board, communication board, etc. of the expansion unit 41 is controlled using the refresh signal. For example, for an extended memory board, refresh control is performed using a refresh signal on the system bus IOA, and for a communication board, execution of timeout processing and the like is controlled. In addition, the refresh operation of the RAM 13 and additional RAM (memory card) 41 is also performed using the system bus I
Controlled by the refresh signal on OA.

On the other hand, the expansion unit 41 is an expansion bus connector (EBC)
20, the refresh signal is output to the internal bus IOH and not to the system bus IOA. In this case, RAM13 and mounting expansion R
The refresh operation of the AM (memory card) 41 is controlled by a refresh signal on the internal bus IOB.

42 connects the main body of the personal computer to a hard disk (
HD D) Mounting type (one HDD and one FDD installed)
This is a built-in connector for connecting a hard disk back housed in the main body as an interface when the system is upgraded, and a hard disk back 43 is connected as an interface via this connector 42.

FIG. 2 is a circuit diagram showing the main part of the refresh signal generation circuit 15 in the above embodiment.

The refresh signal generation circuit 15 includes a refresh control register (RFR) 15 as shown in FIG.
In addition to a, a refresh signal switching circuit 15b is provided. The refresh signal switching circuit 15b is for selectively outputting the refresh signal RF generated by a signal generating section (not shown) in the circuit 15 to the system bus IOA and the internal bus IOB, and
CPU1 determines whether to output to A or internal bus 10B.
Refresh control register (RFR) 15a by l
It is determined by the contents of the control bit (C) set in . That is, control bit <C> is “
1', the AND gate Gl is activated, so that the refresh signal RF is equal to the refresh signal RFa.
It is output to the internal bus IOB as . Further, when the control bit (C) is 02, the AND gate G2 is activated, and thereby the refresh signal RF is outputted to the system bus IOA as the refresh signal RFb.

FIG. 3 shows the bus (system bus IOA or internal bus IOA) that outputs the memory refresh signal in the above embodiment.
3 is a flowchart showing an initial setting routine for determining OB).

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 to 3 above.

When the personal computer main body is powered off, the power switch 33 is operated to turn on the personal computer main body, and when normal system power is supplied from the power supply circuit 32 to each component in the main body, the C
PUII accesses BIOS-ROM12 and
Execute the startup process as shown in the figure.

Here, first, normal initial setting processing upon power-on is executed, and then it is determined whether the expansion device, that is, the expansion unit 41 is connected to the expansion bus connector 20 (step SL in FIG. 3). Whether or not the expansion unit 41 is connected can be determined, for example, by the CPU II performing a process of reading unique identification information provided in the expansion unit 41, and whether or not the reading of the identification information has been executed normally. .

When it is recognized that the expansion unit 41 is connected to the expansion bus connector 20, the CPU II activates the refresh signal generation circuit (RSG) to output the refresh signal RFb to the system bus IOA (setting the normal refresh mode). The control bit (C) of the refresh control register (RF R) 15a provided in the refresh control register (RF
When set to 2, the refresh signal generation circuit (RSG
) 15 in FIG. 2 outputs the refresh signal RFb to the system bus 10A (step 513), and then enters normal O8 startup processing (step 816).

In this way, the expansion unit 41 connects the expansion bus connector 20
If the expansion unit 4 is connected to the expansion unit 4, the refresh signal RFb is output to the system bus 10A.
The expansion memory board and communication board 1 can use the refresh signal RFb to control refresh control and timeout processing, and the expansion unit 41 operates normally in synchronization with the main body of the personal computer. is guaranteed. In addition, RAM13 and expansion R
AM40 can also perform a refresh operation using the refresh signal RFb on the system bus IOA.

On the other hand, if it is recognized that the expansion unit 41 is not connected to the expansion bus connector 20, the CPU II
In order to output the refresh signal RFa to the internal bus tab (setting the high-speed refresh mode), set the control bit (C) of the refresh control register (RFR) 15a provided in the refresh signal generation circuit (RSG) 15 to "l". (Step 514). When the control bit (C) is set to "1", the refresh signal switching circuit L5b of FIG. 2 provided in the refresh signal generation circuit (RSG) 15 switches the internal bus IOH The refresh signal RFa is outputted (step 515), and then normal O8 startup processing begins (step 516).

In this way, the expansion unit 41 connects the expansion bus connector 20
If the refresh signal RFa is not connected to the internal bus 10B, the refresh signal RFa is output to the internal bus 10B, so the refresh operation of the RAM 13 and the additional RAM 40 is controlled by the refresh signal RFa on the internal bus 1 (IB). In this case, Since the refresh signal is not output to the system bus IOA, the exclusive period of the system bus IOA due to this refresh signal is eliminated, making it possible to use the system bus IOA more efficiently.Therefore, the system bus IOA can be used more efficiently. The operating efficiency of each component increases, thereby improving the operating performance of the entire system.

[Effects of the Invention] As described in detail above, according to the present invention, a personal computer having an expansion bus connector connected to a system bus and a memory that requires refreshing connected to an internal bus. , a means for determining whether an expansion unit is connected to the expansion bus connector, and a means for outputting a refresh signal to the system bus when an expansion unit is connected to the expansion bus connector; By having a configuration including means for outputting a refresh signal onto the internal bus when no expansion unit is connected, the refresh signal is output onto the system bus only when an expansion unit is connected to the expansion bus connector. It is possible to guarantee the operation of the expansion device without causing a deterioration in the operating performance of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the system configuration in one embodiment of the present invention, FIG. 2 is a circuit diagram showing the main part of the refresh signal generation circuit in the above embodiment, and FIG. 3 is a block diagram showing the main part of the refresh signal generation circuit in the above embodiment. 3 is a flowchart showing a start-up processing flow when the power is turned on. 10A...System bus, 10B...Internal bus (C
PU bus), II...CPU, 12...ROM, 1
3...RAM. 14・DMA controller (DMAC;
DirectMemory Access Control
ol! er), 15-... Refresh signal generation circuit (RSG), 15a... Refresh control register (RFR), 1B... Interval time v (P
IT; Programsable Interva
l Tiger), 17-... Clock module (RT
C; Real-Time C1ock), 18...
Weight controller (WAIT-CONT), 19
... Backup RAM, 20... Expansion bus connector (EBC), 21... Hard disk controller (HDC), 22... Floppy disk controller (FDC), 23... Printer controller (PR)
T-CONT), 24... Input/output interface (UART; Llnlversal Asyn
chronousRece1ver/Transmit
ter), 25-...Keyboard controller (WB
C), 26...Display controller (D I 5P-C
ONT), 27...Video RAM (VRAM),
28...Kanji ROM, 29...Dictionary ROM. 30...Power control interface (PS-IF),
31...Power adapter (AC adapter), 32...
Power supply circuit (intelligent power supply), 33.
...Power switch, 34L, 34R...Main battery (M-BAT^, M-BATB), 34S.
...Sub battery (S-BATT), 35...
Floppy disk drive (FDD), 38...Keyboard, 37...LCD, 40...Additional RAM
(Memory carton, 41...Expansion unit, 42...
・Built-in connector, 43...Hard disk pack. Applicant's representative Patent attorney Takehiko Suzue C■゛1"; RFa C-'0"; RFb Figure 2 Figure 3

Claims (1)

[Claims] In a personal computer having an expansion bus connector connected to a system bus and memory that requires refreshing connected to an internal bus, determining whether an expansion unit is connected to the expansion bus connector. means for outputting a refresh signal onto the system bus when an expansion unit is connected to the expansion bus connector, and outputting a refresh signal onto the internal bus when no expansion unit is connected to the expansion bus connector; 1. A personal computer comprising means for outputting a refresh signal onto a system bus only when an expansion unit is connected to the expansion bus connector.