JPH04192176A - D-ram - Google Patents

Abstract

PURPOSE:To save electric power consumption and to increase the scale of integration over the entire part of elements by supplying a constant voltage to respective I/F buffers and the constant voltage lower than this constant voltage to the main part of the D-RAM respectively by two power sources and suppressing a control signal in accordance with drop of the constant voltages. CONSTITUTION:The power source of VCC 5V is supplied to the respective I/F buffers 2, 3, 4 and the power source of internal VCC 3.3V is supplied to the main part 1. A comparator 5a of a voltage alarm circuit 5 outputs a high- level voltage alarm signal (a) to an inhibit circuit 1a to suppress the CS signal to put the main part 1 into a non-selection state when the VCC power source falls to <=4.3V. The main part 1 is supplied with the internal VCC power sources 3.3V at all times even if there is no more supply of the VCC power source and, therefore, the respective memory cells are refreshed by a refresh controller and the data are held. Then, the use of the batteries consuming less electric power is possible and there is no need for considering the level matching of the respective control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D-RAM that operates with low power consumption and low voltage when backed up by a battery.

[Prior Art] FIG. 4 is a block circuit diagram showing a conventional D-RAM. In the figure, (1a) is the main part of the D-RAM that performs R/W control of input data, including MemoryArray,
5ense Amps & Ilo Gate
s, Column Decoder.

It is composed of a Row Decoder and the like.

(2) is a 1/F buffer for data, and Memo “y
Data read from Array (Do)
In addition to outputting to the outside via out Buffer, Dat is used to write data (Di) from the outside.
Output to a out Buffer.

(3) is a control I/F buffer, which reads and writes WE (write enable), C6 (column strobe), and RAS (row address strobe), respectively.
ock Generator, C8C1ock G
enerator and RAS C1ock Gen
Output to erator.

(4) is an address I/F buffer, and the address buses AO to A8 are connected to Row Address B.
uffer and Column Address B
Output to uffer.

(6) is a voltage drop circuit (Voltage Dr.

pper) to lower the VCC5V power supply to 3.3V and output it to the main part (IA) of the D-RAM.

The conventional D-RAM is configured as described above, and the D-RAM is configured as described above.
In today's world where high-density RAM is required, in order to reduce power consumption and operate at low voltage, the design rule is set to 0.5 μm or less, and VCC3, 3Vl
:The D-RAM was operating during the descent.

[Problem to be solved by the invention] In the conventional D-RAM configuration as described above, VCC5V
Since the power supply is reduced internally, power consumption increases, and when backing up the memory with a battery, the capacity of the battery must be increased.

Additionally, if each D-RAM cell is designed to operate at a low voltage of 3.3V, the input/output interface of the D-RAM operates at a general TTL level (5V), so it can be operated using a level converter. The problem was that the levels had to be aligned.

The present invention was made to solve such problems, and an object of the present invention is to reduce power consumption during battery backup to lower battery capacity, and to obtain a D-RAM that can operate at low voltage. do.

[Means for Solving the Problems] A D-RAM according to the present invention has a D-RAM supplied with a constant voltage.
1/F buffer section for RAM control, data, and address, and D that receives a constant voltage lower than the above constant voltage.
- The main part of the RAM, a voltage alarm circuit that outputs a voltage alarm signal when the constant voltage drops below a predetermined reference value, and a chip select signal that selects the D-RAM based on the voltage alarm signal from the voltage alarm circuit. It has an inhibit circuit that suppresses this.

[Function] In the present invention, a constant voltage is supplied to the control, data, and address I/F buffer sections of the D-RAM, and a constant voltage lower than the constant voltage is supplied to the main parts of the D-RAM. The voltage alarm circuit outputs a voltage alarm signal to the inhibit circuit when the constant voltage falls below a predetermined reference value, and the inhibit circuit inhibits the chip select signal for selecting the D-RAM. And the above D-R
Since the main part of the AM is supplied with a low constant voltage, the data stored in each memory cell is retained.

[Embodiment] Figure 1 is a block circuit diagram of an embodiment of the present invention, and Figure 2 is a circuit diagram showing details of the voltage alarm circuit in Figure 1.
2) to (4) are the same as the conventional one.

In the figure, (1) is the main part of D-RAM, and Memo
ry Array, 5ense Amps & I
lo Gates, Column Decoder
, Row Decoder, C3C1ock
Inhibit circuit that suppresses the Generator (1a
), etc., and the stored data is retained. Further, the inhibit circuit (1a) is composed of an OR circuit, and suppresses the cs times signal by a signal from a voltage alarm circuit (described later). In addition, each 1/F buffer (2
), (3), and (4) are supplied with VCC power 5■.

(5) is a voltage alarm circuit, which is composed of a comparator (5a) and each resistor, and outputs a voltage alarm signal (a) to the inhibit circuit based on a drop in the vCC power supply 5V.

Note that each of the resistors R1 to R4 is set as follows. R
2-10-R1, R4- (30/13) ・R3 (6) is a power pin that corresponds to the internal VCC power supply (3,3V), and is connected to the main part (1 ).

The D-RAM of the present invention is configured as described above, and FIG. 3 is a timing chart showing the operation of FIG.
Explain the operation.

First, each 1/F buffer 7 (2), (3), (4)
l;: let V CC3V power is supplied, and
The main part (1) is supplied with an internal VCC of 3.3V. Then, this D-RAM is accessed and data is read/written by a command from the central processing unit (not shown).
When the HR/W control signals (WE, C5, RAS) are sent to the control I/F buffer (3), the data is sent to the data ■/F buffer (2), and the data is sent to the address 1/F buffer (4).
), enter the address. Also, voltage alarm [1i (5
)'s comparator (5a) always monitors the vCC5v power supply, and if the vCC power supply is 4.3v or higher, it outputs a low-level voltage alarm signal (a) to the inhibit circuit (1a
) and without suppressing the C8 signal, the main part (1
) is selected.Next, when the CC power supply drops below 4.3V, the comparator (5a) of the voltage alarm circuit (5)
) outputs a high-level voltage alarm signal (a) to the inhibit circuit (1a) to suppress the C8 signal and
) to the non-selected state. The main part (1) is always supplied with the internal vCC power of 3.3 V even when the CC power is no longer supplied, so each memory cell is refreshed by the refresh controller and the data is retained.

In this way, even if the CC power supply drops, the voltage alarm circuit (
5) and the inhibit circuit (1a), the C8 signal can be suppressed and the main part (1) can be held by an external low voltage power supply, so a battery with low power consumption can be used. There is no need to consider level matching of each control signal, etc.

[Effects of the Invention] As described above, according to the present invention, a constant voltage is supplied to each I/F buffer, and a constant voltage lower than the constant voltage is supplied to the main part of the D-RAM by two power supplies, and the constant voltage is Since the control signal is suppressed based on the drop, even if the constant voltage drops, only one of the lower constant voltages is required, allowing operation with low power consumption. Moreover, the degree of integration of the entire device can be increased by supplying the device with two power supplies rather than with a single constant voltage power supply.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram showing details of the voltage alarm circuit of Fig. 1, Fig. 3 is a timing chart showing the operation of Fig. 2, and Fig. 4 is a circuit diagram showing details of the voltage alarm circuit of Fig. 1. FIG. 1 is a block circuit diagram showing a conventional D-RAM. In the figure, (1) is the main part of D-RAM, (1a) is the inhibit circuit, (2) is the data 1/F buffer,
(3) is 1/F buffer for control, (4) is I for address
/F buffer, (5) is a voltage alarm circuit, and (6) is a power supply bin. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Scope of Claims] An I/F buffer section for control, data, and address of the D-RAM that is supplied with a constant voltage, and a main part of the D-RAM that is supplied with a constant voltage that is lower than the constant voltage. , a voltage alarm circuit that outputs a voltage alarm signal when the constant voltage drops below a predetermined reference value; and an inhibit circuit that suppresses a chip select signal that selects the D-RAM by the voltage alarm signal from the voltage alarm circuit. A D-RAM characterized by having the following.