JPH04188975A - Image display device - Google Patents

Abstract

PURPOSE:To reduce a power consumed in a transistor for current amplification and a transistor for current source and to suppress heat generation by reducing a current that flows on the transistor for current amplification at a time other than before and behind the change point of a vertical deflection signal. CONSTITUTION:A large quantity of collector currents are permitted to flow on the transistor 56 for current source to accelerate the on/off speed of output buffer transistors 58, 59 at the time before and behind the change points of variable vertical deflection signals v, v', and the on/off speed of the output buffer transistors 58, 59 are accelerated. In a period where the variable vertical deflection signals v, v' remain unchanged, no output buffer transistors 58, 59 are operated, therefore, only a small quantity of collector currents is required. Thereby, it is possible to reduce the power consumed in the transistor 55 for current amplification and the transistor 53 for current source and to suppress the heat generation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates an electron beam for each division when a screen on a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. The present invention relates to an image display device that displays a plurality of lines by deflecting a beam in the vertical direction to display an image as a whole.

2. Description of the Related Art The basic structure of a conventional image display device will be explained with reference to FIG.

This display element consists of a back electrode 1, a line cathode 2 as a beam source, a beam extraction electrode 3, a beam flow control electrode 4, a focusing electrode 5, a horizontal deflection electrode 6, a vertical deflection electrode 7, and a screen in order from the back to the anode side. A plate 8, etc. are arranged, and these are housed inside the vacuum container.

A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction.
A plurality of line cathodes 2 are further provided at intervals in the vertical direction (in this description, only seven line cathodes 2A to 2G are shown). In this configuration, the spacing between the line cathodes is 4.4 mm, and the number of line cathodes is 19, and the number of line cathodes is 2 to 2.

The distance between the line cathodes cannot be freely increased, but is regulated by the distance between the vertical deflection electrode 7 and the screen 8, which will be described later. The composition of these line cathodes 2 is 10 to 30.
An oxide cathode material is applied to the surface of a tungsten rod with a diameter of μm. As will be described later, the line cathodes are controlled to sequentially emit electron beams from the upper line cathode 2A to the lower line cathodes 2A for a certain period of time. The back electrode 1 has the function of suppressing the generation of electron beams from line cathodes other than the corresponding line cathode, and also has the function of pushing the electron beams only toward the anode. Although the vacuum container is not shown in FIG. 3, it is also possible to adopt a structure in which the back electrode 1 is used to integrate the back electrode 1 with the vacuum container. The beam extraction electrode 3 is the line cathode 2-2
A conductive plate 11 having a large number of through holes 10 arranged at regular intervals in the horizontal direction facing each of the two holes,
The electron beam emitted from the line cathode 2 is taken out through the through hole 10. Next, the control electrode 4 is composed of a vertically long conductive plate 15 having a through hole 14 at a position facing each of the line cathodes 2A to 2A, and a plurality of conductive plates 15 are arranged horizontally at predetermined intervals. has been done. In this configuration, 114 control electrode conductive plates 15a to 15n are provided (
In Figure 3, only eight are shown). The control electrode 4 controls the amount of passage of each of the electron beams divided horizontally by the beam extraction electrode 3 in accordance with the picture elements of the video signal and in synchronization with the timing of horizontal deflection, which will be described later. . The focusing electrode 5 is a conductive plate 17 having a through hole 16 at a position facing each through hole 14 provided in the control electrode 4, and focuses the electron beam. Horizontal deflection electrode 6
is composed of a plurality of conductive plates 18.18'' arranged vertically along both horizontal sides of the through hole 16, and a horizontal deflection voltage is applied to each conductive plate. The electron beams for each picture element are each deflected in the horizontal direction, and emit light by sequentially irradiating R, G, and B phosphors on the screen 8. In this configuration, two trios are used for each electron beam. Vertical deflection electrode 7
is composed of a plurality of conductive plates 19 and 19' arranged horizontally at vertically intermediate positions of the through holes 16, and a vertical deflection voltage is applied to the conductive plates 19 and 19' to deflect the electron beam in the vertical direction. are doing. In this configuration, a pair of electrodes 19
．． 19' deflects the electron beam generated from one line cathode by 12 lines in the vertical direction. The 20 vertical deflection electrodes 7 constitute 19 pairs of vertical deflection conductors corresponding to each of the 19 line cathodes, and draw 228 horizontal scanning lines in the vertical direction on the screen 8. ing. As explained above, in this configuration, the horizontal deflection electrode 6. A plurality of vertical deflection electrodes 7 are arranged in a shape. Further, by setting the distance to the screen 8 longer than the distance between the horizontal and vertical deflection electrodes, it becomes possible to irradiate the screen 8 with the electron beam with a small deflection amount. This allows for horizontal and vertical deflection electrodes. As shown in FIG. 3, the screen 8 is constructed by coating the back surface of a glass plate 21 with phosphor 20 in stripes. Although not shown, a metal back and carbon are also coated. The phosphor 20 is provided so as to irradiate two trios of R, G, and H phosphor pairs by horizontally deflecting an electron beam passing through one through hole 14 of the control electrode 4. , applied in vertical stripes. In FIG. 3, the broken lines drawn on the screen 8 represent the plurality of wire cathodes 2.
The vertical divisions displayed corresponding to each of the plurality of control electrodes 4 are shown, and the dashed-two dotted lines indicate the horizontal divisions displayed corresponding to each of the plurality of control electrodes 4. FIG. 4 shows an enlarged view of one section partitioned by broken lines and two-dot chain lines.

As shown in Figure 4, in the horizontal direction, R and G for two trios.
, B has a width of 12 lines in the vertical direction. In this example, the size of one section is 1+m++ in the horizontal direction,
It is 4.4g in the vertical direction.

Although the phosphors of each of the three colors R, G, and B are shown in stripes in FIG. 4, they may be arranged in a delta.

However, when arranged in a delta shape, it is necessary to apply horizontal and vertical deflection waveforms that are compatible with the arrangement.

In FIG. 3, for convenience of explanation, the aspect ratio is different from the image displayed on the actual screen. In addition, in this configuration, R, G and G
, H phosphors are provided for two trios, but it may be composed of one trio or more than three trios. However, the control electrode 4 has one trio or more than three trios of R.
,G.

The B video signal is applied sequentially, and it is necessary to perform horizontal deflection in synchronization with it.

Next, the operation of the drive circuit for driving this display element will be explained with reference to FIG. First, a driving portion that irradiates the screen 8 with an electron beam to display an image will be explained. The power supply circuit 22 is a circuit for applying a predetermined bias voltage to each electrode of the display element.Vl is applied to the back electrode 1, V3 is applied to the beam output electrode 3, V5 is applied to the focusing electrode 5, and V8 is applied to the screen 8. Apply DC voltage. The line cathode drive circuit 26 is
A line cathode drive pulse (I) is created using the vertical synchronization signal V and the horizontal synchronization signal H. FIG. 7 shows the timing diagram. As shown in Figure 7 (A-C), each line cathode 2A to 2S is heated by a current flowing during the period when the drive pulse is at a high potential, and during the period when the drive pulse (A to C) is at a low potential. The heated state is maintained so that electrons are emitted. This results in 1
Electrons are emitted from the nine line cathodes 2-2 only during 12 horizontal scanning periods to which low-potential drive pulses (1-2) are applied. During the period in which a high potential is applied, the potential applied to the line cathodes 2A to 2 is higher than the potential around the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the beam extraction electrode 3. Since the potential is higher, no electrons are emitted from the wire cathode. To construct one screen, the potentials may be sequentially switched from the upper line cathode 2A to the lower line cathode 2A every 12 scanning periods.

Next, the deflection portion will be explained. The deflection voltage generation circuit 40 includes a direct memory access controller 41 (hereinafter referred to as DMA controller), a deflection voltage waveform storage memory 42 (
(hereinafter referred to as deflection memory), horizontal deflection signal generator 43h1
It is composed of a vertical deflection signal generator 43v and the like, and generates vertical deflection signals v, v' and horizontal deflection signals h'.

In this configuration, regarding the vertical deflection signal, one field displays 228 horizontal scanning periods in consideration of overscanning. In addition, the memory address area that stores the vertical deflection position information corresponding to each line is
It is divided into a field and a second field, each having one set of memory capacity.

When displaying, data is read from the corresponding deflection memory 42, converted into an analog signal by the vertical deflection signal generator 43V, and applied to the vertical deflection electrode 7. The vertical deflection position information stored in the deflection memory 42 is composed of almost regular data for every 12 horizontal scanning periods, and the waveform converted into a deflection signal is also a vertical deflection signal with approximately 12 steps. As mentioned above, the memory capacity for two fields is increased so that the position can be finely adjusted for each horizontal scanning line. Regarding the horizontal deflection signal, it is necessary to horizontally deflect the electron beam in six stages during one horizontal scanning period, and a memory is provided so that the deflection position can be finely adjusted for each horizontal scanning. Therefore, assuming that 456 horizontal scanning periods are displayed between one frame, 456 x 6 = 2736 bytes of memory are required, but since the data of the first field and the second field are shared, the memory is actually 1368 bytes. is using memory. During display, deflection information corresponding to each horizontal scanning line is read out from the deflection memory 42, converted into an analog signal by a horizontal deflection signal generator 43h, and applied to the horizontal deflection electrode 6.

The vertical deflection signal generator 43v includes a D/A converter 80. which converts deflection data into analog current. It consists of an operational amplifier 81 and resistors 82 and 83 that convert the current into voltage, amplifiers 84 and 85 that make the voltage symmetrical, and high voltage amplifiers 86 and 87 that amplify the voltage to the high voltage required for vertical deflection. The operation of the vertical deflection signal generator 43v will be explained using FIG. 6 and FIG. 7 showing the waveform of the vertical deflection signal. Vertical deflection data is read from the deflection memory 42 and sent to the D/A converter 80 where it is converted into an analog current. The analog current is
Opamp 81 and resistance! Convert to analog voltage by 82.83. The voltage signal is connected to a 1x amplifier 84 and 11
A double amplifier 85 converts the signals into symmetrical signals, which are amplified by high-voltage amplifiers 86 and 87, respectively, to generate vertical deflection signals v and v' for beam deflection.

Here, as shown in FIG. 2, the high voltage amplifiers 86 and 87 receive the signal from the amplifiers 84 and 85 and input it to the transistor 51 and resistor 60 of the differential amplifier, and the other transistor 52 of the differential amplifier. Non-inverting amplification is performed by the transistor 54 and resistor 63 which are connected in cascade. This is received by the current amplifying transistor 55, and output buffer transistors 58 and 59 output a high voltage vertical deflection signal. Here, the transistor 53 and the resistor 62 are the current sources of the differential amplifier, the transistor 56 and the resistor 64 are the current sources of the current amplification transistors, and the resistors 70 and 71 are the feedback resistors and resistors that determine the degree of amplification. 68.69 is a protection resistor of transistor 58.59 of the output buffer. Capacitor 72 prevents oscillation. Power supply 74.75
determines the bias voltage of the current source. A power supply 76 determines the center voltage of the vertical deflection signal. The power supply 73 determines the base voltage of the transistors 54 connected in cascade. Power supply 77 is a power supply for the high voltage amplifier. The operation of the high voltage amplifier will be explained. The vertical deflection signals converted into symmetrical signals by amplifiers 84, 85 are transmitted to transistors 51, 52, 54 . Non-inverting amplification is performed by resistor 63. This is the current amplification transistor 5
After the receiving current is amplified in step 5, a high-voltage vertical deflection signal is outputted by transistors 58 and 59 of the output sofa. The amplification degree of the high voltage amplifier is determined by the feedback resistor 70,71.

To summarize, during the display period excluding the vertical retrace period of the vertical period, the electron beam emitted from the line cathode to which a low-potential driving pulse is applied among the line cathodes 2i to 2so is the beam. It is horizontally divided into 114 sections by the extraction electrode 3, forming 114 electron beam rows. This electron beam is applied to control electrodes 4 for each section as described later.
The amount of beam passing is controlled by the beam, and after the beam is focused by the focusing electrode 5, a pair of horizontal deflection signals which change in approximately six steps as shown in FIG. R1, Gl, Bl and R2, G2 . The phosphors such as B2 are sequentially irradiated for each horizontal display period/6. Thus, each horizontal line raster directs the electron beam to R1, G1 . Bl and R2, G2. By modulating with the video signal corresponding to B2, a color image can be displayed on the screen 8.

Next, the modulation control portion of the electron beam will be explained.

First, in FIG. 5, the signal input terminal 23R123G,
Each R, G, and B video signal added to 23B is 114
sample and hold circuit sets 31a-31n. Each sample hold group 31a to 31n is for R1 and Gl, respectively.

It is composed of six sample and hold circuits for B1, R2, G2, and B2. The sampling pulse generation circuit 34 generates signals for each of the 114 sample and hold circuits 31a to 31n for R1 during a horizontal display period (approximately 50μ5ec) of the horizontal period (63.5μsec).
684 (114×6) sampling pulses Ral to Rn2 corresponding to sample hold circuits for Gl, Bl, R2, G2, and B2 are sequentially generated. Six of the 684 sampling pulses are added to each of the 114 sample-and-hold circuit sets 31a to 31n, so that each sample-and-hold circuit set has two picture elements for each of the 114 segments of one line. Minute R1, G1. Bl, R2°G2. Each B2 video signal is individually sampled and held. 114 sample-held pairs of R1, Gl, Bl, R2, G2 . B
After the sample and hold for one line is completed, the video signals of No. 2 are transferred all at once to 114 sets of memories 32a to 32n by a transfer pulse t, where they are held for the next one horizontal scanning period. The held signal is sent to 114 switching circuits 3
Added to 5a-35n.

The switching circuits 35a to 35n each have R1 and G.
l, B1. R2, G2. The switching pulse generation circuit 3 is composed of a circuit having individual input terminals of B2 and a common output terminal that sequentially switches and outputs them.
Switching pulses rl, gl, bl applied from 6
, r2. Switching is controlled simultaneously by g2 and b2. The switching pulses rl, gl, bl, r2. g
2°b2 divides each horizontal display period into 6 and switches the switching circuits 35a to 35n by 6 horizontal display periods R1, G1 . Bl, R2, G2. Each video signal of B2 is time-divided and output sequentially, and the pulse width modulation circuits 37a to 37n
is supplied to. The output of each switching circuit 35a to 35n has 114 sets of pulse width modulation (hereinafter referred to as PWM).
added to the circuits 37a to 37n, R1, Gl, Bl, R
2°G2. The pulse width is modulated according to the magnitude of each B2 video signal and output. These pulse width modulation circuits 37a to 3
7n is used as a control signal for modulating the electron beam to the 114 conductive plates 15a to 1 of the control electrode 4 of the display element.
5n separately.

Next, horizontal deflection and display timing will be explained.

R1. in the switching circuits 35a to 35n. Gl,
Bl, R2, G2. B2 video signal switching and electron beams R1, Gl, Bl, by the horizontal deflection drive circuit 41.
R2, G2. The timing and order of switching the horizontal deflection to the B2 phosphor are synchronously controlled so that they completely match. As a result, when the R1 phosphor is irradiated with the electron beam, the irradiation amount of the electron beam is controlled by the R1 control signal, and the following Gl, B1. R2°G2. B2 is also controlled in the same way, and R1, Gl, Bl of each picture element
, R2, G2. B2 The light emission of each phosphor is the R1 of that picture element,
Gl, Bl, R2°G2. Each picture element is controlled by the B2 video signal, and each picture element is displayed by emitting light according to the input video signal. Such control is executed for 1 line of 114 sets (2 picture elements each) to display an image of 228 picture elements per line, and is further performed sequentially for 228 lines of one field starting from the upper line. An image is displayed on the screen 8. Furthermore, the above operations are repeated for each field of the input video signal, and a television signal or the like is displayed on the screen 8.

The basic clock necessary for this configuration is supplied from a pulse generation circuit 39 shown in FIG. 5, and the timing is controlled by a horizontal synchronizing signal H1 and a vertical synchronizing signal V.

Problem to be Solved by the Invention However, in the configuration of the high voltage amplifier 86,87 of the vertical deflection signal generator 43V as described above, in order to increase the on/off speed of the output buffer transistor 58,59, it is necessary to Since it is necessary to flush out the minority carriers, it is necessary to cause a certain amount of current to flow through the current source transistor 56. Therefore, the power consumption of the current source transistor 55 and the transistor 56 which is the current source of the transistor becomes large, and there is also a problem that heat stress is applied to the surrounding mounted components and the life of the components is shortened.

In view of the above problems, the present invention provides an image display device that reduces power consumption of a high voltage amplifier and reduces thermal stress applied to surrounding mounted components.

Means for Solving the Problems In order to solve the above problems, the image display device of the present invention has a screen coated with a phosphor that emits light when irradiated with an electron beam, and a screen above the screen that is vertically divided. a plurality of line cathodes that generate electron beams for each vertical section; a deflection memory that stores deflection data for deflecting the electron beam; and a digital-to-analog converter that converts the deflection data into an analog voltage; Transistors and resistors that differentially amplify the converted voltage, transistors connected in cascade, and transistors that constitute the current source of the differential amplifier.

A resistor and a power supply, a transistor that amplifies the differentially amplified voltage, a transistor and a resistor that is a current source for the current amplification transistor, and a transistor and a resistor that changes the current of the current source of the current amplification transistor. It has an output buffer transistor, a feedback resistor that determines the degree of amplification, and a vertically deflected high power supply that provides a power supply voltage to the amplifier.

Effect of the Invention With the above-described configuration, the present invention reduces the current flowing through the current amplification transistor except before and after the change point of the vertical deflection signal, so that the power consumed by the current amplification transistor and the transistor that is the current source for current amplification is reduced. becomes less,
Fever is suppressed.

Embodiment Hereinafter, an image display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of a high voltage amplifier in a vertical deflection signal generation circuit of an image display device in one embodiment of the present invention.

In Figure 1, 51 and 52 are transistors of the differential amplifier, 54 are transistors connected in cascade to the transistors of the differential amplifier, 63 is a resistor for converting to voltage, and 53 and 62 are for the current source of the differential amplifier. A transistor and a resistor, 55 is a current amplification transistor, 56.64 is a current source transistor and a resistor of the current amplification transistor,
57゜65 is a transistor and resistor for increasing the current flowing through the current amplification transistor before and after the change point of the vertical deflection signal, 58.59 is an output buffer transistor, 7
0.71 is a feedback resistor that determines the amplification degree, 68.69 is a protection resistor for the output buffer transistor, 72 is a capacitor for preventing oscillation, 74.75 is a power supply that determines the bias voltage of the current source, and 76 is a A power supply 73 determines the center voltage of the vertical deflection signal, a power supply 73 determines the base voltage of the transistor 54 connected in cascade, and 77 a power supply for the high voltage amplifier.

The operation of the high-voltage amplifier circuit in the vertical deflection signal generation circuit of the image display device configured as described above will be described below. The vertical deflection signal converted into a symmetrical signal by the amplifiers 84 and 85 is non-invertingly amplified by the transistor 54 and resistor 63 which are cascaded with the transistors 51 and 52 of the differential amplifier. The current is amplified by the current amplifying transistor 55. The emitter current of the current amplifying transistor 55 is generated by a transistor 56 and a resistor 64, which constitute a current source. Here, V current source control pulses synchronized with the changing points of the vertical deflection signals v and v' shown in FIG. 8 are applied to the pulse generating circuit 3.
By taking it out from 9 and applying it to the base of transistor 57, ■When the current source control pulse is high voltage, transistor 57 is turned on, resistor 64 and resistor 65 are connected in parallel, and the emitter current of current source transistor 56 increases. , the collector current also increases. That is, before and after the change point of the variable vertical deflection signals v and v', the output vanoff transistor 5
In order to increase the on/off speed of the output buffer transistor 58.59, a large collector current of the current source transistor 56 is made to flow, thereby increasing the on/off speed of the output buffer transistor 58.59. Since the output buffer transistors 58 and 59 do not operate during the period when the variable vertical deflection signals v and v' do not change, the collector current of the current source transistor 56 may be small.

As described above, according to this embodiment, the variable vertical deflection signals v, v
The power consumed by the current amplification transistor and the current source transistor can be reduced by increasing the current of the current source of the current amplification transistor only before and after the change point of ', and decreasing it during other periods.

Effects of the Invention As described above, according to the present invention, a screen coated with a phosphor that emits light when irradiated with an electron beam;
A plurality of line cathodes that generate electron beams for each vertical division of the above-mentioned screen, a deflection memory that stores deflection data for deflecting the electron beam, and a deflection data that converts the deflection data into analog voltages. A digital-to-analog converter for conversion, a transistor and a resistor for differentially amplifying the converted voltage, a cascade-connected transistor, a transistor, a resistor, and a power supply that constitute a current source of the differential amplifier. , a transistor that current amplifies the differentially amplified voltage, a transistor and a resistor that are current sources for the current amplification, a transistor and a resistor that change the current of the current source of the current amplification transistor, and an output buffer transistor. By providing a feedback resistor that determines the amplification degree, and a vertically deflected high power supply that supplies the power supply voltage to the amplifier, the power consumption of the high voltage amplifier can be reduced, and heat generation can be suppressed, so the surrounding mounted components can be reduced. can reduce heat stress.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a high voltage amplifier in a vertical deflection signal generation circuit of an image display device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a high voltage amplifier in a vertical deflection signal generation circuit of a conventional image display device. 3 is an exploded perspective view of the image display device used in the present invention, FIG. 4 is an enlarged view of the fluorescent screen of the image display device, and FIG. 5 is a block diagram of the drive circuit of the image display device. Figure 6 is a block diagram of the vertical deflection signal generation circuit, Figure 7 is a waveform diagram for explaining the operation of the image display device, and Figure 8 is a waveform diagram of the current source control signal of the high voltage amplifier of the vertical deflection signal generation circuit. be. 51-59...transistor, 60-71...
...Resistor, 72...Capacitor, 73.
... Cascade power supply, 74 ... Vertical deflection negative power supply, 75 ... Current source power supply, 76 ...
...Vertical deflection center power supply, 77...Vertical deflection high power supply. &n-” Pressure increase f11! Kan 2 Zuki 87 /' Mizukikata I's 1 section 40 Gi! +1 pressure Q: Residential 17th lead 5th meter

Claims (1)

[Claims] A screen coated with a phosphor that emits light when irradiated with an electron beam, and a plurality of line cathodes that generate an electron beam in each vertical section of the above-mentioned screen. , a deflection memory that stores deflection data for deflecting the electron beam, a digital-to-analog converter that converts the deflection data into an analog voltage, and a transistor and a resistor that differentially amplify the converted voltage. , the transistors connected in cascade, the transistors, resistors, and power supplies that make up the current source of the differential amplifier, the transistors that amplify the differentially amplified voltage, and the current sources of the current amplifying transistors. A transistor and resistor, a transistor and resistor that changes the current of the current source of the current amplification transistor, an output buffer transistor, a feedback resistor that determines the degree of amplification, and a vertical deflection high voltage that provides the power supply voltage to the amplifier. an image display device having a source;