JPH04188758A - Package lead for surface mounting of semiconductor device - Google Patents

Package lead for surface mounting of semiconductor device

Info

Publication number
JPH04188758A
JPH04188758A JP2317571A JP31757190A JPH04188758A JP H04188758 A JPH04188758 A JP H04188758A JP 2317571 A JP2317571 A JP 2317571A JP 31757190 A JP31757190 A JP 31757190A JP H04188758 A JPH04188758 A JP H04188758A
Authority
JP
Japan
Prior art keywords
lead
solder
hole
package
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2317571A
Other languages
Japanese (ja)
Inventor
Shinji Uchibori
内堀　真司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2317571A priority Critical patent/JPH04188758A/en
Publication of JPH04188758A publication Critical patent/JPH04188758A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of solder bridges 9 among leads, to ensure mechanical strength and to stabilize electrical continuity by forming through- holes to soldering flat sections at lead noses. CONSTITUTION:One or a plurality of through-holes 203 are formed to the flat section of the grounding surface of a lead 202. Consequently, since solder is sucked up to the top face of the lead 202 by a through-hole 203 at the time o assembly, the excess solder is sucked up to the surface of the lead 202 when the quantity of solder is too increased due to the dispersion of a process, etc. A soldered area is increased by the through-hole 203. A needle-shaped contact pin 304 is inserted into the through-hole 303 by using the needle-shaped one as the contact pin 304 on electrical characteristic inspection, and electrical continuity can be conducted. Accordingly, the generation of solder bridges among the leads is prevented, mechanical strength is ensured and electrical continuity is stabilized.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置のパッケージリード形状に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package lead shape for a semiconductor device.

［従来の技術］ 従来の半導体装置のパッケージにおけるリード形状では
、例えば、クワッド・フラット・パッケージ（以下ＱＦ
Ｐとする）、スモール・アウトライン・パッケージ（以
下ＳＯＰとする）では、第４図（ａ）の様なガルウィン
グタイプ、プラスチック・リーデツド・チップ・キャリ
アー（以下ＰＬＣＣとする）では、第４図（ｂ）の様な
Ｊり一ドタイブのリード形状を持つ。従来、これらリー
ドの接地面はフラットな板状の形状で、組立時に、この
部分に半田付けを行ない基板等との電気的導通をはかる
。また、電気的特性検査時においては、同じ”く、この
部分にコンタクトビンを接触させ電気的導通をはかる。[Prior art] For example, the lead shape in a conventional semiconductor device package is a quad flat package (hereinafter referred to as QF).
For the small outline package (hereinafter referred to as SOP), the gull wing type as shown in Figure 4(a), and for the plastic leaded chip carrier (hereinafter referred to as PLCC), as shown in Figure 4(b). ) has a J-type lead shape. Conventionally, the ground planes of these leads have a flat plate-like shape, and during assembly, this part is soldered to establish electrical continuity with a board or the like. Also, when testing electrical characteristics, a contact bottle is similarly brought into contact with this portion to ensure electrical continuity.

［発明が解決しようとする課題および目的］しかし、半
導体装置のパッケージのファインピッチ化に伴い、リー
ド輻自体が細くなり、この接地面の面積が小さくなって
きている。このため、組立時においては、半田付は面積
の減少による機械的強度不足、更には、リードピッチが
狭くなることにより、リード間の半田ブリッジが発生し
易くなるため、特にリフロー装置等で一括して半田付け
を行なう場合には、ペースト半田量を出来るだけ薄く、
少なくするように半田量を厳密に管理する必要がでてき
た。また、このペースト半田が薄くなるとともに、リー
ド間のリード浮きの制限も厳しくなってきている。[Problems and Objects to be Solved by the Invention] However, as semiconductor device packages become finer pitched, the lead radius itself becomes thinner and the area of this ground plane becomes smaller. For this reason, during assembly, soldering is particularly difficult to do all at once using a reflow machine, etc., as the mechanical strength is insufficient due to the reduced area, and furthermore, the lead pitch becomes narrower, making it easier for solder bridges to occur between the leads. When soldering, make the amount of solder paste as thin as possible.
It has become necessary to strictly control the amount of solder to reduce it. Furthermore, as this paste solder becomes thinner, restrictions on lead floating between leads are becoming stricter.

一方、電気的特性検査時においては、この接地面の面積
が小さくなってきていることにより、コンタクトビンを
安定的に接触させることが難しくなってきている。On the other hand, when testing electrical characteristics, the area of this ground plane is becoming smaller, making it difficult to bring the contact bottle into stable contact.

［課題を解決するための手段］ こ°の様な問題を解決するため、本発明では、半導体装
置の表面実装用パッケージリードにおいて、リード接地
面のフラット部に１個または複数個の半田メツキされた
スルーホールを設けたことを特徴とする。[Means for Solving the Problems] In order to solve these problems, the present invention provides a package lead for surface mounting of a semiconductor device in which one or more solder plates are plated on the flat part of the lead grounding surface. It is characterized by having a through hole.

［実施例］ 第１図（ａ）は、本発明のＱＦＰタイプのパッケージで
１個の半田メツキされたスルーホールを設けた実施例を
示す断面図であって、第１図（ｂ）は、その上面図であ
る。１０１は半導体装置のパッケージボディで、１０２
は半導体装置の入出力端子と導通を計ったパッケージリ
ード、１０３は本発明の特徴であるリード先端に設けら
れた半田メツキされたスルーホールである。[Example] FIG. 1(a) is a cross-sectional view showing an example in which a QFP type package of the present invention is provided with one solder-plated through hole, and FIG. 1(b) is a FIG. 101 is a package body of a semiconductor device; 102 is a package body of a semiconductor device;
Reference numeral 103 indicates a package lead for continuity with the input/output terminal of the semiconductor device, and 103 indicates a solder-plated through hole provided at the tip of the lead, which is a feature of the present invention.

第２図は、本発明のパッケージリードを半田付けした時
の断面図を示す。２０１はパッケージボディ、２０２は
パッケージリード、２０３は半田メツキされたスルーホ
ール、２０４は２０３スルーホールによって吸い上げら
れた半田、２０５は組立される基板とパッケージリード
をつなぐ半田。FIG. 2 shows a cross-sectional view when the package lead of the present invention is soldered. 201 is a package body, 202 is a package lead, 203 is a solder-plated through hole, 204 is solder sucked up by the 203 through hole, and 205 is solder that connects the board to be assembled and the package lead.

２０−６は組立される基板を示す。組立時においては、
２０３スルーホールにより、半田がリード上面に吸い上
げられるため、工程バラツキ等によって半田量が多くな
りすぎた場合、この余剰半田はリード表面に吸い上げら
れ、余剰半田によるリード間の半田ブリッジを防ぐ。更
に、このスルーホールにより半田付けされる面積が増加
すことにより、半田付けの機械的強度も増す。20-6 indicates a board to be assembled. During assembly,
Since the solder is sucked up to the top surface of the lead by the through hole 203, if the amount of solder becomes too large due to process variations, this excess solder is sucked up to the lead surface, preventing solder bridging between the leads due to the excess solder. Furthermore, since the area to be soldered is increased by the through-hole, the mechanical strength of the soldering is also increased.

第３図は、電気的特性検査時において本発明のパッケー
ジリードとコンタクトビンにニードル状の物を使用する
ことによって、このスルーホールにニードル状のコンタ
クトビンを挿入し電気的導通を行なった時の断面図を示
したものである。３０１はパッケージボディ、３０２は
パッケージリード、３０３は半田メツキされたスルーホ
ール、３０４はニードル状のコンタクトビンを示す。こ
の様に、ニードル状のコンタクトビンを挿入するため、
リードのファインピッチ化に伴い、リード輻自体が細く
なることによるコンタクトビンの滑り等による接触不良
を防止圧きる。Figure 3 shows the case when electrical continuity is established by inserting the needle-shaped contact bottle into the through-hole by using a needle-shaped object for the package lead and contact bottle of the present invention during electrical characteristic testing. It shows a cross-sectional view. 301 is a package body, 302 is a package lead, 303 is a solder-plated through hole, and 304 is a needle-shaped contact bottle. In this way, in order to insert a needle-shaped contact bottle,
With the finer pitch of the leads, the lead radius itself becomes thinner, which prevents contact failures such as slipping of the contact pin.

［発明の効果１ 以上述べた本発明によれば半導体装置のパッケージのフ
ァインピッチ化に伴い、リード輻自体が細くなったパッ
ケージの半田付けに対しても、リード間の半田ブリッジ
が発生しにくく、機械的強度も確保し易いため、品質、
信頼性に優れた半導体装置の半田付けを提供できる。ま
た、電気的特性検査時においても、ニードル状のコンタ
クトビンを挿入することによって、安定した電気的導通
を提供できる。[Advantageous Effects of the Invention 1] According to the present invention described above, solder bridges between leads are less likely to occur even when soldering packages whose lead radius itself has become narrower due to the finer pitch of semiconductor device packages. Since it is easy to ensure mechanical strength, quality and
It is possible to provide highly reliable soldering of semiconductor devices. Moreover, stable electrical continuity can be provided by inserting a needle-shaped contact bottle even when testing electrical characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明のＱＦＰタイプのパッケージで１個の
半田メツキされたスルーホールを設けた断面図（ａ）と
上面図（ｂ）。 第２図は、本発明のパッケージリードを半田付けした時
の断面図。 第３図は、電気的特性検査時において本発明のパッケー
ジリードにニードル状のコンタクトビンを挿入し時の断
面図。 第４図は、従来のＱＦＰの断面図（ａ）とＰＬＣＣの断
面図（ｂ）。 １０１・・・パッケージボディ １０２・・・パッケージリード １０３・・・スルーホール ２０１・・・パッケージボディ ２０２・・・パッケージリード ２０３・・・スルーホール ２０４・・・吸い上げられた半田 ２０５・・・組立される基板とパッケージリードをつな
ぐ半田 ２０６・・・基板 ３０１・・・パッケージボディ ３０２・・・パッケージリード ３０３・・・スルーホール ３０４・・・コンタクトビン ４０１・・−・パッケージボディ ４０２・・・パッケージリード 以上 出願人　セイコーエプソン株式会社 代理人　弁理士　齢木喜三部（他１名）充１１Ａ（α）
　　　　　　　ネ１邑ｃｂ）昇２邑FIG. 1 is a cross-sectional view (a) and a top view (b) of a QFP type package of the present invention provided with one solder-plated through hole. FIG. 2 is a cross-sectional view when the package lead of the present invention is soldered. FIG. 3 is a cross-sectional view when a needle-shaped contact pin is inserted into the package lead of the present invention during electrical characteristic testing. FIG. 4 is a cross-sectional view of a conventional QFP (a) and a cross-sectional view of a PLCC (b). 101...Package body 102...Package lead 103...Through hole 201...Package body 202...Package lead 203...Through hole 204...Sucked up solder 205...Assembled Solder 206 to connect the board and the package leads...Substrate 301...Package body 302...Package lead 303...Through hole 304...Contact bin 401...Package body 402...Package lead Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Yoshizo Ogi (and 1 other person) Mitsuru 11A (α)
ne 1 eup cb) noboru 2 eup

Claims (1)

【特許請求の範囲】[Claims] 半導体装置のパッケージリードにおいて、リード先端の
半田付けフラット部にスルーホールの穴を設けた事を特
徴とする半導体装置の表面実装用パッケージリード。A package lead for surface mounting of a semiconductor device, characterized in that a through hole is provided in the soldering flat part at the tip of the lead.
JP2317571A 1990-11-21 1990-11-21 Package lead for surface mounting of semiconductor device Pending JPH04188758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2317571A JPH04188758A (en) 1990-11-21 1990-11-21 Package lead for surface mounting of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2317571A JPH04188758A (en) 1990-11-21 1990-11-21 Package lead for surface mounting of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04188758A true JPH04188758A (en) 1992-07-07

Family

ID=18089736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2317571A Pending JPH04188758A (en) 1990-11-21 1990-11-21 Package lead for surface mounting of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04188758A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4313797A1 (en) * 1992-08-06 1994-02-10 Mitsubishi Electric Corp Conductor for bonding in semiconductor chip - has perforated end section through conducting layer for connection to contact bumps on semiconductor chip
WO2010068577A2 (en) * 2008-12-12 2010-06-17 Intel Corporation Anchor pin lead frame

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4313797A1 (en) * 1992-08-06 1994-02-10 Mitsubishi Electric Corp Conductor for bonding in semiconductor chip - has perforated end section through conducting layer for connection to contact bumps on semiconductor chip
WO2010068577A2 (en) * 2008-12-12 2010-06-17 Intel Corporation Anchor pin lead frame
WO2010068577A3 (en) * 2008-12-12 2010-08-19 Intel Corporation Anchor pin lead frame
GB2478071A (en) * 2008-12-12 2011-08-24 Intel Corp Anchor pin lead frame
CN102171822A (en) * 2008-12-12 2011-08-31 英特尔公司 Anchor pin lead frame

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