JPH02137290A - Printed circuit board for packaging electronic parts and electronic device - Google Patents
Printed circuit board for packaging electronic parts and electronic deviceInfo
- Publication number
- JPH02137290A JPH02137290A JP29192688A JP29192688A JPH02137290A JP H02137290 A JPH02137290 A JP H02137290A JP 29192688 A JP29192688 A JP 29192688A JP 29192688 A JP29192688 A JP 29192688A JP H02137290 A JPH02137290 A JP H02137290A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- solder
- printed circuit
- circuit board
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title abstract description 3
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 7
- 238000012790 confirmation Methods 0.000 claims description 6
- 238000007689 inspection Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000000007 visual effect Effects 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000005394 sealing glass Substances 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子部品実装用プリント基板（ボード）及び
それを用いた電子装置に関し、特に、高信頼性な部品高
密度実装技術に適用して有効な技術に関するものである
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a printed circuit board (board) for mounting electronic components and an electronic device using the same, and is particularly applicable to highly reliable component high-density mounting technology. It is about effective techniques.
従来、例えば、リードピンピッチの狭い多ピンのピング
グリッド・アレイ・パッケージ（以下、ＰＧＡという）
を用いた半導体装置をプリント基板に接続する際、半導
体装置のリードピンをプリント基板上のフローパッドに
突当てた状態で半田付けする突き当て方式（Ｂ ｕｔｔ
Ｓ ｏｌｄｅｒｉｇ法）を採用し、表面の配線と裏面
の配線との接続にはスル−ホールを介して行っている。Conventionally, for example, a multi-pin pin grid array package (hereinafter referred to as PGA) with a narrow lead pin pitch has been used.
When connecting a semiconductor device using a semiconductor device to a printed circuit board, the butt method (butt method) is used, in which the lead pins of the semiconductor device are soldered while touching the flow pads on the printed circuit board.
The wiring on the front surface and the wiring on the back surface are connected via through-holes.
また、半導体装置の端子と配線の接合部の確認は、傾斜
ミラーを用いた外観検査機にて行っている（例えば、電
子技術、１９８７年、第６１頁〜第６７頁、″大、中型
コンピュータ″）。In addition, the joints between terminals and wiring of semiconductor devices are checked using a visual inspection machine that uses a tilted mirror (for example, Electronic Technology, 1987, pp. 61-67, "Large and medium-sized computers"). ″).
しかしながら、本発明者は、前記従来技術を検討した結
果、ＰＧＡ型半導体装置のリードピンを面実装する場合
、ＰＧＡ型半導体装置のり−ドピンを実装した後の接続
確認の点についての配慮が足らず、接合部の確認が容易
ではないという問題点を見い出した。However, as a result of studying the above-mentioned prior art, the present inventor found that when surface mounting the lead pins of a PGA type semiconductor device, insufficient consideration was given to the connection confirmation after mounting the PGA type semiconductor device lead pins. We found a problem in that it was not easy to confirm the parts.
本発明の目的は、半導体装置を実装した後、電子部品の
接続部の検査を容易にすることができる技術を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that allows easy inspection of connections of electronic components after mounting a semiconductor device.
本発明の他の目的は、高信頼性な高密度実装を行うこと
ができる技術を提供することにある。Another object of the present invention is to provide a technique that allows high-density packaging with high reliability.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、部品接続用スルーホールを有する電子部品実
装用プリント基板において、前記部品接続用スルーホー
ルの電子部品を実装しない側の径を電子部品のリードビ
ン先端部の径より小さく構成したものである。That is, in a printed circuit board for mounting electronic components having a through hole for connecting components, the diameter of the through hole for connecting components on the side where the electronic component is not mounted is smaller than the diameter of the tip of the lead bin of the electronic component.
また、前記電子部品実装用プリント基板上の部品接続用
スルーホールに、当該電子部品のリードビンを半田で面
実装し、前記半田が前記部品接続用スルーホールの実装
面と反対側の面に露出している電子装置である。Further, the lead bin of the electronic component is surface-mounted to the component connection through hole on the electronic component mounting printed circuit board using solder, and the solder is exposed on the surface opposite to the mounting surface of the component connection through hole. It is an electronic device.
また、前記電子部品のリードピンに、あらかじめ予備半
田を形成し、この形成された予備半田を高温で溶解して
電子部品を面実装すると共に部品接続用スルーホールに
半田を充填して部品接続用スルーホールの実装面と反対
側の面に半田を露出させる電子装置の製造方法である。In addition, preliminary solder is formed on the lead pins of the electronic component in advance, and the formed preliminary solder is melted at high temperature to surface-mount the electronic component, and the through hole for connecting the component is filled with solder. This is a method of manufacturing an electronic device in which solder is exposed on the surface opposite to the mounting surface of the hole.
また、前記部品接続用スルーホールの反対側に露出して
いる半田を利用して目視接続確認検査を行う電子装置の
検査方法である。Further, the present invention is an electronic device inspection method that performs a visual connection confirmation inspection using solder exposed on the opposite side of the component connection through-hole.
前述の手段によれば、電子部品実装用プリント基板上の
部品接続用スルーホール又は電子部品の端子に予備半田
を設け、その予備半田を高温でスルーホールへ挿入実装
することによって、スルーホール内に半田を充填するこ
とができるので、温度サイクル等によるスルーホール断
線を低減することができる。これにより信頼性を向上す
ることができる。According to the above-mentioned means, preliminary solder is provided in the through holes for connecting components on a printed circuit board for mounting electronic components or terminals of electronic components, and by inserting and mounting the preliminary solder into the through holes at high temperature, the through holes can be soldered. Since the solder can be filled, breakage of the through-hole due to temperature cycles or the like can be reduced. This can improve reliability.
また、実装時に押し出された半田を、電子部品実装用プ
リント基板の裏面部分より目視確認することにより、接
続確認検査を行うことができる。Further, by visually checking the solder extruded during mounting from the back side of the electronic component mounting printed circuit board, a connection confirmation test can be performed.
また、前記スルーホールの電子部品を実装する面と反対
面側の径は、リードピンの先端部の径より小さくするこ
とにより、リードピンが貫通しないので、スペーサ部品
を必要とせず、かつ、大きなスルーホールによる配線可
能部分の狭小化を低減することができる。これにより、
実装効率及び布線時性を向上することができる。In addition, by making the diameter of the through-hole on the side opposite to the surface on which electronic components are mounted smaller than the diameter of the tip of the lead pin, the lead pin will not penetrate, eliminating the need for a spacer component and making the through-hole large. It is possible to reduce the narrowing of the wiring area due to This results in
It is possible to improve mounting efficiency and ease of wiring.
以下、本発明の一実施例を図面を用いて具体的に説明す
る。Hereinafter, one embodiment of the present invention will be specifically described using the drawings.
なお、実施例を説明するための全図において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第２図は、本発明の実施例Ｉの電子装置の全体構成の概
略を示す外観斜視図である。FIG. 2 is an external perspective view schematically showing the overall configuration of an electronic device according to Example I of the present invention.
本実施例Ｉの電子装置は、第２図に示すように、厚さが
２．５〜３．０ｍｍのプリント基板（電子部品実装用プ
リント基板）１００の上に、複数個のＰＧＡ型ＬＳＩＩ
、複数個のデイアルインライン・パッケージ（ＤＩＰ）
型ＬＳＩ２、複数のメモリボード３等が実装されたもの
である。そして、それぞれの端子は、ソケット４に集め
られ、外部装置と電気的に接続されるようになっている
。As shown in FIG. 2, the electronic device of Example I includes a plurality of PGA type LSII
, multiple daily inline packages (DIPs)
A type LSI 2, a plurality of memory boards 3, etc. are mounted. The respective terminals are collected in a socket 4 and are electrically connected to an external device.
第３図は、第１図に示すＰＧＡ型ＬＳＩの平面図、第４
図は、第３図に示すＩＶ−ＩＶ線で切った断面図、第５
図は、同ＰＧＡ型ＬＳＩの平面図である。Figure 3 is a plan view of the PGA type LSI shown in Figure 1;
The figure is a cross-sectional view taken along the line IV-IV shown in Figure 3.
The figure is a plan view of the same PGA type LSI.
ＰＧＡ型ＬＳＩＩは、第３図及至第４図に示すように、
ベース１１、該ベース１１上に設けられた配線Ｍ１２．
半導体素子１３．金属細線１４．封止ガラス１５、キャ
ップ１６、半導体素子１３内の内部配線を外部に取り出
すリードピン１７等からなっている。The PGA type LSII, as shown in Figures 3 and 4,
a base 11, a wiring M12 provided on the base 11;
Semiconductor element 13. Fine metal wire 14. It consists of a sealing glass 15, a cap 16, lead pins 17 for taking out internal wiring inside the semiconductor element 13 to the outside, and the like.
前記ＰＧＡ型ＬＳ１１の外形寸法は、例えば、縦横とも
に５０ｍｍであり、その裏面には高さ２゜５〜４．０ｍ
ｍ、径０．４〜０．６ｍｍのリードピン１７が１００ｍ
１ｌ （２，５４ｍｍ）間隔で信号リードピン数２２０
又は２１９本設けられており、例えば、２５６個の入出
力回路を有し、最大２２０の信号を入出力することがで
きる。各入出力回路は、専用の入力・出力回路とともに
独立したベーシックセル（ＢＣ）を持ち、ＮＡＮＤ理論
やフリップフロップの機能を実現できる。これらの機能
により外部信号とのタイミングを入出力回路の遅延効果
のみで実現でき、ＬＳＩの高速性を十分に発揮できるよ
うになっている。The external dimensions of the PGA type LS11 are, for example, 50 mm in length and width, and a height of 2.5 to 4.0 m is provided on the back side.
m, lead pin 17 with a diameter of 0.4 to 0.6 mm is 100 m
Number of signal lead pins 220 at 1l (2.54mm) intervals
For example, it has 256 input/output circuits and can input/output a maximum of 220 signals. Each input/output circuit has a dedicated input/output circuit and an independent basic cell (BC), and can implement NAND theory and flip-flop functions. These functions allow the timing with external signals to be realized only by the delay effect of the input/output circuit, making it possible to fully utilize the high speed performance of the LSI.
第１図は、本発明のプリント基板の一実施例の概略構成
を示す要部断面図である。FIG. 1 is a sectional view of essential parts showing a schematic configuration of an embodiment of a printed circuit board of the present invention.
第１図に示すように、本実施例のプリント基板（ボード
）１００は、絶縁性のガラスエポキシ基板２１にその表
裏で異った径のスルーホール２２が設けられ、そのスル
ーホール２２にはスルーホール配線２３が設けられてい
る。そのスルーホール配、１２３と同時に配線２４が設
けられている。配線保護膜としてソルダーレジスト２５
が設けられている。As shown in FIG. 1, the printed circuit board (board) 100 of this embodiment has through holes 22 with different diameters on the front and back sides of an insulating glass epoxy substrate 21. A hole wiring 23 is provided. A wiring 24 is provided at the same time as the through-hole wiring 123. Solder resist 25 as a wiring protection film
is provided.
このプリント基板（ボード）１０ｏの上に前記ＰＧＡ型
ＬＳＩ１等を実装する際に、第６図に示すように、あら
かじめリードピン１７に予備半田２６を施こしておき、
これをスルーホール２２に高温で挿入実装し、スルーホ
ール２２内部を予備半田２６によって充填させ、裏面に
その予備半田２６を露出させる。このようにして、第７
図に示すように、プリント基板（ボード）１００の上に
前記ＰＧＡ型ＬＳＩ１等が実装される。When mounting the PGA type LSI 1 etc. on this printed circuit board (board) 10o, as shown in FIG. 6, preliminary solder 26 is applied to the lead pins 17 in advance.
This is inserted and mounted into the through hole 22 at high temperature, the inside of the through hole 22 is filled with preliminary solder 26, and the preliminary solder 26 is exposed on the back surface. In this way, the seventh
As shown in the figure, the PGA type LSI 1 and the like are mounted on a printed circuit board (board) 100.
前記スルーホール２２の断面形状は、第７図に示すよう
に、円形であり、第６図に示すように、その前記プリン
ト基板（ボード）１００のＰＧＡ型ＬＳＩ１側の径２２
Ａは、例えば、０．８〜１．３ｍｍであり、その深さは
１．５ｍｍであり、その反対側の径２２Ｂは、リードビ
ン１７の径よりも小さい径、例えば、０．４〜０．５ｍ
ｎ＋にしである。As shown in FIG. 7, the cross-sectional shape of the through hole 22 is circular, and as shown in FIG.
A is, for example, 0.8-1.3 mm, its depth is 1.5 mm, and the diameter 22B on the opposite side is smaller than the diameter of the lead bin 17, for example, 0.4-0. 5m
It's n+.
以上の説明かられかるように、本実施例によれば、プリ
ント基板（ボード）１００上のスルーホール２２に予備
半田２６を設け、その予備半田２６を高温でスルーホー
ル２２へ挿入実装することによって、スルーホール２２
内に半田を充填することができるので、温度サイクル等
によるスルーホール２２内のスルーホール配＃Ｉ２３の
断線を低減することができる。As can be seen from the above description, according to this embodiment, preliminary solder 26 is provided in the through hole 22 on the printed circuit board (board) 100, and the preliminary solder 26 is inserted and mounted into the through hole 22 at high temperature. , through hole 22
Since the inside can be filled with solder, disconnection of the through-hole wiring #I23 in the through-hole 22 due to temperature cycling or the like can be reduced.
これにより信頼性を向上することができる。This can improve reliability.
また、実装時に押し出された半田を、プリント基板（ボ
ード）１００の裏面部分より目視で接続確認検査を行う
ことができる。Further, the solder extruded during mounting can be visually inspected for connection confirmation from the back side of the printed circuit board (board) 100.
また、前記スルーホール２２のＰＧＡ型ＬＳＩＩ側の径
は、リードピン１７の先端部の径より大きくし、その反
対側の径をリードピン１７の先端部の径より小さくする
ことにより、リードピン１７が貫通しないので、大きな
スルーホールによる配線可能部分の狭小化を低減するこ
とができる。これにより、実装効率及び布線特性を向上
することができる。Further, the diameter of the through hole 22 on the PGA type LSII side is made larger than the diameter of the tip of the lead pin 17, and the diameter of the opposite side is made smaller than the diameter of the tip of the lead pin 17, so that the lead pin 17 does not penetrate. Therefore, it is possible to reduce the narrowing of the wiring area due to large through holes. Thereby, mounting efficiency and wiring characteristics can be improved.
第８図は、本発明の実施例■のＰＧＡ型ＬＳＩをプリン
ト基板（ボード）上に実装した状態を示す要部断面図で
ある。FIG. 8 is a sectional view of a main part showing a state in which a PGA type LSI according to Example 2 of the present invention is mounted on a printed circuit board (board).
本実施例■の電子装置は、実施例■の応用例であり、第
８図に示すように、第１図に示すスルーホール２２の断
面形状に傾斜を持たせ、実装するリードピンエフの先を
尖らせたものである。The electronic device of Example 2 is an application example of Example 2, and as shown in FIG. 8, the cross-sectional shape of the through hole 22 shown in FIG. It is sharp.
本実施例■によれば、スルーホール２２の断面形状に傾
斜が持たせであるため、リードビン１７を挿入実装する
際、スルーホール２２の中央にリードビン１７を導くこ
とができるので、実装位置の制御を容易にすることがで
きる。According to this embodiment (2), since the cross-sectional shape of the through hole 22 is inclined, when the lead bin 17 is inserted and mounted, the lead bin 17 can be guided to the center of the through hole 22, so that the mounting position can be controlled. can be facilitated.
第９図は、本発明の実施例■のＰＧＡ型ＬＳＩをプリン
ト基板（ボード）上に実装した状態を示す要部断面図で
ある。FIG. 9 is a sectional view of a main part showing a state in which the PGA type LSI of Example 2 of the present invention is mounted on a printed circuit board (board).
本実施例■の電子装置は、実施例１の応用例であり、ス
ルーホール２２の径をＰＧＡ型ＬＳＩＩ側とその反対側
ともに同一径にし、ソルダーレジスト２５を厚膜化する
ことによって、実施例Ｉのスルーホール２２によるリー
ドピン１７のガイドの役割を持たせたものである。The electronic device of Example 2 is an application example of Example 1, and the diameter of the through hole 22 is made the same on both the PGA type LSII side and the opposite side, and the solder resist 25 is made thicker. The through hole 22 of I serves as a guide for the lead pin 17.
本実施例■によれば、スルーホール２２の径を単一にで
きるので、プリント基板（ボード）１００の製造工程を
簡略化することができる。According to the present embodiment (2), since the diameter of the through hole 22 can be made uniform, the manufacturing process of the printed circuit board (board) 100 can be simplified.
第１０図は、本発明の実施例■のＰＧＡ型ＬＳＩをプリ
ント基板（ボード）上に実装した状態を示す要部断面図
である。FIG. 10 is a sectional view of a main part showing a state in which the PGA type LSI of Example 2 of the present invention is mounted on a printed circuit board (board).
本実施例■の電子装置は、実施例Ｉの応用例であり、ス
ルーホール２２を兼用してプリント基板（ボード）１０
０の表にＰＧＡ型ＬＳＩＩを設け、裏に表面実装型ＬＳ
Ｉ、例えばフラットパッケージ型ＬＳＩ５を設けたもの
である。The electronic device of the present embodiment (■) is an application example of the embodiment I, and the through hole 22 is also used as the printed circuit board (board) 10.
A PGA type LSII is installed on the front side of 0, and a surface mount type LS is installed on the back side.
I, for example, a flat package type LSI 5 is provided.
本実施例■によれば、ＰＧＡ型ＬＳＩＩからプリント基
板（ボード）１００のその反対側まで結線する場合、ス
ルーホール２２を兼用してプリント基板１００の表裏に
、それぞれＰＧＡ型ＬＳＩＩとフラットパッケージ型Ｌ
ＳＩ５を設けたので、配線を短くすることができる。According to this embodiment (2), when connecting a PGA type LSII to the opposite side of the printed circuit board (board) 100, the through hole 22 is also used to connect the PGA type LSII and flat package type L to the front and back sides of the printed circuit board 100, respectively.
Since SI5 is provided, the wiring can be shortened.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
例えば、前記実施例■〜■では、プリント基板（ボード
）１００の片面にＰＧＡ型ＬＳＩＩを設けた例で説明し
たが１本発明は、プリント基板（ボード）１００の表裏
両面にそれぞれピン実装型電子部品を設ける場合及びピ
ン単体をプリント基板へ立設する場合にも適用できるこ
とは勿論である。For example, in the above-described embodiments (■ to ■), an example was explained in which a PGA type LSII was provided on one side of the printed circuit board (board) 100, but in the present invention, a pin-mounted type electronic Of course, the present invention can also be applied to the case where parts are provided and when a single pin is erected on a printed circuit board.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、プリント基板のスルーホールを半田で充填す
ることにより、スルーホール部の断線が低減され信頼性
が向上する。また、実装後の接続確認検査は、スルーホ
ールの裏面部に押し出された半田を目視確認することに
より容易に行うことができる。That is, by filling the through-holes of the printed circuit board with solder, disconnections in the through-hole portions are reduced and reliability is improved. Further, the connection confirmation test after mounting can be easily performed by visually checking the solder pushed out to the back side of the through hole.
前記スルーホールの裏面側の径は、リードピンの径より
小さくしであるため、リードピンが貫通せず、スペーサ
部品を省くことができる。また、スルーホール部によっ
て配線可能部分を狭くさせられるのも改善され、実装効
率や布線特性が向上する。Since the diameter of the back side of the through hole is smaller than the diameter of the lead pin, the lead pin does not penetrate through the through hole, and a spacer component can be omitted. Furthermore, the ability to narrow the wiring area due to the through-hole portion is improved, and mounting efficiency and wiring characteristics are improved.
第１図は、本発明のプリント基板の一実施例の概略構成
を示す要部断面図
第２図は、本発明の実施例■の電子装置の全体構成の概
略を示す外観斜視図、
第３図は、第１図に示すＰＧＡ型ＬＳＩの平面図、
第４図は、第３図に示すＩＶ−ＩＶ線で切った断面図、
第５図は、同ＰＧＡ型ＬＳＩの平面図、第６図は、本実
施例Ｉのプリント基板（ボード）の上にある電子装置の
ＰＧＡ型ＬＳＩの概略構成を示す要部断面図。
第７図は、第１図に示すＯ印で囲んだ部分の拡大斜視図
、
第８図は１本発明の実施例■のＰＧＡ型ＬＳＩをプリン
ト基板（ボード）上に実装した状態を示す要部断面図、
第９図は、本発明の実施例■のＰＧＡ型ＬＳＩをプリン
ト基板（ボード）上に実装した状態を示す要部断面図、
第１０図は、本発明の実施例■のＰＧＡ型ＬＳＩをプリ
ント基板（ボード）上に実装した状態を示す要部断面図
である。
図中、１００・・・プリント基板（ボード）、工・・・
ＰＧＡ型ＬＳＩ、２・・・デュアルインラインパッケー
ジ型ＬＳＩ、３・・・メモリボード、４・・・ソケット
、５フラツトパツケージ型ＬＳＩ、１１・・・ベース、
１２・・・配線層、１３・・・半導体素子、１４・・・
金属細線、１５・・・封止ガラス、１６・・・キャップ
、１７・・・リードピン、１８・・・リード、２１・・
・ガラスエポキシ基板、２２・・・スルーホール、２３
・・・スルーホール配線、２４・・・配線、２５・・・
ソルダーレジスト、２６・・・半田である。1 is a cross-sectional view of main parts showing a schematic configuration of an embodiment of a printed circuit board of the present invention; FIG. 2 is an external perspective view showing an outline of the overall structure of an electronic device according to embodiment The figures are a plan view of the PGA type LSI shown in Fig. 1, Fig. 4 is a sectional view taken along the line IV-IV shown in Fig. The figure is a sectional view of a main part showing a schematic configuration of a PGA type LSI of an electronic device on a printed circuit board (board) of Example I. FIG. 7 is an enlarged perspective view of the part surrounded by the O mark shown in FIG. FIG. 9 is a cross-sectional view of a main part showing a state in which a PGA type LSI according to the embodiment (2) of the present invention is mounted on a printed circuit board (board), and FIG. FIG. 2 is a cross-sectional view of main parts showing a state in which a type LSI is mounted on a printed circuit board (board). In the figure, 100...Printed circuit board (board), engineering...
PGA type LSI, 2... dual inline package type LSI, 3... memory board, 4... socket, 5 flat package type LSI, 11... base,
12... Wiring layer, 13... Semiconductor element, 14...
Fine metal wire, 15... Sealing glass, 16... Cap, 17... Lead pin, 18... Lead, 21...
・Glass epoxy board, 22...Through hole, 23
...Through-hole wiring, 24...Wiring, 25...
Solder resist, 26...Solder.
Claims (4)
リント基板において、前記部品接続用スルーホールの電
子部品を実装しない側の径を電子部品のリードピン先端
部の径より小さく構成したことを特徴とする電子部品実
装用プリント基板。1. 1. A printed circuit board for electronic component mounting having through holes for connecting components, characterized in that the diameter of the side of the through holes for connecting components on which electronic components are not mounted is smaller than the diameter of the tip of a lead pin of the electronic component. Printed circuit board for mounting.
品接続用スルーホールに、当該電子部品のリードピンを
半田で面実装し、前記半田が前記部品接続用スルーホー
ルの実装面と反対側の面に露出していることを特徴とす
る電子装置。2. The lead pins of the electronic component are surface-mounted to the component connection through holes on the electronic component mounting printed circuit board according to claim 1 with solder, and the solder is applied to the surface opposite to the mounting surface of the component connection through holes. An electronic device characterized by being exposed.
め予備半田を形成し、この形成された予備半田を高温で
溶解して電子部品を面実装すると共に部品接続用スルー
ホールに半田を充填して部品接続用スルーホールの実装
面と反対側の面に半田を露出させることを特徴とする電
子装置の製造方法。3. Preliminary solder is formed in advance on the lead pins of the electronic component according to claim 2, and the formed preliminary solder is melted at high temperature to surface-mount the electronic component, and the through holes for component connection are filled with solder to connect the components. A method of manufacturing an electronic device, comprising: exposing solder on a surface opposite to a mounting surface of a through-hole.
スルーホールの反対側に露出している半田を利用して目
視接続確認検査を行うことを特徴とする電子装置の検査
方法。4. 3. A method for inspecting an electronic device according to claim 2, wherein a visual connection confirmation inspection is performed using solder exposed on the opposite side of the component connection through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29192688A JPH02137290A (en) | 1988-11-17 | 1988-11-17 | Printed circuit board for packaging electronic parts and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29192688A JPH02137290A (en) | 1988-11-17 | 1988-11-17 | Printed circuit board for packaging electronic parts and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02137290A true JPH02137290A (en) | 1990-05-25 |
Family
ID=17775251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29192688A Pending JPH02137290A (en) | 1988-11-17 | 1988-11-17 | Printed circuit board for packaging electronic parts and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02137290A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834802A (en) * | 1996-01-23 | 1998-11-10 | Nec Corporation | Metal semiconductor field effect transistors having improved intermodulation distortion using different pinch-off voltages |
| CN110678759A (en) * | 2017-05-30 | 2020-01-10 | 日本麦可罗尼克斯股份有限公司 | Electrical connection device |
-
1988
- 1988-11-17 JP JP29192688A patent/JPH02137290A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834802A (en) * | 1996-01-23 | 1998-11-10 | Nec Corporation | Metal semiconductor field effect transistors having improved intermodulation distortion using different pinch-off voltages |
| CN110678759A (en) * | 2017-05-30 | 2020-01-10 | 日本麦可罗尼克斯股份有限公司 | Electrical connection device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5280193A (en) | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate | |
| JPH01217993A (en) | Semiconductor device | |
| US6272741B1 (en) | Hybrid solder ball and pin grid array circuit board interconnect system and method | |
| JPH09289052A (en) | Packaged structure of module | |
| JPH02137290A (en) | Printed circuit board for packaging electronic parts and electronic device | |
| JPH07336030A (en) | Solder land structure for printed circuit board | |
| JPS62118555A (en) | Integrated circuit package | |
| JPS62134945A (en) | Molded transistor | |
| JPH0233960A (en) | Semiconductor device | |
| JPH01232753A (en) | Semiconductor device | |
| JPH01138791A (en) | Hybrid integrated circuit device | |
| JPS6129164A (en) | Semiconductor device | |
| JPH0739260Y2 (en) | Hybrid integrated circuit device | |
| JPH0823163A (en) | Mounting method for substrate | |
| KR100261298B1 (en) | Ball grid array test socket in a pcb packaging | |
| JPH038366A (en) | Package for semiconductor device | |
| JPH03196554A (en) | Mounting method for semiconductor device | |
| JPH01183084A (en) | Application of solder to connector | |
| JPH0519985B2 (en) | ||
| JPS62243393A (en) | Printed board | |
| JPS6352497A (en) | Wiring board | |
| JPH04345083A (en) | Printed wiring board for three-dimensional mounting and its manufacture | |
| JPH03125468A (en) | Mounting method for semiconductor integration circuit device and semiconductor integration circuit device used therefor | |
| US20060022327A1 (en) | Enhanced PGA interconnection | |
| JPH04236480A (en) | Solderless mounting connection structure of semiconductor package, and said semiconductor package |