JPH0418874A - Vertical thinning circuit - Google Patents

Abstract

PURPOSE:To generate a thinned signal so that the information of an original video signal is included without an omission by apportionment in accordance with reduction ratio by changing the selection mode of a multiplexer according to the rate of the omission of the thinned signal for reducing the input video signal. CONSTITUTION:A luminance signal is introduced to an input terminal 21, and is inputted to a delaying means in which one-line delay circuits 22,23 are connected in series, and simultaneously, it is supplied to coefficient multipliers 31,32. The output of the one-line delay circuit 22 is supplied to the coefficient multipliers 33,34, and the output of the one-line delay circuit 23 is inputted to the one-line delay circuits 35,36, and the outputs of the coefficient multipliers 31 to 36 are supplied to the multiplexers 37 to 39, and are supplied to an adder 40. Here, the multiplexers 37 to 39 are changed into the mode to select the outputs of the coefficient multipliers 31, 33, 35 and the mode to select the outputs of the coefficient multipliers 32, 34, 36. Thus, in the case of obtaining a reduced picture, the thinned signal can be generated so that the information of the original video signal is included without an omission by the apportionment in accordance with the reduction ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to a vertical interpolation circuit used in an image display device that forms a sub-playback screen within a main playback screen.

(Prior Art) Recent image display devices such as color television receivers are equipped with a picture-in-picture (PIF) function that forms a sub-playback screen within the main playback screen. There is.

The circuit that implements this PIF function utilizes digital image processing technology. This circuit uses a first video signal that becomes the main playback screen and a second video signal that becomes the sub screen, and reduces the image of the second video signal and replaces it with a part of the first video signal. ing.

When reducing the image of the second video signal, the second video signal is reduced in the vertical direction by thinning out horizontal lines, and is also reduced in the horizontal direction by thinning out pixels.

In this process, when thinning horizontal lines, the second video signal is first input to the vertical interpolation circuit to create an interpolation signal, and then this interpolation signal is divided to create a signal for the reduced screen. Creating. This is because if the line signal of the second video signal is simply thinned out as it is, a large amount of information present in the thinned out signal will be missing, resulting in an unnatural reduced image.

FIG. 4 shows a conventional vertical interpolation circuit.

After the second @image signal is digitized and subjected to luminance/color separation, the luminance signal therein is supplied to the input terminal 11. Although the chrominance signal system is not shown, since it is a circuit similar to the luminance signal system, the luminance signal system will be explained. The luminance signal at the input terminal 11 is supplied to a one-line delay circuit 12 having a delay amount of one line (one horizontal period), and is also supplied to a coefficient multiplier 14 . The output of the 1-line delay circuit 12 is further supplied to the 1-line delay circuit 13 and also to the coefficient unit 15. The output of the one-line delay circuit 13 is supplied to the coefficient multiplier 16, and each coefficient multiplier 14.
The outputs of 15 and 16 are input to the adder 17. As a result, the adder 17 obtains a scanning line signal that is a combination of three horizontal line signals.

If one out of every three scanning lines is extracted from this scanning line signal, it is possible to obtain a screen that is reduced in size to 1/3 in the vertical direction. Furthermore, if one out of every two scanning lines is extracted, a screen that is reduced in size to 1/2 in the vertical direction can be obtained.

(Invention or Section to be Solved Wi) As mentioned above, according to the conventional vertical interpolation circuit, three signals are multiplied at a constant rate, that is, to create one line signal from three lines. The coefficients used are always constant to create an interpolated signal (in the example of FIG. 4, the coefficient value of each coefficient unit is, for example, 1/3).

However, in the PIF circuit, the size of the sub-playback screen is not always fixed with respect to the main playback screen. For example, if the vertical ratio of the main playback screen is 1/2, it may be switched to 1/3. This is possible by switching the thinning rate of the interpolated signal.

In the case of a PIF circuit that can switch the size of the sub-playback screen in this way, with the conventional interpolation signal creation method, it may not be possible to obtain a sub-playback screen that feels like it is uniformly reduced by averaging the second video signal. .

In the vertical interpolation circuit shown in FIG. 4, when the second video signal is reduced to ⅓ in the vertical direction, an average reduction can be obtained. In other words, the information of each scanning line of the original second video signal is uniformly included. However, when reducing the size to 1/2, the interpolated signal is thinned out at a rate of 1 in 2, but the original information (information of the second video signal) is thinned out for the resulting scanning line signal. ) may not be included evenly, resulting in an unnatural reduced image.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a vertical interpolation circuit that can create an interpolation signal so that when obtaining a reduced image, the information of the original video signal is not omitted and is distributed in accordance with the reduction ratio. do.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a delay means to which a video signal is supplied and a plurality of one-line delay circuits connected in series, and an Nth one-line delay circuit of the delay means. At least two or more first coefficient multiplier groups each having a different coefficient value are supplied with the signal at the input section of the input section, and the signal at the output section of the Nth 1-line delay circuit of the 1-line delay circuit is supplied, respectively. a second coefficient unit group of at least two or more coefficient units having different coefficient values;
The system includes a multiplexer that selects and derives the output of one coefficient unit from each group of coefficient units, and an adder that adds the outputs of this multiplexer and derives the result as a vertical interpolation signal.

(Function) By using the above means, if the selection mode of the multiplexer is switched according to the thinning rate of the interpolation signal in order to reduce the input video signal, the video signal for the reduced screen that evenly contains the information of the input video signal can be generated. can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A digitized luminance signal is introduced into the input terminal 2], inputted to delay means connected in series with a plurality of one-line delay circuits 22 and 23, and also supplied to, for example, two coefficient multipliers 31 and 32. The one-line delay circuits 22 and 23 have a delay amount of one horizontal period. The output of the one-line delay circuit 22 is sent to the coefficient multiplier 33.
34. Further, the output of the 1-line delay circuit 23 is input to 1-line delay circuits 35 and 36. Coefficient unit 3
1.32 is fed to a multiplexer 37, the outputs of the coefficient multipliers 33, 34 are fed to a multiplexer 38, and the outputs of the coefficient multipliers 35, 36 are fed to a multiplexer 39. The outputs of multiplexers 37, 38, 39 are then supplied to adder 40.

Here the multiplexer 37, 38, 39 has the control terminal 4
2, the coefficient multiplier 31.33
．． 35 (first group) output selection mode and coefficient unit 3
The mode is switched to select the output of 2.34.36 (second group).

The coefficient values of the first group coefficient multiplier 3], 33.35 are, for example, 1/2.1/2.0, and the coefficient values of the second group coefficient multiplier 32.34 are, for example, 1/2.1/2.0.
．． Each of the 36 coefficient values is 1/3.2/3.1/3.

The above embodiment is an example of a system in which the vertical reduction ratio can be switched between, for example, 1/2 and 1/3.

When the first group of coefficient units is selected, if one out of every two signals is thinned out from the interpolation signal derived to the output terminal 41 of the adder 40, it is suitable for reducing the screen by half in the vertical direction. It is possible to obtain a video signal. When the second group of coefficient units is selected, by thinning out one out of three signals from the interpolation signal derived to the output terminal 41, a video signal suitable for vertical screen reduction by 1/3 can be obtained. I can do it.

FIG. 2 shows the relationship between the input luminance signal, the output luminance signal, and the luminance signal resulting from thinning when the first group of coefficient multipliers is selected, and its internal components.

FIG. 3 shows the relationship between the input luminance signal, the output luminance signal, and the decimation-resulted luminance signal and its internal components when the second group of coefficient multipliers is selected. As can be seen from this explanatory diagram, the components of the luminance signal obtained as a result of thinning include all components of the input luminance signal according to the thinning ratio (vertical reduction ratio), and the proportion is has been done. Furthermore, when the position to which the greatest weight is applied is as shown in FIG. 3, this distribution is obtained at an interval of one in three lines, and the weights are symmetrically weighted vertically. Therefore, the reduced screen can also give a uniform feeling of reduction.

In the above embodiment, an example was explained in which a screen reduction of 1/2.1/3 is obtained, but it is possible to further increase the number of coefficient units and select each coefficient unit according to switching of the reduction ratio. Of course, it is possible.

[Effects of the Invention] As explained above, in the present invention, when obtaining a reduced image, it is possible to create an interpolation signal so that the information of the original video signal is not omitted and is distributed in accordance with the reduction ratio.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams for explaining the operation of the circuit in FIG. 1, and FIG. 4 is a circuit diagram showing a conventional vertical interpolation circuit. FIG. 22.23...1 line delay circuit, 31-36...
Coefficient unit, 37.38.39...Multiplexer, 40-Adder. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] Delay means to which a video signal is supplied and a plurality of one-line delay circuits connected in series, and a signal from an input section of the Nth one-line delay circuit of the delay means to which coefficient values are respectively supplied. At least two or more different first coefficient units; and at least two or more second coefficient units each having a different coefficient value and each of which is supplied with a signal from the output section of the Nth one-line delay circuit among the one-line delay circuits. A group of coefficient units, a multiplexer that selects and derives the output of one coefficient unit from each of the first and second coefficient unit groups, and adds the outputs of this multiplexer to derive a vertical interpolation signal. A vertical interpolation circuit characterized by comprising an adder.