JPH04188489A - Storage device - Google Patents

Abstract

PURPOSE:To effectively distribute a built-in memory according to the request of various systems by installing a first readout and write circuit and a second readout and write circuit which respectively read out from and write to memory cells which have been connected to a plurality of bit lines, on one side each, which have been divided into two by using one out of a plurality of bit-line dividing means. CONSTITUTION:A first readout and write circuit and a second readout and write circuit which respectively read out from and write to memory cells which have been connected to a plurality of bit lines, on one side each, which have been divided into two by using one out of a plurality of bit-line dividing means. In this case, e.g. a memory cell array 1 divides a memory cell into three blocks in 64 words each. A memory cell 64 can change the allocation ratio of a data space and an instrauction space as a word unit. Thereby, a memory can be constitutted according to the request of a logic system to be used.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device having a plurality of memory spaces.

[Conventional technology]

A microprocessor that has a data space and an instruction space as separate address spaces is generally referred to as a microprocessor with an l\-node architecture, and is used in digital signal processing processors (hereinafter referred to as DSP), etc. . These SPs tend to include internal data and instruction memories in order to speed up processing and reduce costs, but there is a limit to the memory capacity that can be mounted on a single DSP chip. Therefore, it becomes necessary to effectively allocate data memory and instruction memory.

FIG. 3 is an address map showing the memory space shown in the user's manual of Texas Instruments grTMs32020J, which is an example of a conventional DSP.

As shown in the figure, the rTMs32020'J has a data space 101°, an instruction space 1
It has three independent memories of 02 and I10 spaces 1.03.

Memory blocks Bl (256 words) and B2 (32 words)
Word) is data memo 1. used only as 2
The 56-word memory block BO can be used as both data memory and instruction memory.

When using memory block BO (256 words) as a data memory, by executing the "CNFD" instruction on the TMS32020 software, as shown in FIG. 3(a), and when using as an instruction memory. By executing the “CNFP” command, the third
As shown in Figure (b), each memory block BO can be defined as either a data memory or an instruction memory.

[Problem to be solved by the invention]

As described above, in conventional storage devices, the capacity of built-in memory that can be allocated to the data space or instruction space is fixed.
Even if it was desired to allocate 64 words to the data space and 192 words to the instruction space, it was only possible to allocate all 256 words to some space.

In order to increase the degree of freedom in memory allocation of built-in memories, it is necessary to increase the number of possible built-in memories for allocation according to the degree of freedom. However, if the built-in memory is increased, it is necessary to provide an increased number of sense amplifiers and write drivers, which requires the addition of a large amount of hardware.

The present invention has been made to solve the above-mentioned problems, and aims to provide a storage device with a high degree of freedom in allocating built-in memory without significantly adding hardware.

[Means to solve the problem]

A memory device according to the present invention includes a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged for each memory cell in each row, and a plurality of bit lines arranged for each memory cell in each column. a plurality of bit line dividing means for dividing a plurality of bit lines into the same row of a plurality of memory cells; and one of the plurality of dividing means. a first access means for accessing a memory cell connected to one of the plurality of bit lines divided into two, and a first access means of the plurality of dividing means;
and second access means for accessing a memory cell connected to the other of the plurality of bit lines divided into two by one bit line.

[Effect]

In this invention, a memory having a plurality of memory cells arranged in a matrix, a plurality of word lines arranged for each memory cell in each row, and a plurality of bit lines arranged for each memory cell in each column. In the apparatus, the plurality of bit lines are divided in the same row of memory cells by activating any one of the plurality of bit line dividing means, and the eighteenth access means divides the plurality of bit lines by one of the plurality of dividing means. accessing a memory cell connected to one of the plurality of bit lines divided into two, and the plurality of bit lines divided into two by one of the plurality of dividing means by a second access means; Since the memory cells connected to the other one of the memory cells are accessed, the ratio of memory cells accessed by the first access means and the second access means can be made variable.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention.

In the memory cell array 1, blocks of memory cells MO to MO7, blocks of memory cells MIO to M17, and blocks of memory cells M20 to M27 are arranged, each block having a capacity of 64 words.

Therefore, the total capacity of memory cell array 1 is 192 words.

Furthermore, memory cells MOO to MO3 in the same row are connected to the word line WO, and memory cells MO4 to MO7 are connected to the word line W.
1, the memory 10 M1 to M]3 is the word line W2.
Memory cells M14 to M17 are connected to word line W3, memory cells M20 to M23 are connected to word line W4, and memory cells M24 to M27 are connected to word line W5.

Furthermore, memory cells MOO to M24 in the same column are connected to N channel transfer gates (hereinafter referred to as N ch, T, G,
It is called. ) To the bit line BO through T10 and T20, memory cells Mol to M2S or N ch, T, G,
T 1 ] and T21 to bit line B1, memory cells MO2 to M26 are connected to N cb, T, G, T12.
and memory cell MO3 to bit line B2 via T22.
or M27 or N ch, T, G, T 1.3 and T
It is connected to bit line B3 via 2B.

At one end of the bit lines BO to B3, Nch, T,
A sense amplifier and write driver 13 for inputting and outputting the data bus 17 via G, TOO or TO3,
At the other end of the bit lines BO to B3, Nch, T,
A sense amplifier and write driver 15 for inputting and outputting command data t<S 19 are connected via G and T30 to T33.

Further, word lines WO and Wl are connected to an address decoder 10, word lines W2 and W3 are connected to an address decoder 11, and word lines W4 and W5 are connected to an address decoder 12.

The MACR decoder 2 receives a first output 31 and a second output 32 of a MACR (memory assignment control I register) 3, and outputs a first output of a NOR circuit 6 to an inverting circuit 4.
The first output 3 of the MACR3 inverted by the inverting circuit 5 is given to the second output, the second output 32 of the MACR3 inverted by the inversion circuit 5 is supplied to the first output of the NOR circuit 7, and the first output 31 of the MACR3 is supplied to the first output of the NOR circuit 7. MACR3 inverted by the inversion circuit 5 to the second human power
The first output 31 of the MACR3 inverted by the inverting circuit 4 is given to the first power of the NOR circuit 8, the second output 32 of the MACR3 is given to the second power, and the second output 32 of the MACR3 is given to the first power of the NOR circuit 8. The first output 31 of the MACR3 is given to the first human power, and the second output 32 of the MACR3 is given to the second human power.

The divided signal line MACROO, which is the output of the NOR circuit 6, is N
ch, T, G, T 00 to TO4 gate,
The divided signal line MACRO1, which is the output of the NOR circuit 7, is N
ch, T, G, T10 to T14 gate,
The divided signal line MACRIO, which is the output of the NOR circuit 8, is N
ch, T, G, T 20 to T24 gate,
The divided signal line MACR11 which is the output of the NOR circuit 9 is N
They are connected to the gates of ch, T, G, and T30 to T34, respectively.

Also, between N ch, T, G, T O4, 14, N c
h, T, GT14. Between T24, N ch, T, G, T2
4. Connected between T34, N ch, T, G,
The signal line between T04 and T1.4 goes to the address decoder 1o, the signal line between Nch, T, G, T]1 and T24 goes to the address decoder 11, Nch, T, G, T
A signal line between T24 and T34 is connected to address decoder ]2.

Furthermore, the other terminal of Nch, T, G, T04 is connected to the address input port 14 for inputting the data address bus [8], the other terminal of Nch, T, G, T34 or the command address bus 2o. are respectively connected to address input ports 16 for inputting.

Note that the word line between the word lines WO and Wl and the memory cells associated therewith, the word line between the q-domain lines w2 and W3 and the memory cells associated therewith, and the word lines between the word lines W4 and W5 and the memory cells associated therewith are as follows. Omitted.

Furthermore, the bit lines between bit lines B1 and B2 and the associated memory cells are omitted.

Next, the operation will be explained. Table 1 is a table showing the relationship between the contents of MACR3 and divided signal lines MACROO to MACR1,1.

Table 1 As shown in Table 1, the first horn 31 and the second horn of MACR3
When the combination of output 32 is “oo”, the divided signal line M
Only ACROO is 0”, and the output combination is O]
”, only the divided signal line MACRO1 becomes “0”,
When the output combination is 10”, the divided signal line MACR
Only IO is “0” and the output combination is “11”
At this time, only the divided signal line MACRII becomes "0".

Now, when the divided signal line πτ11] becomes 0', Nch,
T, G, T00 to TO4 become non-conductive, and the sense amplifier and write driver 13 and bit lines BO to 8
3 and address input port 14 and Nch, T, G,
T04 is divided.

Therefore, the data bus 17 and data address bus 18, which are input to the sense amplifier and write driver] 3 and the address input port 14, respectively, cannot provide address signals and data signals to the memory cell array 1.

On the other hand, the command data path control 9 and the command address bus 20, which are respectively input to the sense amplifier and write driver 15 and the address J port 16, are connected to all the memory cells MOO to MO7, MI in the memory cell array 1.
A total of 192 bytes, O to M17 and M2O to M27, can be accessed.

At this time, address decoders 10 to 12 are used for instruction space.

Next, the divided signal line MACRO1 becomes O°.
Nch, T, G, T1.0 to T14 become non-conductive, and bit lines BO to 80 between word lines W1 and W2
3 is divided.

Therefore, the data bus core and data address bus 18 inputted to the sense amplifier and write driver] 3 and the address input port 14, respectively, can access 64 bytes of memory cells MOO to MO7 in the memory cell array 1.

On the other hand, the command data bus 19 and command address bus 20, which are input to the sense amplifier and write driver 15 and the address input port 16, respectively, are connected to a total of 128 memory cells M1.0 to M17 and M2O to M27 in the memory cell array 1. bytes can be accessed.

At this time, address decoder 1o is used for data space, and address decoders 11 and 12 are used for instruction space.

Next, when the divided signal lines MACR1, MACR0 become “0”, N
ch, T, G, T20 to T24 become non-conductive,
Bit lines BO to 803 between word lines W3 and W4 are divided.

Therefore, the data bus 17 and data address bus 18 input to the sense amplifier and write driver 13 and the address input port 4 respectively carry a total of 1 to 28 bytes of memory cells MOO to M07 and MIO to M17 in the memory cell array 1. can be accessed.

On the other hand, the sense amplifier and write driver 15 and the command data bus 19 and command address bus 2 which are respectively input to the address input port 16 can access 64 hides of memory cells M20 to M27 in the memory cell array 1. .

At this time, address decoders 10 and 11 are used for the data space, and address decoder 12 is used for the instruction space.

Finally, when the divided signal line MACRII becomes O'', Nc
h, T, G, T 30 to T34 become non-conductive, and between the sense amplifier and write driver 15 and bit lines BO to 83 and between the address input port 14 and N ch, T,
The area between G and T 34 is divided.

Therefore, the data bus 17 and the data address bus 18, which are respectively input to the sense amplifier and write driver 13 and the address input port]4, connect all memory cells MOO to MO7, MI in the memory cell array 1.
A total of 192 bytes, O to M17 and M2O to M27, can be accessed.

On the other hand, the command data bus 19 and the command data address bus 20, which are connected to the sense amplifier and write driver 15 and the address power port 6, respectively, cannot provide address signals and data signals to the memory cell array 1.

At this time, address decoders 10 to 12 are used for data space.

Therefore, depending on the output contents of MACR3, 192 words of memory cells can be arbitrarily allocated to the data space and instruction space in units of 64 words.

Table 2 shows the first output 31 and second output 32 of MA CR3.
3 is a table showing the relationship between data memory capacity and instruction memory capacity according to combinations of .

Table 2 As shown in Table 2, the first output 31 and the second output of MACR3
When the output 32 is ``OO'', the capacity of the data memory is O words, and the capacity of the instruction memory is 192 words. Become.

Further, when the combination of the first output 3] and the second output 32 of MA CR3 is "01", that is, the divided signal line MA
If only CROI is 0, the data memory capacity is 64
The capacity of word and instruction memory is 128 words.

Furthermore, the first output 31 and the second output 32 of MA CR3
When the combination of is “10”, that is, the divided signal line M
When only ACRIO is “0°, the data memory capacity is”
28 words, and the instruction memory capacity is 64 words.

Finally, when the combination of the first output 31 and the second output 32 of MACR3 is "11", that is, the divided signal line MA
When CRII is only or “0”, the data memory capacity is 19
2 words, and the instruction memory capacity is 0 words.

FIG. 2 shows the divided signal line MACROO shown in Table 1.

MacRo 1. The memory allocation of data space and instruction space according to the state of MAcRl 0 and MACRII is an address map indicating the state.

In this figure, an example will be explained in which the memory addresses of the instruction space are from address FF40 to address FFFF, and the memory addresses of the data space are from address 0200 to address 028F.

This memory address is address human port 14 and 16
By changing the address pattern input to , other addresses can be set.

First, when the divided signal line MACROO goes to the "L" level, as shown in FIG. 2(a), there are 192
Bytes (from address FF40 to address FFFF) are implemented, and no memory is implemented in the data space.

Next, when the divided signal line MACROI goes to "L" level, as shown in FIG. 2(b), 28 hides (from address FF80 to address FFFF) are implemented in the instruction space, and 64 bye) (from address 0200 to 02
(up to 3F address) will be implemented.

Next, when the divided signal line MACRIO goes to "L" level, 64 hides (from address FFC0 to address FFFF) are implemented in the instruction space, as shown in FIG. 2(c).
The data space has 128 bytes (0200 to 027
(up to address F) is implemented.

Finally, when the divided signal line MACRII goes to "L" level, no memory is installed in the instruction space and 192 bytes (020
0 to 028F) are implemented.

As described above, according to this embodiment, the memory capacity of the data memory space and the instruction memory space can be distributed in units of 64 words using MACR3, so that ]9
The memory capacity of 2 words can be allocated from 0 to 192 words every 64 words depending on the needs of data memory space and instruction memory space.

Further, by configuring MACR3 as a register and setting a value in this register by a program, the built-in memory can be used effectively.

In this example, the configuration of MACR3 is 2 bits, the memory allocation has 4 states, and the unit of memory allocation is 64 words, but the configuration of MACR3 is changed and the memory allocation has more states. By doing this, it is possible to create a memory configuration with a large degree of freedom and a detailed memory increase/decrease unit.

Further, the type of memory may be ROM or RAM, and the two spaces to be divided are not limited to the instruction space and the data space.

〔Effect of the invention〕

As described above, according to the present invention, there are a plurality of memory cells arranged in a matrix, a plurality of word lines arranged for each memory cell in each row, and a plurality of word lines arranged for each memory cell in each column. a plurality of bit line dividing means for dividing a plurality of bit lines by the same row of memory cells, any one of which is selectively activated in a storage device having a bit line; and one of the plurality of dividing means. a first access means for accessing a memory cell connected to one of the plurality of bit lines divided into two by the plurality of bit lines; and a plurality of bits divided into two by one of the plurality of division means. A second access means for accessing a memory cell connected to the other one of the lines is provided, so that the first . This has the advantage that the number of memory cells that can be accessed by the second access means can be varied depending on the purpose.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a memory device according to the present invention, in which 1 is a memory cell array, 2 is a MACR decoder, and 3 is a memory cell array.
MACR114 and 16 are address input ports, MO
O to MO7, Ml, 0 to Ml7 and M2O to M27 are memory cells, TOO to T3B are N-channel transfer gates, MACROO to MACRl
, 1 are divided signal lines. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A memory having a plurality of memory cells arranged in a matrix, a plurality of word lines arranged for each of the memory cells in each row, and a plurality of bit lines arranged for each of the memory cells in each column. a plurality of bit line dividing means, one of which is selectively activated, dividing the plurality of bit lines by the same row of the memory cells; and one of the plurality of dividing means. a first access means for accessing a memory cell connected to one of the plurality of bit lines divided into two; and a first access means for accessing a memory cell connected to one of the plurality of bit lines divided into two; and the plurality of bit lines divided into two by one of the plurality of dividing means. a second access means for accessing a memory cell connected to the other of the bit lines.